`
`The #1, easy-to-read, math-free introduction to
`semiconductor processing
`
`Perfect for training, teaching, & vo-tech
`
`Updnted with new cleaning techniques, packing
`technolo~es, & fabrication methods
`
`FOURTH EDITION
`
`Microchip
`Fabrication
`
`A Practical Guide to
`SEMICONDUCTOR PROCESSING
`
`PETER VAN ZANT
`
`Elm Exhibit 2158
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00387
`
`
`
`Elm Exhibit 2158, Page 2
`
`Elm Exhibit 2158, Page 2
`
`
`
`Microchip
`Fabrication
`
`Elm Exhibit 2158, Page 3
`
`
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`
`Elm Exhibit 2158, Page 4
`
`
`
`Microchip
`Fabrication
`
`A Practical Guide to Semiconductor Processing
`
`Peter Van Zant
`
`Fourth Edition
`
`McGraw-Hill
`New York San Francisco Washington, D.C. Auckland Bogotd
`Caracas Lisbon London Madrid Mexico City Milan
`Montreal New Delh, San Juan Singapore
`Sydney Tokyo Toronto
`
`Elm Exhibit 2158, Page 5
`
`
`
`Library of Congress Cataloging-in-Publication Data
`
`Van Zant, Peter.
`Microchip fabrication : a practical guide to semiconductor processing / Peter Van
`Zant.--4th ed.
`p. cm.
`Includes bibliographical references and index.
`ISBN 0-07-135636-3
`1. Semiconductors--Design and construction.
`TK7871.85.V36 2000
`621.3815’2--dc21
`
`I. Title.
`
`00-02317
`
`McGraw-Hill
`
`A Division of TheMcGraw.Hill Companies
`
`Copyright © 2000, 1997, 1984 by The McGraw-Hill Companies, Inc. All
`rights reserved. Printed in the United States of America. Except as
`permitted under the United States Copyright Act of 1976, no part of
`this publication may be reproduced or distributed in any form or by any
`means, or stored in a data base or retrieval system, without the prior
`written permission of the publisher.
`
`2 3 4 5 6 7.8 9 0 DOC/DOC 0 9 8 7 6 5 4 3 2 10
`
`ISBN 0-07-135636-3
`
`The sponsoring editor for this book was Stephen Chapman and the
`production supervisor was Sherri Souffrance. It was set in Century
`Schoolbook by Pro-Image Corporation.
`
`Printed and bound by R. R. Donnelley & Sons Company.
`
`This book is printed on recycled, acid-free paper containing
`a minimum of 50% recycled, de-inked fiber.
`
`Information contained in this work has been obtained by The Mc-
`Graw-Hill Companies, Inc. ("Mc-Graw-Hill’) from sources be-
`lieved to be reliable. However, neither McGraw-Hill nor its au-
`thors guarantee the accuracy or completeness of any information
`published herein, and neither McGraw-Hill nor its authors shall
`be responsible for any errors, omissions, or damages arising out
`of use of this information. This work is published with the un-
`derstanding that McGraw-Hill and its authors are supplying in-
`formation but are not attempting to render engineering or other
`professional services. If such services are required, the assistance
`of an appropriate professional should be sought.
`
`Elm Exhibit 2158, Page 6
`
`
`
`Many thanks to Mary DeWitt, my ever patient and supportive
`wife, and my sons, Patrick, Jeffrey, and Stephen. They have all
`brought great joy to my life and all have managed to live through
`the demands of my microelectronics career. Thank you.
`
`Elm Exhibit 2158, Page 7
`
`
`
`Contents
`
`Preface xv
`
`Chapter 1. The Semiconductor Industry
`
`Overview
`Objectives
`Birth of an Industry
`The Solid State Era
`Integrated Circuits (I.C.’s)
`Process and Product Trends
`Industry Organization
`Stages of Manufacturing
`The Development Decade (1951-1960)
`The Processing Decade (1961-1970)
`The Production Decade (1971-1980)
`The Automation Decade (1981-1990)
`The Production Era (1991-2000)
`The Nano Era
`Key Terms
`Review Questions
`References
`
`Chapter 2. Semiconductor Materials and Process Chemicals
`
`Overview
`Objectives
`Atomic Structure
`The Periodic Table of the Elements
`Electrical Conduction
`Dielectrics and Capacitors
`Intrinsic Semiconductors
`Doped Semiconductors
`Electron and Hole Conduction
`
`1
`1
`1
`3
`4
`5
`11
`13
`16
`18
`19
`2O
`20
`22
`23
`23
`23
`
`25
`
`25
`25
`26
`27
`29
`30
`31
`31
`34
`
`vii
`
`Elm Exhibit 2158, Page 8
`
`
`
`viii Contents
`
`Carrier Mobility
`Semiconductor Production Materials
`Semiconducting Compounds
`Silicon Germanium
`Ferroelectric Materials
`Process Chemicals
`States of Matter
`Plasma State
`Properties of Matter
`Pressure and Vacuum
`Acids, Alkalis, and Solvents
`The Safety Material Data Sheet
`Key Terms and Concepts
`Review Questions
`References
`
`Chapter 3. Manufacturing Wafers
`
`Overview
`Objectives
`Introduction
`Semiconductor Silicon Preparation
`Crystalline Materials
`Crystal Orientation
`Crystal Growth
`Crystal and Wafer Quality
`Wafer Preparation
`Wafer Slicing
`Wafer Marking
`Rough Polish
`Chemical Mechanical Polishing |CMP)
`Backside Processing
`Double-Sided Polishing
`Edge Grinding and Polishing
`Wafer Evaluation
`Oxidation
`Packaging
`Epi on Silicon Wafers
`Key Terms
`Review Questions
`References
`
`Chapter 4. Overview of Wafer Fabrication
`
`Overview
`Objectives
`Goal of Wafer Fabrication
`
`36
`37
`37
`38
`38
`39
`41
`42
`42
`43
`45
`47
`47
`47
`43
`
`49
`
`49
`49
`50
`50
`51
`52
`53
`57
`59
`61
`62
`62
`63
`64
`64
`64
`65
`65
`65
`66
`66
`66
`67
`
`69
`
`69
`69
`70
`
`Elm Exhibit 2158, Page 9
`
`
`
`Wafer Terminology
`Basic Wafer-Fabrication Operations
`Manufacturing Semiconductor Devices and Circuits
`Example Fabrication Process
`Chip Terminology
`Wafer Sort
`Packaging
`Summary
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 5. Contamination Control
`
`Overview
`Objectives
`Introduction
`The Problem
`Contamination Sources
`Clean-Room Construction
`Clean-Room Materials and Supplies
`Clean-Room Maintenance
`Wafer Surface Cleaning
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 6. Process Yields
`
`Overview
`Objectives
`Yield Measurement Points
`Accumulative Wafer-Fabrication Yield
`Wafer-Fabrication Yield Limiters
`Wafer-Sort Yield Factors
`Assembly and Final Test Yields
`Overall Process Yields
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 7. Oxidation
`
`Overview
`Objectives
`Silicon Dioxide Layer Uses
`
`Contents ix
`
`70
`71
`75
`79
`82
`82
`85
`85
`86
`86
`86
`
`87
`
`87
`87
`88
`88
`92
`101
`114
`114
`115
`130
`130
`131
`
`133
`
`133
`133
`133
`134
`136
`141
`149
`149
`151
`151
`152
`
`153
`
`153
`153
`154
`
`Elm Exhibit 2158, Page 10
`
`
`
`x Contents
`
`Thermal Oxidation Mechanisms
`Thermal Oxidation Methods
`Horizontal Tube Furnaces
`Vertical Tube Furnaces
`Fast Ramp Furnaces
`Rapid Thermal Processing (RTP)
`High-Pressure Oxidation
`Oxidation Processes
`Postoxidation Evaluation
`Anodic Oxidation
`Thermal Nitridation
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 8. Basic PatterningmSurface Preparation to Exposure
`
`Overview
`Objectives
`Introduction
`Overview of the Photomasking Process
`Ten-Step Process
`Basic Photoresist Chemistry
`Photoresist Performance Factors
`Comparison of Positive and Negative Resists
`Physical Properties of Photoresists
`Phot’omasking Processes
`Surface Preparation
`Photoresist Spinning
`Soft Bake
`Alignment and Exposure
`Aligner System Comparison
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 9. Basic PatterningmDeveloping to Final Inspection
`
`Overview
`Objectives
`Development
`Hard Bake
`Develop Inspect
`Etch
`Wet Etching
`¯ Dry Etch
`Resist Stripping
`
`157
`163
`164
`177
`179
`179
`183
`185
`186
`188
`188
`189
`189
`190
`
`193
`
`193
`193
`194
`195
`197
`198
`203
`207
`209
`213
`213
`217
`222
`227
`239
`240
`240
`240
`
`243
`
`243
`243
`243
`250
`252
`256
`256
`263
`270
`
`Elm Exhibit 2158, Page 11
`
`
`
`Final Inspection
`Mask Making
`Summary
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 10. Advanced Photolithography Processes
`
`Overview
`Objectives
`Issues of VLSI/ULSI Patterning
`Optical Resolution Control
`Other Exposure Issues
`Pellicles
`Surface Problems
`Antireflective Coatings
`Planarization
`Photoresist Process Advances
`CMP Summary
`Improving Etch Definition
`Self-Aligned Structures
`Etch Profile Control
`The End of Optical Lithography?
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 11. Doping
`
`Overview
`Objectives
`Definition of a Junction
`Formation of a Doped Region
`Formation of a Doped Region and Junction by Diffusion
`Diffusion Process Steps
`Deposition
`Drive-in-Oxidation
`Introduction to Ion Implantation
`Concept of Ion Implantation
`Ion Implantation System
`Dopant Concentration in Implanted Regions
`Evaluation of Implanted Layers
`Uses of Ion Implantation
`The Future of Doping
`Key Concepts and Terms
`
`Contents xi
`
`274
`274
`277
`278
`278
`279
`
`281
`
`281
`281
`281
`283
`288
`292
`294
`295
`297
`298
`308~
`313
`314
`314
`315
`316
`316
`316
`
`319
`
`319
`319
`319
`320
`321
`326
`326
`335
`337
`340
`340
`348
`352
`354
`355
`356
`
`Elm Exhibit 2158, Page 12
`
`
`
`xii Contents
`
`Review Questions
`References
`
`Chapter 12, Deposition
`
`Overview
`Objectives
`Introduction
`Chemical Vapor Deposition Basics
`CVD Process Steps
`CVD System Types
`Atmospheric Pressure CVD Systems
`Low-Pressure Chemical Vapor Deposition (LPCVD)
`Plasma-enhanced CVD (PECVD)
`Vapor Phase Epitaxy (VPE)
`Molecular Beam Epitaxy (MBE)
`Metalorganic CVD (MOCVD)
`Deposited Films
`Deposited Semiconductors
`Epitaxial Silicon
`Polysilicon and Amorphous Silicon Deposition
`SOS and SOl
`Insulators and Dielectrics
`Conductors
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 13. Metallization
`
`Overview
`Objectives
`Introduction
`Conductors-Single Level Metal
`Conductors-Multilevel Metal Schemes
`Conductors
`Metal Film Uses
`Deposition Methods
`Vacuum Pumps
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 14, Process and Device Evaluation
`
`Overview
`Objectives
`
`356
`356
`
`359
`
`359
`359
`359
`363
`366
`366
`367
`371
`373
`376
`377
`378
`379
`380
`380
`386
`388
`389
`392
`393
`393
`393
`
`395
`
`395
`395
`396
`396
`397
`398
`405
`407
`416
`422
`422
`424
`
`427
`
`427
`427
`
`Elm Exhibit 2158, Page 13
`
`
`
`Introduction
`Wafer Electrical Measurements
`Physical Measurement Methods
`Layer Thickness Measurements
`Junction Depth
`Critical Dimensions (CD) and Line Width Measurements
`Contamination and Defect Detection
`General Surface Characterization
`Contamination Identification
`Device Electrical Measurements
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 15. The Business of Wafer Fabrication
`
`Overview
`Objectives
`Fabrication and Factory Economics Overview
`Wafer-Fabrication Costs
`Equipment
`Cost of Ownership
`Automation
`Factory-Level Automation
`Equipment Standards
`Statistical Process Control (SPC)
`Inventory Control
`Line Organization
`Key Concepts and Terms
`Review Questions
`References
`
`Contents
`
`428
`429
`434
`435
`440
`443
`446
`453
`454
`457
`466
`467
`467
`
`469
`
`469
`469
`470
`471
`477
`479
`480
`483
`485
`487
`492
`494
`496
`496
`496
`
`Chapter 16. Semiconductor Devices and Integrated Circuit Formation 499
`
`Overview
`Objectives
`Semiconductor-Device Formation
`Integrated-Circuit Formation
`Superconductors
`Microelectromechanical systems (MENS)
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 17. Integrated Circuit Types
`
`Overview
`Objectives
`
`499
`499
`499
`518
`529
`530
`536
`537
`537
`
`539
`
`539
`539
`
`Elm Exhibit 2158, Page 14
`
`
`
`xiv Contents
`
`Introduction
`Circuit Basics
`Integrated-Circuit Types
`Wafer Scale Integration
`The Next Generation
`Key Concepts and Terms
`Review Questions
`References
`
`Chapter 18. Packaging
`
`Overview
`Objectives
`Introduction
`Chip Characteristics
`Package Functions and Design
`Overview of Packaging Operations
`Packaging Processes
`Package Process Flows
`Package/Bare Die Strategies
`Package Design
`Package Type/technology Summary
`Key Concepts and Terms
`Review Questions
`References
`
`Glossary
`
`Index 615
`
`539
`540
`542
`552
`553
`554
`554
`555
`
`557
`
`557
`557
`557
`558
`560
`561
`567
`584
`585
`586
`591
`592
`592
`592
`
`595
`
`Elm Exhibit 2158, Page 15
`
`
`
`Preface
`to the Fourth Edition
`
`Little did I think in 1984 that Microchip Fabrication would continue
`into a fourth edition. Yet with the supportive guidance of McGraw-Hill
`and my editor Steve Chapman here is the new edition. Readers will
`note that this edition was written sooner than the usual time for major
`technical books. To microchip professionals and observers the reason
`is obvious: the pace of technical change in this industry is increasing,
`not slowing down.
`I’ve tried to purge the previous edition of old and minor process
`descriptions and replace them with new ones. The advent of copper
`technology and multilevel metallization has spawned a number of new
`process steps. As reported in the first three editions, some day optical
`imaging will be replaced by other technologies. It is still a true state-
`ment, but clever engineers have continued to wring smaller and
`smaller images out of optical technology. Someday I will get to drop
`this imaging technique from the book, but probably not soon.
`The chapter subjects are essentially the same as the previous edi-
`tion with the exception of placing the Overview of Wafer Fabrication
`as Chapter 4. This switch was intended to give the reader a grounding
`in the basics of processing before tackling the process specific chapters.
`The Semiconductor Industry Association is reporting that soon the
`industry will soon be producing the equivalent of one billion transis-
`tors for each person on earth. With this type of growth we can expect
`many more years of advances in this industry. In the mean time the
`physics, chemistry, and electronics of integrated circuit operation and
`semiconductor processing are still valid and this fourth edition is fo-
`cused on these foundations.
`I wish to thank Anne Miller, Semiconductor Services, Jim Hayes,
`Consultant, and David Hata, of Portland Community College for sug-
`
`XV
`
`Elm Exhibit 2158, Page 16
`
`
`
`xvi Preface
`
`gesting new material for this edition. I also thank Lucy Luckenbaugh
`of Pro-Image Corp. for her fine editing support and patience with my
`missed deadlines.
`
`Peter Van Zant
`Grass Valley, California
`
`Elm Exhibit 2158, Page 17
`
`
`
`Chapter 1
`
`The Semiconductor Industry
`
`Overview
`
`In this chapter, you will be introduced to the Semiconductor industry
`via a brief history, as well as by the importance of the industry in the
`world economy, an overview of the significant technical developments,
`and the trends that have made the industry the world’s leading in-
`dustrial segment. The major manufacturing stages are introduced by
`product types, and transistor building structures along with integra-
`tion levels will be explained.
`
`Objectives
`
`Upon completion of this chapter you should be able to:
`
`1. Describe the difference between discrete devices and integrated cir-
`cuits.
`
`2. Define the terms "solid state," "planar processing" and "N" and "P"
`type semiconducting materials.
`
`3. List the four major stages of semiconductor processing.
`
`4. Explain the Integration Scale and the implications of processing
`circuits of different levels of integration.
`
`5. List the major process and device trends in semiconductor process-
`ing.
`
`Birth of an Industry
`
`The electronic signal processing industry got its jump start with the
`discovery of the audion vacuum tube in the 1906 by Lee Deforest.1 It
`
`Elm Exhibit 2158, Page 18
`
`
`
`2 Chapter One
`
`made possible the radio, television, and other consumer electronics. It
`also was the brains of the world’s first electronic computer, named the
`Electronic Numeric Integrator and Calculator (ENIAC), first demon-
`strated at the Moore School of Engineering in Pennsylvania in 1947.
`This ENIAC hardly fits the modern picture of a computer. It occu-
`pied some 1500 square feet, weighed 30 tons, generated large quan-
`tities of heat, required the services of a small power station, and cost
`$400,000 in 1940 dollars. The ENIAC was based on 19000 vacuum
`tubes along with thousands of resistors and capacitors (Fig. 1.1).
`A vacuum tube consists of three elements, two electrodes separated
`by a grid in a glass enclosure (Fig. 1.2). Inside the enclosure is a vac-
`uum, required to prevent the elements from burning up, and to allow
`the easy transfer of electrons.
`Tubes perform two important electrical functions, switching and
`amplification. Switching refers to the ability of an electrical device to
`turn a current on or off. Amplification is a little more complicated. It
`is the ability of a device to receive a small signal (or current) and
`amplify it while retaining its electrical characteristics.
`Vacuum tubes suffer from a number of drawbacks. They are bulky,
`prone to loose connections and vacuum leaks, fragile, require rela-
`
`Size. tt
`Weight, tons
`Vacuum Tubes
`Resistors
`Capacitors
`Switches
`Power Requirements, W
`Cost (in 1940)
`
`30 x 50
`30
`18,000
`70,000
`10,000
`6000
`150,000
`$400,000
`
`Figure 1.1 Eniac statistics. (Foundations of Computector
`Technology, J. G. Giarratano, Howard W. Sams & Co., Indi-
`anapolis, Ind., 1983.)
`
`Figure 1.2 Vacuum tube.
`
`Elm Exhibit 2158, Page 19
`
`
`
`The Semiconductor Industry 3
`
`tively large amounts of power to operate, and their elements deterio-
`rate rather rapidly. One of the major draw backs to the ENIAC and
`other tube-based computers was a limited operating time due to tube
`burn-out.
`These problems were the impetus leading many laboratories around
`the country to seek a replacement for the vacuum tube. That effort
`came to fruition on Dec, 23, 1947 when three Bell Lab scientists dem-
`onstrated an electrical amplifier formed from the semiconducting ma-
`terial Germanium (Fig. 1.3).
`This device offered the electrical functioning of a vacuum tube, but
`with the advantages of the solid state (no vacuum), small and light
`weight, low power requirements and long lifetime. First named a
`transfer resistor, the new device soon became known as the transistor.
`The three scientists, John Bardeen, Walter Brattin and William
`Shockley were awarded the 1956 Nobel Prize in physics for their in-
`vention.
`
`The Solid State Era
`
`That first transistor was a far distance from the high density inte-
`grated circuit of today. But it was the component that gave birth to
`the solid state electronics era with all its famous progeny. Besides
`transistors, solid state technology is also used to create diodes, resis-
`tors and capacitors. Diodes are two-element devices that function in a
`circuit as a switch. Resistors are monoelements devices that serve to
`limit current flow. Capacitors are two-element devices that store
`charge in a circuit. In some circuits, the technology is used to create
`fuses. Refer to Chapter 14 for an explanation of these concepts and a
`explanation of how these devices work.
`These devices, containing only one device per chip, are called dis-
`crete devices (Fig 1.4). Most discrete devices have less demanding op-
`erational and fabrication requirements than integrated circuits. In
`
`Figure 1.3 The first transistor.
`
`Elm Exhibit 2158, Page 20
`
`
`
`4 Chapter One
`
`¯ Transistors
`
`o Diodes
`
`¯ Capacitors
`
`¯ Resistors
`
`Discrete Diode Package
`
`Figure 1.4 Solid-state discrete devices.
`
`general, discrete devices are not considered leading edge products. Yet
`they are required in most sophisticated electronic systems. In 1998,
`they accounted for 12% of the dollar volume of all semiconductor de-
`vices sold.2 The semiconductor industry was in full swing by the early
`1950’s, supplying devices for transistor radios and transistor based
`computers.
`
`Integrated Circuits (I.C.’s)
`
`The dominance of discrete devices in solid state circuits came to an
`end in 1959. In that year Jack Kilby, a new engineer at Texas Instru-
`ments in Dallas, Texas, formed a complete circuit on a single piece of
`the semiconducting material germanium. His invention combined sev-
`eral transistors, diodes and capacitors (five components total) and
`used the natural resistance of the germanium chip (called a bar by
`Texas Instruments) as a circuit resistor. This invention was the inte-
`grated circuit, the first successful integration of a complete circuit in
`and on the same piece of a semiconducting substrate.
`The Kilby circuit did not h~ve the form that is prevalent today. It
`took Robert Noyce, then at Fairchild Camera, to furnish the final piece
`of the puzzle. In Fig. 1.5 is a drawing of the Kilby circuit. Note that
`the devices are connected with individual wires.
`Earlier Jean Horni, also at Fairchild Camera, had developed a pro-
`cess of forming electrical junctions in the surface of a chip to create a
`
`Plateaus
`
`Out
`
`Figure 1.5 Kilby integrated cir-
`cuit from his notebook. (Cour-
`tesy of Texas Instruments.)
`
`Elm Exhibit 2158, Page 21
`
`
`
`The Semiconductor Industry 5
`
`solid state transistor with a flat profile (Fig. 1.6). The flattened profile
`was the outcome of taking advantage of the easily formed natural
`oxide of silicon, that also happened to be a dielectric (electrical insu-
`lator). Horni’s transistor used a layer of evaporated aluminum, that
`was patterned into the proper shape, to serve as wiring for the device.
`This technique is called planar technology.
`Noyce applied this technique to "wire" together the individual de-
`vices previously formed in the silicon wafer surface.
`The Kilby/Noyce integrated circuit became the model for all inte-
`grated circuits. The techniques used not only met the needs of that
`era, but contained the seeds for all the miniaturization and cost effec-
`tive manufacturing that still drives the industry. Kilby and Noyce
`shared the patent for the integrated circuit.
`
`Process and Product Trends
`
`Since 1947, the semiconductor industry has seen the continuous de-
`velopment of new and improved processes. These process improve-
`ments have in turn led to the more highly-integrated and reliable cir-
`cuits that have, in their turn, fueled the continuing electronics
`revolution. These process improvements fall into two broad categories;
`process and structure. Process improvements are those that allow the
`fabrication of the devices and circuits in smaller dimensions, in ever
`higher density, quantity and reliability. The structure improvements
`are the invention of new device designs allowing greater circuit per-
`formance, power control and reliability.
`Device component size and the number of components in an IC are
`the two common trackers of IC development. Component dimensions
`are characterized by the smallest dimension in the design. This is
`called the feature size, and is usually expressed in microns. A micron
`is 1/10,000 of a centimeter or about 1/100 the diameter of a human
`hair.
`
`Metal
`
`Figure 1.6 Horni "teardrop"
`transistor.
`
`Elm Exhibit 2158, Page 22
`
`
`
`6 Chapter One
`
`In 1964, Gordon Moore, a founder of Intel, predicted that integrated
`circuit density would double in eighteen months. This prediction be-
`came known as Moore’s law and has proven very accurate (Fig. 1.7).
`Circuit density is tracked by the integration level, which is the num-
`ber of components in a circuit. Integration levels (Fig. 1.8) range from
`Small Scale Integration (SSI) to Ultra Large Scale Integration (ULSI).
`ULSI chips are sometimes referred to as Very Very Large Scale In-
`tegration (VVLSI). The popular press calls these newest products
`megachips.
`In addition to the integration-scale, memory circuits are identified
`by the number of memory bits contained in the circuit (a four-meg
`memory chip can store four million bits of memory). Logic circuits are
`often rated by their number of "gates." A gate is the basic operational
`component of a logic circuit.
`
`10g
`
`10a
`
`107
`
`10~
`
`105
`
`104
`
`3
`10
`
`1970 1975 1980 1985 1990 1995
`Year
`
`Figure 1.7 Growth of Dram Density (After Camp-
`bell, The Science of Engineering and Microelectron-
`ics fabrication, Oxford Press.)
`
`Level
`
`Abbreviation # Components per Chip
`
`Small Scale Integration
`Medium Scale Integration
`Large Scale Integration
`Very Large Scale Integration
`Ultra Large Scale Integration
`
`SSI
`MSI
`LSI
`VLSI
`ULSI
`
`2 o 50
`50- 5000
`5000 - 100,000
`Over 100,000 - 1,000,000
`> 1,000,000
`
`Figure 1.8 IC integration table.
`
`Elm Exhibit 2158, Page 23
`
`
`
`The Semiconductor Industry 7
`
`Decreasing feature ~size
`
`The journey from Small Scale Integration to today’s megachips has
`been driven primarily by reductions in the feature size of the individ-
`ual components. This decrease has been brought about by dramatic
`increases in the imaging process, known as photolithography, and the
`trend to multilayers of conductors. Actual and projected feature sizes
`over a twenty-five year span are shown in Fig. 1.9. The Semiconductor
`Industry Association (SIA) has projected feature sizes decreasing to
`50 nanometers (0.005 microns) by the year 2012.~ Along with the abil-
`ity to make components on the chip smaller, comes the benefit of
`crowding them closer together further increasing density.
`An analogy ’used to explain these trends is the layout of a neigh-
`borhood of single family homes. The density of the neighborhood is a
`function of the house size, lot size and the width of the streets. Accom-
`odating a higher population could come by increasing size of the neigh-
`borhood (increasing the chip area). Another possibility is to reduce the
`size of the individual houses, and place them on smaller lots. We can
`also reduce the street size to increase density. However, at some point
`the streets cannot be reduced anymore in size or they won’t be wide
`enough for autos and at some point the houses cannot be further re-
`duced in size and still function as dwelling units. At this point an
`option is to replace individual homes with apartment buildings. All of
`these options are used in semiconductor technology.
`
`~ 1o
`E
`
`1960
`
`1965
`
`1970
`
`1975
`Year
`
`1980
`
`1985
`
`1990
`
`Figure 1.9 Decreasing image feature size. (After Wolf and Tauber,
`"Silicon Processing for the VLSI Era.")
`
`Elm Exhibit 2158, Page 24
`
`
`
`8 Chapter One
`
`There are several benefits to the reduction of the feature size and
`its attendant increase in circuit density. At the circuit performance
`level there is an increase in circuit speed. With less distances to travel
`and with the individual devices occupying less space, information can
`be put into and gotten out of the chip in less time. Anyone who has
`waited for their personal computer to perform a simple operation can
`appreciate the effect of faster performance. These same density im-
`provements result in a chip or circuit that requires less power to op-
`erate. The small power station required to run the ENIAC has given
`way to powerful lap top computers that run on a set of batteries.
`
`Increasing chip and wafer size
`
`The advancement of chip density from the SSI level to ULSI chips has
`driven larger chip sizes. Discrete and SSI chips average about 100 mils
`(0.1 inch) on a side. ULSI chips are in the 500 mil (0.5 inch) per side,
`or larger, range. IC’s are manufactured on thin disks of silicon (or
`other semiconductor material, see Chapter 2) called wafers. Placing
`square or rectangular chips on a round wafer leaves unavailable areas
`around the edge. These unavailable areas can become large as the chip
`size increases (Fig. 1.10). To desire to offset the loss of usable silicon
`has driven the industry to larger wafers. As the chip size increases,
`the 1 inch diameter wafers of the 1960’s have given way to 200 and
`300 mm (8" and 12") sized wafers.
`
`Reduction in defect density
`
`As feature sizes have decreased, the need for reduced defect density
`and defect size on the chips, and in the manufacturing process, be-
`comes critical. A one micron piece of dirt on a 100 micron sized tran-
`sistor may not be a problem. On a one micron sized transistor it be-
`comes a killer defect that can render the component inoperable (Fig.
`
`Equal
`Diameters
`
`~l I I I I I III
`\lllllll II
`
`Die Size
`
`# Whole Die
`
`Figure 1.10
`fers.
`
`69
`
`12
`
`40
`
`Effect of processing larger die on larger wa-
`
`Elm Exhibit 2158, Page 25
`
`
`
`The Semiconductor Industry 9
`
`1.11). Contamination control needs has driven the cost of building an
`IC manufacturing facility into the billion dollar range.
`
`Increase in interconnection levels
`
`The component density increase has led to a "wiring" problem. In the
`neighborhood anology, reducing street widths was one strategy to in-
`crease density. But at some point the streets become too narrow to
`allow cars to travel. The same thing happens in IC design. The in-
`creased component density and close packing rob the surface space
`needed on the surface to connect the components. The solution is mul-
`tiple levels of "wiring" stacked (Fig. 1.12) above the surface compo-
`nents in layers of insulators and conducting layers (Chapter 13).
`
`The SIA roadmap
`
`These major IC parameters are inter-related. Moore’s law predicts the
`future of component density, which triggers the calculation of the in-
`tegration level (component density), chip size, defect density (and
`
`layer
`
`Figure 1.11 Relative size of airborne particles and wa-
`fer dimensions.
`
`Via Plugs
`
`M1 = First Metal
`
`M2 = Second Metal
`
`Figure 1.12 Cross section of typical planarized two-level metal VLI
`structure showing range of via depths after planarization. (Courtesy
`of Solid State Technology)
`
`Elm Exhibit 2158, Page 26
`
`
`
`10 Chapter One
`
`size), and the number of interconnection levels required. The Semi-
`conductor Industry Association has made these projections into the
`future in a series of "roadmaps" covering these and other critical de-
`vice and production parameters (Fig. 1.13).
`
`Chip cost
`
`Perhaps the most significant effect of these process and product im-
`provements is the cost of the chips. Fig. 1.14 shows the year by year
`drop in memory chips through the 1980’s. The curves are typical for
`any maturing product. Prices start high and, as the technology is mas-
`tered and manufacturing efficiencies increase, the prices drop and
`eventually become stable. These chip prices have constantly declined
`even as the performance of the chips have increased. In its first 30
`years, the semiconductor industry had 2 to 5 times the economic im-
`pact in the U.S. that the railroads had in a similiar period.4 The factors
`affecting chip cost are discussed in Chapter 15.
`The two factors, increased performance at less cost, have driven the
`explosion of products using solid state electronics. By the 1990’s, an
`
`Year of Production
`
`2001
`
`Line width (nm)
`Memory size
`Logic Bits/cm2
`Chip Size-DRAM (ram2)
`Max wiring levels
`Mask layers
`Defect density-DRAM (D/m
`Chip conections-I/O’s
`Wafer diameter (mm)
`
`150
`1 Gb
`380M
`445
`7
`23
`875
`1195
`300
`
`2006
`
`I00
`16Gb
`2.2B
`790
`7-8
`24/26
`490
`1970
`300
`
`2012
`
`50
`64 Gb
`17B
`1580
`9
`28
`250
`3585
`450
`
`Figure 1.13 Wafer fabrication (and electrical test).
`
`.025¢
`
`1980
`
`’81 ’82 ’83 ’84 ’85 ’86 ’87
`
`Figure 1.14 Price of chips per bit
`of memory.
`
`Elm Exhibit 2158, Page 27
`
`
`
`The Semiconductor Industry 11
`
`,into had more computing power on-board than the first lunar space
`~dmts. Even more impressive is the personal computer. T