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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________
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`SAMSUNG ELECTRONICS CO., LTD.,
`MICRON TECHNOLOGY, INC., and SK HYNIX INC.
`Petitioners
`
`v.
`
`ELM 3DS INNOVATIONS, LLC,
`Patent Owner
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`
`
`
`
`
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`Case IPR2016-00387
`Patent 8,841,778
`
`____________
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`
`PETITIONERS’ NOTICE OF APPEAL
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`Case IPR2016-00387
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`Pursuant to 37 C.F.R § 90.2(a) and 35 U.S.C. § 142, Petitioners Samsung
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`Electronics Co., Ltd., Micron Technology, Inc., and SK hynix Inc. (“Petitioners”)
`
`hereby respectfully give Notice that they appeal the Patent Trial and Appeal
`
`Board’s (“Board”) Final Written Decision, dated June 23, 2017 (Paper 63),
`
`concluding that claims 1, 2, 8, 14, 31, 32, 44, 46, and 52-54 of U.S. Patent No.
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`8,841,778 have not been shown to be unpatentable to the United States Court of
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`Appeals for the Federal Circuit, and from all underlying orders, decisions, rulings
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`and opinions that are adverse to Petitioners, including, without limitation, those
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`within the Decision on Institution of Inter Partes Review, entered June 30, 2016
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`(Paper 13).
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`For the limited purpose of providing the Director with the information
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`requested in 37 C.F.R § 90.2(a)(3)(ii), issues on Petitioners’ appeal may include,
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`but are not limited to, the construction of the “substantially flexible” terms,
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`including the Board’s construction of these terms; the Board’s interpretation of its
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`construction and application of its construction to the prior art; the Board’s
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`determination of patentability of claims 1, 2, 8, 14, 31, 32, 44, 46, and 52-54 of
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`U.S. Patent No. 8,841,778 under 35 U.S.C § 103, which is factually incorrect, not
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`supported by law or substantial evidence, was not the result of a logical and
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`rational process, and is incorrect as a matter of law; any findings supporting that
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`determination, including findings regarding motivation to combine and a
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`1
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`reasonable expectation of success; the Board’s failure to consider evidence of
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`Case IPR2016-00387
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`record fully and properly; the Board’s legal errors in undertaking its obviousness
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`analysis; the Board’s findings that conflict with the evidence of record and are not
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`supported by substantial evidence; any finding or determination supporting or
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`related to those issues; and any other issues decided adversely to Petitioners in any
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`orders, decisions, rulings and opinions.
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`Simultaneous with this submission, a copy of the Notice of Appeal is being
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`filed electronically with the Patent Trial and Appeal Board. In addition, a copy of
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`this Notice of Appeal, along with the required docketing fees, are being filed
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`electronically with the Clerk’s Office for the United States Court of Appeals for
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`the Federal Circuit.
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`
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`
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`Date: August 24, 2017
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`Respectfully submitted,
`
`
`
`
`
`
`/Naveen Modi/
`
`Naveen Modi (Reg. No. 46,224)
`Paul Hastings LLP
`875 15th St. N.W.
`Washington, D.C., 20005
`Tel.: 202.551.1700
`Fax: 202.551.1705
`PH-Samsung-ELM-IPR@paulhastings.com
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`Attorney for Petitioners
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`Case IPR2016-00387
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`CERTIFICATE OF SERVICE
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`In accordance with 37 CFR § 90.2(a)(1) and § 104.2, I hereby certify that on
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`August 24, 2017, in addition to being filed electronically through the Board’s E2E
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`System, the original version of the foregoing Petitioners’ Notice of Appeal was
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`filed by hand on the Director of the United States Patent and Trademark Office, at
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`the following address:
`
`Director of the United States Patent and Trademark Office
`c/o Office of the General Counsel
`Madison Building East, 10B20
`600 Dulany Street
`Alexandria, VA 22314-5793
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`
`
`CERTIFICATE OF SERVICE
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` hereby certify that on August 24, 2017, a true and correct copy of the
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`
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` I
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`foregoing Petitioners’ Notice of Appeal, along with a copy of the Final Written
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`Decision, was filed electronically with the Clerk’s Office of the United States
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`Court of Appeals for the Federal Circuit, at the following address:
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`United States Court of Appeals for the Federal Circuit
`717 Madison Place, N.W., Suite 401
`Washington, DC 20005
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`CERTIFICATE OF SERVICE
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`Case IPR2016-00387
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`Pursuant to 37 CFR § 42.6(e)(1), the undersigned certifies that on August
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`24, 2017, a complete and entire copy of the Petitioners’ Notice of Appeal was
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`provided via email, to the Patent Owner by serving the email correspondence
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`addresses of record as follows:
`
`William A. Meunier
`Michael T. Renaud
`Mintz, Levin, Cohn, Ferris,
`Glovsky and Popeo, P.C.
`One Financial Center
`Boston, MA 02111
`
`James Carmichael
`Carmichael IP, PLLC
`8000 Towers Crescent Drive, 13th Floor
`Tysons Corner, VA 22182
`
`Email: WAMeunier@mintz.com
`Email: mtrenaud@mintz.com
`Email: mcnewman@mintz.com
`Email: ELM 3DS IPRs@mintz.com
`Email: jim@carmichaelip.com
`
`
` /Naveen Modi/
`Naveen Modi
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`4
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`
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`Trials@uspto.gov
`571-272-7822
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` Paper 63
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`Entered: June 23, 2017
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`SAMSUNG ELECTRONICS CO., LTD.,
`MICRON TECHNOLOGY, INC., and SK HYNIX, INC.,
`Petitioner,
`
`v.
`
`ELM 3DS INNOVATIONS, LLC,
`Patent Owner.
`____________
`
`Case IPR2016-00386 Patent 8,653,672 B2
`Case IPR2016-00387 Patent 8,841,778 B2
`Case IPR2016-00388 Patent 7,193,239 B2
`____________
`
`
`Before GLENN J. PERRY, BARBARA A. BENOIT, and
`FRANCES L. IPPOLITO, Administrative Patent Judges.
`
`BENOIT, Administrative Patent Judge.
`
`
`DECISION
`Final Written Decision
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`
`I. INTRODUCTION
`
`These inter partes reviews, instituted pursuant to 35 U.S.C. § 314,
`challenge the patentability of certain claims of U.S. Patent
`Nos. 8,653,672 B2 (“the ’672 patent”), 8,841,778 B2 (“the ’778 patent”),
`and 7,193,239 B2 (“the ’239 patent),1 each of which shares the same written
`description. All of the challenged patents are owned by Elm 3DS
`Innovations, LLC (“Patent Owner”). We have jurisdiction under 35 U.S.C.
`§ 6. This Final Written Decision is entered pursuant to 35 U.S.C. § 318(a)
`and 37 C.F.R. § 42.73. This Decision is issued concurrently with a Final
`Written Decision in IPR2016-00393, which also challenges the patentability
`of claims 10−12, 18−20, 60−63, 67, 70−73, and 77 of the ’239 patent.
`For the reasons discussed herein, Petitioner has not shown by a
`preponderance of the evidence that the challenged claims in any of the
`challenged patents are unpatentable.
`
`A. Procedural History
`In IPR2016-00386, Petitioner filed a Petition seeking inter partes
`review of certain claims of the ’672 patent and we instituted a review.
`IPR386-Paper 1 (“IPR386-Petition” or “IPR386-Pet.”); IPR386-Paper 14
`(“IPR386-Institution Decision” or “IPR386-Inst. Dec.”). In IPR2016-00387,
`Petitioner filed a Petition seeking inter partes review of certain claims of the
`’778 patent, and we instituted a review. IPR387-Paper 1 (“IPR387-Petition”
`
`1 The challenged patent is Exhibit 1001 in each proceeding. Citations may
`be preceded by “IPR386” to designate IPR2016-00386, “IPR387” to
`designate IPR2016-00387, or “IPR388” to designate IPR2016-00388.
`2
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`or “IPR387-Pet.”); IPR387-Paper 13 (“IPR387-Institution Decision” or
`“IPR387-Inst. Dec.”). In IPR2016-00388, Petitioner filed a Petition seeking
`inter partes review of certain claims of the ’239 patent, and we instituted a
`review. IPR388-Paper 4 (“IPR388-Petition” or “IPR388-Pet.”);
`IPR388-Paper 11 (“IPR388-Institution Decision” or “IPR388-Inst. Dec.”).
`In our Decisions to Institute, we did not agree with Patent Owner that the
`Petitions were barred under 35 U.S.C. § 315(b) because, according to Patent
`Owner, the Office lacked authority to treat certain days on which the Office
`experienced an emergency situation, such that many of its online and
`information technology systems were shut down, as federal holidays.
`IPR386-Inst. Dec. 4–5; IPR387-Inst. Dec. 3–4; IPR388-Inst. Dec. 4–5.
`Patent Owner has not raised this issue subsequent to institution in any of the
`three proceedings.
`In response to an order to clarify the claim construction standard to be
`applied in each proceeding (IPR386-Paper 18; IPR387-Paper 16; IPR388-
`Paper 14), Patent Owner certified that each of the challenged patents in these
`three proceedings would expire prior to the deadline for issuing a final
`written decision and, therefore, contended that the claim construction
`standard set forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005),
`should be applied (IPR386-Paper 23; IPR387-Paper 21; IPR388-Paper 19).
`Petitioner concurred with Patent Owner’s contention. IPR386-Paper 25;
`IPR387-Paper 23; IPR388-Paper 21. We agreed with the parties and issued
`an order indicating that the Phillips claim construction standard should be
`
`3
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`
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`applied in each of these three proceedings. IPR386-Paper 28; IPR387-
`Paper 26; IPR388-Paper 24.
`Subsequent to institution, Patent Owner filed a Patent Owner
`Response to the Petition in each case. IPR386-Paper 55 (“IPR386-PO
`Resp.”); IPR387-Paper 50 (“IPR387-PO Resp.”); IPR388-Paper 47
`(“IPR388-PO Resp.”). Petitioner filed a Reply to Patent Owner’s Response
`to the Petition in each case. IPR386-Paper 61 (“IPR386-Pet. Reply”);
`IPR387-Paper 56 (“IPR387-Pet. Reply”); IPR388-Paper 53 (“IPR388-Pet.
`Reply”).
`We held a consolidated hearing for the inter partes reviews. A
`transcript of the oral hearing is included in the record of each proceeding.
`IPR386-Paper 67; IPR387-Paper 62; IPR388-Paper 59 (collectively “Tr.”).
`
`B. Related Matters
`As required by 37 C.F.R. § 42.8(b)(2), each party identifies various
`judicial or administrative matters that would affect or be affected by a
`decision in this proceeding. IPR386-Pet. 1–2; IPR386-Paper 9 (Patent
`Owner’s Mandatory Notices); IPR387-Pet. 1–2; IPR387-Paper 8 (Patent
`Owner’s Mandatory Notices); IPR388-Pet. 1–2; IPR388-Paper 7 (Patent
`Owner’s Mandatory Notices). Petitioner indicates that the challenged
`patents are involved in the following United States District Court
`proceedings: Elm 3DS Innovations, LLC v. Samsung Elecs. Co., No. 1:14-
`cv-01430 (D. Del.); Elm 3DS Innovations, LLC v. Micron Tech., Inc.,
`No. 1:14-cv-01431 (D. Del.); and Elm 3DS Innovations, LLC v. SK Hynix
`Inc., No. 1:14-cv-01432 (D. Del.).
`
`4
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`
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`
`The ’239 patent, which is challenged in IPR2016-00388, also is the
`subject of inter partes review IPR2016-00393. Additionally, patents related
`to the challenged patent are the subjects of petitions filed in IPR2016-00389
`(U.S. Patent No. 8,035,233); IPR2016-00390 (U.S. Patent No. 8,629,542);
`IPR2016-00391 (U.S. Patent No. 8,796,862); IPR2016-00394 (U.S. Patent
`No. 8,410,617); IPR2016-00395 (US Patent No. 7,504,732); IPR2016-00687
`(U.S. Patent No. 8,928,119); IPR2016-00691 (U.S. Patent No. 7,474,004);
`IPR2016-00708 (U.S. Patent No. 8,907,499); IPR2016-00770 (U.S. Patent
`No. 8,907,499); and IPR2016-00786 (U.S. Patent No. 8,933,570). We also
`note that Petitioner filed two additional petitions requesting inter partes
`review of U.S. Patent No. 8,791,581 (IPR2016-00703 and IPR2016-00706)
`for which we did not institute a review.
`
`C. The Written Description of the Challenged Patents2
` The challenged patents identify Glenn J. Leedy as sole inventor of the
`claimed subject matter. The patents each claim the benefit of the filing date
`of April 4, 1997 through a series of continuation or divisional applications.
`Accordingly, the patents share a common written description.
` The patents generally relate to a three-dimensional structure (3DS)
`for integrated circuits that allows for physical separation of memory circuits
`and control logic circuits on different layers. Ex. 1001, Abstract. Figure 1a
`is reproduced below.
`
`
`2 For brevity, citations to the written description refer to the ’672 patent at
`issue in IPR2016-00386.
`
`5
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`
`
` Figure 1a shows 3DS memory device 100 having a stack of
`integrated circuit layers with a “fine-grain inter-layer vertical interconnect”
`between all circuit layers. Id. at 3:64–67. Layers shown include controller
`circuit layer 101 and memory array circuit layers 103. Id. at 4:17–19. The
`written description discloses that “each memory array circuit layer is a
`thinned and substantially flexible circuit with net low stress, less than 50 µm
`and typically less than 10 µm in thickness.” Id. at 4:22–24. The written
`description further discloses that the “thinned (substantially flexible)
`substrate circuit layers are preferably made with dielectrics in low stress
`(less than 5×108 dynes/cm2) such as low stress silicon dioxide and silicon
`nitride dielectrics as opposed to the more commonly used higher stress
`dielectrics of silicon oxide and silicon nitride used in conventional memory
`circuit fabrication.” Id. at 8:45–50.
`Figure 1b is reproduced below.
`
`6
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`
`
`Figure 1b of written description shows a cross-section of a 3DS
`integrated circuit with metal bonding interconnect between thinned circuit
`layers. Id. at 3:38–40. Bond and interconnect layers 105a, 105b, 105c are
`shown between circuit layers 103a and 103b. Id. at Fig. 1b. The written
`description discloses that pattern 107a, 107b, 107c in the bond and
`interconnect layers 105a, 105b, 105c defines the vertical interconnect
`contacts between the integrated circuit layers and serves to electrically
`isolate these contacts from each other and the remaining bond material. Id.
`at 4:11–15. Additionally, the written description teaches that the pattern
`takes the form of voids or dielectric filled spaces in the bond layers. Id. at
`4:15–16.
`
`7
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`
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`
`Further, the written description teaches that the “term fine-grained
`inter-layer vertical interconnect is used to mean electrical conductors that
`pass through a circuit layer with or without an intervening device element
`and have a pitch of nominally less than 100 µm. . . .” Id. at 3:67–4:4. The
`fine-grained inter-layer vertical interconnect functions to bond together
`various circuit layers. Id. at 4:5–7.
`
`D. Instituted Grounds of Unpatentability
`We instituted inter partes reviews of the challenged patents based on
`Petitioner’s asserted grounds involving the following references:3 (i) U.S.
`Patent No. 5,202,754, issued April 13, 1993 (Ex. 1004, “Bertin ’754”);
`(ii) U.S. Patent No. 5,354,695, issued Oct. 11, 1994 (Ex. 1006,
`“Leedy ’695”); (iii) U.S. Patent No. 5,162,251, issued Nov. 10, 1992 (Ex.
`1005, “Poole”); (iv) Yu, et al., Real-Time Microvision System with Three-
`Dimensional Integration Structure, Proceedings of the 1996 IEEE/SICE/RSJ
`International Conference on Multisensor Fusion and Integration for
`Intelligent Systems, 1996 (Ex. 1009, “Yu”); and (v) U.S. Patent No.
`5,627,106, issued May 6, 1997 (Ex. 1008, “Hsu”).
`We instituted inter partes reviews of the challenged patents based on
`35 U.S.C. § 1034 on the particular following grounds:
`
`
`3 The prior art references have the same exhibit numbers in each proceeding.
`4 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29, 125
`Stat. 284, 287–88 (2011), revised 35 U.S.C. § 103, effective March 16,
`2013. Because the challenged patent was filed before March 16, 2013, we
`refer to the pre-AIA version of § 103 in this decision.
`8
`
`
`
`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`
`IPR2016-00388 Patent 7,193,239 B2
`
`IPR2016-00386 Benin ,754, P0016,
`and Leedy ’695
`IPR2016-00386 Yu and Leedy ’695
`
`IPR2016 00387 Bertln ,754 and
`Leedy 695
`IPR2016-00387 Bertin ’754, Poole,
`and Leed ’695
`
`Claims 17, 18, 22, 84, 95,
`129—132, 145, 146, and 152
`Claims 17, 18, 22, 84, 95,
`129—132, 145, 146, and 152
`Claims 1’ 2, 8, 14’ and 52
`
`Claims 2, 8, 31, 32, 44, 46,
`and 52—54
`
`Claims 1, 2, 8, 14, 31,32,
`
`44, 46, and 52—54
`
`
`
`IPR2016—00387
`
`- HS“ and Leedy 695
`
`,
`
`IPR2016-00388
`
`,
`Y“ and Leedy 695
`
`Claims 10—12, 18—20, 60—
`63, 67, 70—73, and 77
`
`IPR386—Inst. Dec. 40; IPR3 87—Inst. Dec. 34; IPR388—Inst. Dec. 28.
`
`II. DISCUSSION5
`
`A. Principles ofLaw
`
`1. Principles of Claim Construction
`
`The patents challenged in these three proceedings have expired. See
`
`IPR386-Paper 23 (Patent Owner’s Notice of Patent Expiration indicating the
`
`’672 patent would expire on April 4, 2017); IPR387-Paper 21 (indicating
`
`that the ’778 patent would expire on April 4, 2017), IPR388—Paper 19
`
`indicating that the ’239 patent would expire on April 4, 2017. For claims of
`
`an expired patent, the Board’s claim construction analysis is similar to that
`
`of a district court. See In re Rambus, Inc., 694 F.3d 42, 46 (Fed. Cir. 2012);
`
`see, e.g., IPR386—Paper 28 (determining a district court-type claim
`
`5 The discussion in this section, unless otherwise noted, addresses issues
`relevant to IPR2016—00386, IPR2016—00387, and IPR2016—00388.
`9
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`construction approach following Phillips is to be applied during IPR2016-
`IPR00386, IPR2016-00387, and IPR2016-00388). In this context, claim
`terms “are generally given their ordinary and customary meaning” as
`understood by a person of ordinary skill in the art in question at the time of
`the invention. Phillips v. AWH Corp., 415 F.3d 1303, 1312–13 (Fed. Cir.
`2005) (en banc). “In determining the meaning of the disputed claim
`limitation, we look principally to the intrinsic evidence of record, examining
`the claim language itself, the written description, and the prosecution
`history, if in evidence.” DePuy Spine, Inc. v. Medtronic Sofamor Danek,
`Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips, 415 F.3d at
`1312–17). Extrinsic evidence, such as expert testimony and dictionary
`definitions, can be helpful but is “less significant than the intrinsic record in
`determining the legally operative meaning of claim language.” Phillips, 415
`F.3d at 1317. Also, extrinsic evidence is to be considered within the context
`of the intrinsic evidence. Id. A claim term may be construed contrary to its
`ordinary and customary meaning only “under two circumstances: ‘(1) when
`a patentee sets out a definition and acts as [its] own lexicographer, or (2)
`when the patentee disavows the full scope of a claim term either in the
`specification or during prosecution.’” Aventis Pharma S.A. v. Hospira, Inc.,
`675 F.3d 1324, 1330 (Fed. Cir. 2012) (quoting Thorner v. Sony Computer
`Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012)); Hill-Rom Svcs, Inc.
`v. Stryker Corp., 755 F.3d 1367, 1371 (Fed. Cir. 2014).
`In each proceeding, we construe the challenged claims according to
`these principles.
`
`10
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`
`2. Principles of Law Concerning Demonstrating Unpatentability
`To prevail in challenging Patent Owner’s claims, Petitioner must
`demonstrate by a preponderance of the evidence that the claims are
`unpatentable. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d). “In an [inter partes
`review], the petitioner has the burden from the onset to show with
`particularity why the patent it challenges is unpatentable.” Harmonic Inc. v.
`Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed. Cir. 2016) (citing 35 U.S.C.
`§ 312(a)(3) (requiring inter partes review petitions to identify “with
`particularity . . . the evidence that supports the grounds for the challenge to
`each claim”)). This burden never shifts to Patent Owner. See Dynamic
`Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375, 1378 (Fed.
`Cir. 2015) (citing Tech. Licensing Corp. v. Videotek, Inc., 545 F.3d 1316,
`1326–27 (Fed. Cir. 2008)) (discussing the burden of proof in inter partes
`review). Furthermore, Petitioner cannot satisfy its burden of proving
`obviousness by employing “mere conclusory statements.” In re Magnum
`Oil Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed. Cir. 2016).
`Petitioner asserts that certain claims of the challenged patents are
`unpatentable under 35 U.S.C. § 103(a) as obvious over various combinations
`of references. A claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time of the
`invention to a person having ordinary skill in the art. KSR Int’l Co. v.
`Teleflex, Inc., 550 U.S. 398, 406 (2007). The question of obviousness is
`resolved on the basis of underlying factual determinations including: (1) the
`
`11
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`IPR2016-00386 Patent 8,653,672 B2 IPR2016-00387 Patent 8,841,778 B2
`IPR2016-00388 Patent 7,193,239 B2
`
`scope and content of the prior art; (2) any differences between the claimed
`subject matter and the prior art; (3) the level of ordinary skill in the art; and
`(4) objective evidence of nonobviousness. Graham v. John Deere Co., 383
`U.S. 1, 17–18 (1966). Consideration of the Graham factors “helps inform
`the ultimate obviousness determination.” Apple v. Samsung Elecs. Co., 839
`F.3d 1034, 1048 (Fed. Cir. 2016) (en banc).
`
`B. Level of Ordinary Skill
`In determining whether an invention would have been obvious at the
`time it was made, 35 U.S.C. § 103 requires us to resolve the level of
`ordinary skill in the pertinent art at the time of the invention. Graham, 383
`U.S. at 17. “The importance of resolving the level of ordinary skill in the art
`lies in the necessity of maintaining objectivity in the obviousness inquiry.”
`Ryko Mfg. Co. v. Nu-Star, Inc., 950 F.2d 714, 718 (Fed. Cir. 1991). The
`person of ordinary skill in the art is a hypothetical person who is presumed
`to have known the relevant art at the time of the invention. In re GPAC,
`Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). Factors that may be considered in
`determining the level of ordinary skill in the art include, but are not limited
`to, the types of problems encountered in the art, the sophistication of the
`technology, and educational level of active workers in the field. GPAC, 57
`F.3d at 1579. In a given case, one or more factors may predominate. Id.
`Generally, it is easier to establish obviousness under a higher level of
`ordinary skill in the art. Innovention Toys, LLC v. MGA Entm’t, Inc.,
`637 F.3d 1314, 1323 (Fed. Cir. 2011) (“A less sophisticated level of skill
`
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`generally favors a determination of nonobviousness . . . while a higher level
`of skill favors the reverse.”).
`Petitioner, with support of its declarant Paul D. Franzon, Ph.D.,
`contends that one of ordinary skill in the art at the time of the inventions of
`the challenged patents “would have had at least a B.S. degree in electrical
`engineering, material science, or equivalent thereof, and at least 3–5 years of
`experience in the relevant field, e.g., semiconductor processing.” IPR386-
`Pet. 5 (citing Ex. 1002 ¶¶ 52–53); see IPR387-Pet. 4 (citing Ex. 1002 ¶¶ 52–
`53); IPR388-Pet. 4 (citing Ex. 1002 ¶¶ 52–53). According to Dr. Franzon,
`his testimony as to the level of ordinary skill is based on considering “the
`types of problems encountered in the art, prior art solutions to those
`problems, the rapidity with which innovations are made, the sophistication
`of the technology, and the educational level of active workers in the field.”
`IPR386-Ex. 1002 ¶ 53; see IPR387-Ex. 1002 ¶ 53; IPR388-Ex. 1002 ¶ 53.
`Patent Owner did not propose expressly a particular level of ordinary skill.
`See, e.g., generally IPR386 PO Resp.; IPR386 Ex. 2166 (Patent Owner’s
`expert’s declaration). At the oral hearing, however, Petitioner indicated that
`there did not seem to be any dispute as to the correct level of ordinary skill.
`Tr. 112:11–14 (“I don’t think there was any dispute about whether [Dr.
`Franzon’s proposed level of ordinary skill] was the correct level of skill,
`although Patent Owner can correct me.”).
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`Having reviewed the prior art asserted in these proceedings (see, e.g.,
`Exs. 1004–07, 1009, 21606), we determine that the level of ordinary skill
`proposed by Petitioner’s declarant is consistent with the challenged patents
`and the referenced prior art, and we adopt that definition of the level of
`ordinary skill in the art for the purposes of the analysis below.
`
`C. Disclosures of Prior Art References6
`1. Disclosure of Bertin ’754
`Bertin ’754 is a United States Patent that describes an improvement to
`a known multichip package as shown in its “prior art” Figure 1, reproduced
`below.
`
`
`
`
`6 The exhibit numbers for the asserted prior art references are the same in
`IPR2016-00386, IPR2016-00387, and IPR2016-00388.
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`Bertin ’754’s Figure 1 is an exploded perspective view of a basic prior
`art multichip package. Ex. 1004, 2:43–44.
`Bertin ’754 describes “[a] fabrication method and resultant three-
`dimensional multichip package having a densely stacked array of
`semiconductor chips.” Id. at Abstract. More specifically, Bertin ’754 relates
`to a method for fabricating a three-dimensional multichip package having a
`densely stacked array of semiconductor chips interconnected at least
`partially by means of a plurality of metallized trenches in the semiconductor
`chips. Ex. 1004, 1:10-15. Figure 3a is reproduced below.
`
`
`Referring first to FIG. 3a of Bertin ’754, which depicts a three-
`dimensional multichip package, processing begins with semiconductor
`device 50 (preferably comprising a wafer) having substrate 52 and active
`layer 54, which is typically positioned at least partially therein. Layer 54
`may be totally or partially defused into substrate 52 and/or partially or
`totally built up from substrate 52 using conventional semiconductor
`processing techniques known to those skilled in the art. Id. at 3:50–57
`(emphasis added). Layer 54 is adjacent to first, upper planar surface 56 of
`device 50. Id. at 3:57–58. Second, lower planar surface 58 of stacked chip
`50 is positioned substantially parallel to first planar surface 56. Id. at 3:59–
`60. Stacked chip 50 includes semiconductor “substrate 52” (id. at 3:50–4:3),
`which is thinned to 20 μm or less (id. at 3:25–46, 5:10–22). Bertin ’754
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`further teaches that “dielectric layer 60, for example, SiO2, is grown over
`active layer 54 of device 50.” Id. at 3:60–62, Fig. 3a. Additionally, Bertin
`’754 teaches that the multichip package includes vertical electrical
`interconnections (e.g., metallized trenches) that pass completely through
`substrates 52. Id. at Abstract, 1:62–2:12, 4:11–52, Figs. 3c, 3b, 3e, 3g.
`
`2. Disclosure of Leedy ’695
`Leedy ’695 is a United States Patent naming Glenn J. Leedy as sole
`inventor and titled “Membrane Dielectric Isolation IC Fabrication.”
`Ex. 1006 [54], [76]. In its Abstract, the patent indicates that the disclosed
`integrated circuits are fabricated “from flexible membranes formed of very
`thin low stress dielectric materials, such as silicon dioxide or silicon nitride,
`and semiconductor layers.” Id. at Abstract. Leedy ’695 is incorporated by
`reference into the written description of the ’672, ’778, and ’239 patents
`(and the entire Elm 3DS patent family). IPR386-Ex. 1001, 2:21–23
`(“Assembling die in a stacked or three dimensional (3D) manner is disclosed
`in [Leedy ’695] of the present inventor, incorporated herein by reference.”);
`IPR387-Ex. 1001, 2:21–23; IPR388-Ex. 1001, 2:34–36. Leedy ’695
`discloses forming a “tensile low stress dielectric membrane” on a
`semiconductor layer as part of its integrated circuit structure. Id. at 1:53–58.
`Leedy ’695 defines “[l]ow stress . . . relative to the silicon dioxide and
`silicon nitride deposition made with the Novellus equipment as being less
`than 8 x 108 dynes/cm2 (preferably 1 x 107 dynes/cm2) in tension.” Id. at
`11:33–37. Additionally, Leedy ’695 discloses two chemical vapor
`deposition (CVD) process recipes for manufacturing “structurally enhanced
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`low stress dielectric circuit membranes.” Id. at 11:51–65.
`Referring to Figure 8, Leedy ’695 discloses a three dimensional
`circuit membrane. Id. at 4:43. Figure 8 is reproduced below.
`
`
`Figure 8 shows the vertical bonding of two or more circuit membranes
`to form a three dimensional circuit structure. Id. at 16:38–40.
`Interconnection between circuit membranes 160a, 160b, 160c including SDs
`162, 164, 166 is by compression bonding of circuit membrane surface
`electrodes 168a, 168b, 168c, 168d (pads). Id. at 16:40–43. Bonding 170
`between MDI circuit membranes is achieved by aligning bond pads 168c,
`168d (typically between 4 μm and 25 μm in diameter) on the surface of two
`circuit membranes 160b, 160c and using a mechanical or gas pressure source
`to press bond pads 168c, 168d together. Id. at 16:43–49.
`
`3. Disclosure of Poole
`Poole is a United States Patent that describes techniques for making
`charge-coupled devices, which are thinned to allow illumination of the
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`backside of the device to improve quantum efficiency and UV spectral
`response. Ex. 1005, Abstract, 1:8–11. It describes a two-step method for
`thinning the backside of a silicon semiconductor substrate that includes
`integrated circuitry previously formed on the front side. Id. at Abstract, 1:7–
`18, 3:12–25. First, “[t]he bulk silicon is thinned to 75 μm with a 700 micro-
`grit aluminum oxide abrasive” (id. at 3:21–25; see also id. at Abstract, 3:33–
`34, 5:60–6:35), and “is then thinned and polished to 10 µm using 80 nm grit
`colloidal silica” (id. at 3:21–25; see also id. at Abstract, 3:33–34, 6:37–46).
`The result is a surface “almost totally free of work damage.” Id. at 5:64–65;
`see also id. at 3:44–46.
`
`4. Disclosure of Yu
`Yu is a paper published in the proceedings of a technical conference
`sponsored by IEEE Industrial Electronics Society, the IEEE Robotics and
`Automation Society, the Society of Instrument and Control Engineers, and
`the Robotics Society of Japan. Ex. 1009, 3. Yu describes a three-
`dimensional integrated circuit structure for implementing a real-time
`microvision system. Ex. 1009, 831–32. “The system consists of a number
`of 2D LSIs vertically stacked using 3D LSI technology. . . .” Id. at 832.
`Yu’s Figure 1 is reproduced below.
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`
`Figure 1 shows a basic concept of a real-time microvision system with
`a 3D integration structure.
`In Yu’s microvision system, substrates are ground and polished to thin
`the substrates to about 30 microns. Id. at 831–32 (“The Si substrate of the
`2D-LSI which has the basic circuits is ground and polished to make thin
`wafer.”); id. at Abstract (“In fabrication, grinding and chemical-mechanical
`polishing techniques are used to thin the wafer to 30 μm.”). Wafers then are
`bonded together using a combination of conductive microbumps and a UV-
`hardening adhesive. Id. at 834–35 (“The thinned wafer is bonded to a thick
`wafer using In/Au micro-bumps with the minimum size of 5 μm x 5 μm and
`UV hardening adhesive layer with th
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