UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`
`
`SAMSUNG ELECTRONICS CO., LTD.;
`MICRON TECHNOLOGY, INC.; and
`SK HYNIX INC.
`Petitioner
`
`v.
`
`ELM 3DS INNOVATIONS, LLC
`Patent Owner
`
`____________________
`
`Case No. IPR2016-00387
`U.S. Patent No. 8,841,778
`____________________
`
`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE
`
`

`

`
`
`IPR2016-00387 (U.S. Patent 8,841,778)
`
`2.
`
`3.
`
`4.
`
`5.
`
`B.
`
`C.
`
`I.
`II.
`
`TABLE OF CONTENTS
`INTRODUCTION .......................................................................................... 1
`3D IC DIELECTRICS COULD HAVE BEEN REPLACED WITH
`LEEDY ’695’S PECVD LTSDS ..................................................................... 3
`A.
`PO’s FEOL Arguments Lack Merit ..................................................... 3
`Leedy ’695 Teaches Using PECVD To Deposit LTSDs In
`1.
`The FEOL .................................................................................. 3
`Prior Art Literature Proves That PECVD Is Used In
`FEOL ........................................................................................ 11
`PECVD Dielectrics Are Compatible With Silicon
`Substrates And High Temperature Processes .......................... 11
`Silicides Are Not Required—FEOL Dielectrics Need Not
`Undergo High-Temperature Processing .................................. 15
`PECVD Was A Viable Process For Forming Silicon
`Dioxide And Silicon Nitride LTSDs ....................................... 16
`III. THE CHALLENGED CLAIMS ARE OBVIOUS ...................................... 17
`A.
`The Petition Establishes That A POSA Would Have Been
`Motivated To Combine Prior Art Teachings ..................................... 17
`It Would Have Been Obvious To Replace BEOL Dielectrics In
`The Prior Art With Leedy ’695’s LTSD ............................................ 20
`The Need To Adjust Dielectric Parameters Does Not Preclude
`Obviousness ........................................................................................ 21
`PO’s Teaching Away Argument Fails ............................................... 24
`D.
`IV. BERTIN COMBINED WITH LEEDY ’695 RENDERS THE
`CHALLENGED CLAIMS OBVIOUS ........................................................ 25
`Bertin’s Dielectrics Are BEOL .......................................................... 25
`A.
`Even If Bertin’s Dielectrics Are FEOL, The Challenged Claims
`B.
`Are Obvious ....................................................................................... 26
`Layer 60 Is Not Removed .................................................................. 26
`C.
`BERTIN COMBINED WITH POOLE AND LEEDY ’695 RENDERS
`THE CHALLENGED CLAIMS OBVIOUS................................................ 27
`
`V.
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`i
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`

`IPR2016-00387 (U.S. Patent 8,841,778)
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`
`VI. HSU COMBINED WITH LEEDY ’695 RENDERS THE
`CHALLENGED CLAIMS OBVIOUS ........................................................ 29
`VII. CLAIM CONSTRUCTION ......................................................................... 30
`VIII. CONCLUSION ............................................................................................. 32
`
`
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`ii
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`IPR2016-00387 (U.S. Patent 8,841,778)
`
`TABLE OF AUTHORITIES
`
`CASES
`In re Keller,
`642 F.2d 413 (CCPA 1981) ................................................................................ 17
`
`Lockwood v. American Airlines,
`107 F.3d 1565 (Fed. Cir. 1997) .......................................................................... 22
`
`Marine Polymer Techs., Inc. v. HemCon, Inc.,
`672 F.3d 1350 (Fed. Cir. 2012) .......................................................................... 31
`
`In re Mouttet,
`686 F.3d 1322 (Fed. Cir. 2012) .......................................................................... 21
`
`In re Paulsen,
`30 F.3d 1475 (Fed. Cir. 1994) ............................................................................ 31
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) .......................................................................... 31
`
`Spectra–Physics, Inc. v. Coherent, Inc.,
`827 F.2d 1524 (Fed. Cir. 1987) .......................................................................... 23
`
`Syntex (U.S.A.) LLC v. Apotex, Inc.,
`407 F.3d 1371 (Fed. Cir. 2005) .......................................................................... 25
`
`Tempo Lighting, Inc. v. Tivoli, LLC,
`742 F.3d 973 (Fed. Cir. 2014) ............................................................................ 31
`
`OTHER AUTHORITIES
`
`IPR 2016-00691, Institution Decision ..................................................................... 20
`
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`Ex. No.
`
`UPDATED EXHIBIT LIST
`
`Description
`
`Ex. 1007
`
`Ex. 1001 U.S. Patent No. 8,841,778 (“the ’778 Patent”)
`Ex. 1002 Declaration of Dr. Paul D. Franzon
`Ex. 1003 Curriculum Vitae o Dr. Paul D. Franzon
`Ex. 1004 U.S. Patent No. 5,202,754 to Bertin et al., issued April
`13, 1993
`Ex. 1005 U.S. Patent No. 5,162,251 to Poole et al., issued
`November 10, 1992
`Ex. 1006 U.S. Patent No. 5,354,695 to Leedy, issued October 11,
`1994
`Japanese Patent Publication No. 3-151637 to Kowa
`including Japanese-language version, English-language
`translation, and translation certification
`Ex. 1008 U.S. Patent No. 5,627,106 to Hsu, issued May 6, 1997
`Ex. 1009 RESERVED
`Ex. 1010 RESERVED
`Ex. 1011 RESERVED
`Ex. 1012 RESERVED
`Ex. 1013 RESERVED
`Ex. 1014 RESERVED
`Ex. 1015 RESERVED
`Ex. 1016 RESERVED
`Ex. 1017 Prosecution History for U.S. Patent No. 8,841,778
`Ex. 1018 Excerpt of the Prosecution File History of U.S. Patent
`No. 8,907,499—Non-Final Office Action dated May 29,
`2013.
`
`Previously
`Submitted
`X
`X
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`X
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`Ex. 1019 Excerpt of the Prosecution File History of U.S. Patent
`No. 8,907,499—Applicant’s Response dated June 20,
`2013
`Ex. 1020 Excerpt of the Prosecution File History of U.S. Patent
`No. 8,907,499—Specification filed on April 4, 2013
`Ex. 1021 Prosecution History of U.S. Patent App. No. 12/497,652
`– Response to Office Action dated September 26, 2013
`Ex. 1022 Prosecution History of U.S. Patent App. No. 12/497,653
`– Response to Office Action dated October 24, 2013
`Ex. 1023 Prosecution History of U.S. Patent App. No. 12/497,652
`- Response to Office Action dated April 5, 2013
`Ex. 1024 Prosecution History of U.S. Patent No. 5,915,167 -
`Response to Office Action dated April 28, 1998
`Ex. 1025 Prosecution History of U.S. Patent No. 5,915,167 -
`Response to Office Action dated September 8, 1998
`Ex. 1026 Prosecution History of U.S. Patent No. 8,629,542 -
`Response to Office Action dated July 30, 2012
`Ex. 1027 RESERVED
`Ex. 1028 Prosecution History of U.S. Patent No. 7,705,466 -
`Response to Office Action dated February 16, 2009
`Ex. 1029 Prosecution History of U.S. Patent No. 7,705,466 -
`Response to Office Action dated June 25, 2009
`Ex. 1030 Prosecution History of U.S. Patent No. 8,928,119 -
`Response to Office Action dated September 4, 2012
`Ex. 1031 Prosecution History of U.S. Patent No. 8,928,119 –
`Appeal Brief dated June 3, 2013
`Ex. 1032 Prosecution History of U.S. Patent No. 8,410,617 -
`Response to Office Action dated December 14, 2010
`Ex. 1033 Prosecution History of U.S. Patent Application No.
`12/497,652 - Final Office Action dated August 27, 2014
`Ex. 1034 Prosecution History of U.S. Patent Application No.
`12/497,652 - Express Abandonment dated November 20,
`2014
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`Ex. 1035 Prosecution History of U.S. Patent Application No.
`12/497,653 - Advisory Action dated August 27, 2014
`Ex. 1036 Prosecution History of U.S. Patent Application No.
`12/497,653 - Express Abandonment dated November 20,
`2014
`Ex. 1037 RESERVED
`Ex. 1038 RESERVED
`Ex. 1039 Concept One CVD System Process Specifications from
`Novellus
`Ex. 1040 Wolf et al., Processing for the VLSI Era, Volume 1 -
`Process Technology (1986).
`Ex. 1041 U.S. Patent No. 3,508,980 to Jackson et al., issued April
`28, 1970
`Ex. 1042 U.S. Patent No. 3,044,909 to Shockley, issued July 17,
`1962
`Ex. 1043 Fahey et al., Stress-induced dislocations in silicon
`integrated circuits, IBM J. Res. Develop. Vol. 36, No. 2,
`March 1992
`Ex. 1044 Hass et al., Physics of Thin Films: Advances in Research
`and Development (1966)
`Ex. 1045 EerNisse, E.P., Stress in thermal SiO2 during growth,
`Appl. Phys. Lett. 35(1), July 1, 1979
`Ex. 1046 Klokholm, Erik, Delamination and fracture of thin films,
`IBM J. Res. Develop., Vol. 31, No. 5, September 1987
`Ex. 1047 U.S. Patent No. 4,948,482 to Kobayashi et al., issued
`August 14, 1990
`Isobe et al., Dielectric Film Influence on Stress-
`Migration, June 12-13 IEEE VMIC Conference (1990)
`Ex. 1049 Van de Ven, et al., Advantages of Dual Frequency
`PECVD for Deposition of ILD and Passivation Films,
`June 12-13 IEEE VMIC Conference (1990)
`Ex. 1050 U.S. Patent No. 5,160,998 to Itoh et al., issued
`November 3, 1992
`
`Ex. 1048
`
`vi
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`X
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`X
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`X
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`Ex. 1051 Garrou, Philip, Polymer Dielectrics for Multichip
`Module Packaging, Proceedings of the IEEE, Vol. 80,
`No. 12, December 12, 1992
`Ex. 1052 Grief et al., Warpage and Mechanical Strength Studies of
`Ultra Thin 150MM Wafers, IEEE/CPMT Int’l
`Electronics Manufacturing Technology Symposium
`(1996)
`Ex. 1053 Tatsuno, Sheridan, Japan’s Push into Creative
`Semiconductor Research: 3-Dimensional ICs, Solid State
`Technology, March 1987
`Ex. 1054 Akasaka, Yoichi, Three-Dimensional IC Trends,
`Proceedings of the IEEE, Vol. 74, No. 12, December
`1986
`Ex. 1055 Hayashi, Yoshihiro, Evaluation of Cubic (Cumulatively
`Bonded IC) Devices, 9th Symposium on Future Electron
`Devices, November 14-15, 1990
`Ex. 1056 Williams et al., Future WSI Technology: Stacked
`Monolithic WSI, IEEE Transactions on Components,
`Hybrids, and Manufacturing Technology, Vol. 16, No. 7,
`November 1993
`Ex. 1057 Crowley et al., 3-D Multichip Packaging for Memory
`Modules, MCM ’94 Proceedings, 1994
`Ex. 1058 Malinak, David, Memory-Chip Stacks Send Density
`Skyward, Electronic Design, August 22, 1994
`Ex. 1059 Kuhn et al., Interconnect Capacitances, Crosstalk, and
`Signal Delay in Vertically Integrated Circuits, IEEE
`1995
`Ex. 1060 RESERVED
`Ex. 1061 RESERVED
`Ex. 1062 RESERVED
`Ex. 1063 RESERVED
`Ex. 1064 RESERVED
`Ex. 1065 RESERVED
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`Ex. 1066 RESERVED
`Ex. 1067 Transcript of Teleconference of August 1, 2016
`Ex. 1068 Complaint by Elm 3DS Innovations, LLC against
`Michelle K. Lee and the United States Patent and
`Trademark Office in Case No. 16-cv-01036 in the
`Eastern District of Virginia, dated August 12, 2016
`Ex. 1069 RESERVED
`Ex. 1070 RESERVED
`Ex. 1071 RESERVED
`Ex. 1072 RESERVED
`Ex. 1073 RESERVED
`Ex. 1074 RESERVED
`Ex. 1075 RESERVED
`Ex. 1076 RESERVED
`Ex. 1077 Declaration of Andrew B. Grossman
`Ex. 1078 Declaration of Harold H. Davis, Jr.
`Ex. 1079 RESERVED
`Ex. 1080 U.S. Patent No. 6,204,174 to Glew et al., issued March
`20, 2001
`Ex. 1081 Alexander David Glew, Plasma Deposition of Diamond-
`Like Carbon and Fluorinated Amorphouse Carbon and
`the Resultant Properties and Structure (Dec. 2002), UMI
`No. 3085291
`Ex. 1082 Deposition Transcript of Alexander D. Glew, Ph.D.
`(January 20, 2017)
`Ex. 1083 Chanana, et al., Effect of Annealing and Plasma
`Precleaning on the Electrical Properties of N2/SiH4
`PECVD Oxide as Gate Material in Mosfets and CCDs,
`Solid State Electronics, 36(7):1021-1026 (1993)
`Ex. 1084 Wang et al., Characteristics of CMOS Devices
`Fabricated Using High Quality Thin PECVD Gate
`Oxide, IEDM ’89:463-466 (Dec. 1989)
`
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`Ex. 1085 Milton Ohring, The Materials Science of Thin Films, pp.
`355-402 (Academic Press 1992)
`Ex. 1086 U.S. Patent No. 8,907,499 to Leedy et al., issued
`December 9, 2014
`Ex. 1087 U.S. Patent No. 4,717,448 to Cox et al., issued January 5,
`1988
`Ex. 1088 Schubert, P.J., and Neudeck, G.W., Confined Lateral
`Selective Epitaxial Growth of Silicon for Device
`Fabrication, IEEE Electronic Devices Letters 11(5):181-
`183 (May 1990)
`Ex. 1089 U.S. Patent No. 7,485,571 to Leedy, issued February 3,
`2009
`Ex. 1090 Guldi, R.L., Source/Drain Dislocations and Electrical
`Leakage in Titanium-Salicided CMOS Integrated
`Circuits” J. Electrochem. Soc. 141(7):1957-1963 (July
`1994)
`
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`I.
`
`INTRODUCTION
`
`Petitioner submits this Reply to the PO Response. (Paper 50, “Resp.”). The
`
`evidence of record, including testimony from PO’s expert, Dr. Glew, completely
`
`undermines PO’s arguments. As explained in the Petition (“Pet.”) and below,
`
`claims 1, 2, 8, 14, 31, 32, 44, 46, and 52-54 (“challenged claims”) of the ’778
`
`Patent are unpatentable.
`
` First, PO asserts that plasma-enhanced chemical vapor deposition
`
`(“PECVD”) cannot be used to deposit dielectrics, such as the low tensile stress
`
`dielectrics (“LTSDs”) in Leedy ’6951, during front end of line (“FEOL”) integrated
`
`circuit (“IC”) fabrication. Relying on this flawed premise, PO concludes Leedy
`
`’695’s PECVD LTSDs cannot replace the FEOL dielectrics identified in the cited
`
`prior art. But the dielectrics identified in Bertin (Ex. 1004) are formed during back
`
`end of line (“BEOL”) fabrication. Nevertheless, PO’s distinction between FEOL
`
`and BEOL is of no consequence, given the ’778 Patent and Leedy ’695 do not
`
`place any limit on where in the fabrication process LTSDs can be formed, nor do
`
`they distinguish between FEOL and BEOL. In fact, Leedy ’695 plainly discloses
`
`that its LTSDs can be formed in the FEOL.
`
`
`
` 1
`
` PO acknowledges that the Leedy ’695 “low stress dielectric” is formed by
`
`PECVD and is in low tensile stress. Resp., 38; Ex. 1006, 11:25-64.
`
`1
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`

`

`IPR2016-00387 (U.S. Patent 8,841,778)
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`The ’778 Patent admits that 3D ICs were known in the prior art, relying on
`
`Leedy ’695 as an example. Ex. 1001, 2:19-342. Nowhere does the ’778 Patent
`
`express concern over dielectrics of any kind as a problem to be solved by the
`
`alleged invention. Id., 2:28-43; see also 2:65-3:29 (Summary of the Invention
`
`makes no mention any novelty associated with dielectrics). Thus, PO’s focus on
`
`LTSDs is untethered from the ’778 Patent. The word “tensile” is never used in the
`
`’778 Patent specification. The word “stress” appears in only two passages. Id.,
`
`4:22-27, 8:47-64; see also 2:66-3:29. Where “stress” is discussed, the ’778
`
`specification merely incorporates by reference Leedy ’695 without any guidance on
`
`how to implement such dielectrics in 3D structures. Id., 8:53-64. The lack of
`
`disclosure of “tensile” dielectrics or how to make an LTSD, aside from
`
`incorporating a §102(b) reference, indicates that it was trivial for a POSA to
`
`substitute Leedy ’695’s LTSDs in place of other dielectrics.
`
`PO sets forth a host of purported technical obstacles supposedly preventing
`
`incorporation of Leedy ’695’s LTSDs into prior art ICs. PO ignores, however, that
`
`the ’778 Patent does not address how to overcome any of these obstacles. If these
`
`
` Citations to U.S. patents are to column:line number. Citations to non-patent
`
` 2
`
`publications are to original page numbers (unless reference is made to PO’s
`
`branded exhibit page numbering “PO’s p. _”).
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`obstacles were real, the challenged claims would not be enabled. PO’s alleged
`
`obstacles should be seen for what they are—an attempt to obscure the scope and
`
`content of the prior art.
`
`Second, PO’s response is premised on an incorrect claim construction of
`
`“substantially flexible” that (1) differs from the Board’s construction, (2) lacks
`
`intrinsic support, and (3) is indefinite. Under a proper construction, PO offers no
`
`rebuttal to the conclusion that the “substantially flexible” limitations are met.
`
`II.
`
`3D IC DIELECTRICS COULD HAVE BEEN REPLACED WITH
`LEEDY ’695’S PECVD LTSDS
`A.
`PO’s FEOL Arguments Lack Merit
`PO assumes the dielectrics Petitioner identified in Bertin and Hsu (Ex. 1008)
`
`are FEOL dielectrics, and argues that such FEOL dielectrics cannot be deposited
`
`using PECVD. Resp., 41-44, 46-49. PO is wrong; nothing limits where in the
`
`fabrication process Leedy ’695’s LTSDs can be formed.
`
`1.
`
`Leedy ’695 Teaches Using PECVD To Deposit LTSDs In The
`FEOL
`
`PO contends that FEOL ends and BEOL begins with the “addition of the
`
`metal systems necessary to connect the different components.” Resp., 15; see also
`
`Ex. 1082, 27:10-12. Per Dr. Glew, that means “whenever we’re making
`
`transistors, we’re in the front end” (Ex. 1082, 142:3-5), including when forming
`
`contacts to the semiconductor or transistors (id., 146:19-147: 18). See also id.,
`
`16:1-5.
`
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`Applying this understanding, Leedy ’695 confirms that its LTSDs can be
`
`formed in the FEOL using PECVD. For example, the LTSD in claim 16 of Leedy
`
`’695 is formed in the FEOL because it is deposited before “forming electrical
`
`interconnections…between the semiconductor devices.”3 Ex. 1006, 48:43-52; Ex.
`
`1082, 27:18-20, 90:12-15, 141:6-17. Dr. Glew confirmed that this LTSD,
`
`deposited “over the semiconductor devices,” is FEOL: “[d]ielectrics that are
`
`formed on semiconductor devices are in the front end.”4 Ex. 1082, 27:18-20.
`
`Leedy ’695 also describes several examples of using PECVD to form LTSDs
`
`in the FEOL. See Ex. 1006, FIGS. 9a-9e, 17:7-18:2; FIGS. 9f-9i, 18:3-50; FIG. 9j,
`
`18:51-56; FIG. 10d, 19:48-64; FIG. 11f, 21:21-27; FIG. 12a-d, 22:16-23:27; FIG.
`
`12e, 22:18-57, 23:28-30; FIG. 12f, 22:18, 23:43-47; FIG. 12g, 23:53-57.
`
`For example, LTSD 20, shown in FIG. 1c below is an FEOL dielectric.
`
`LTSD 20 “serves as an isolation dielectric between adjacent semiconductor
`
`
` 3
`
` Emphasis in italics added herein.
`
`4 U.S. Patent No. 7,485,571 (Leedy ’571, Ex. 1089), a continuation of Leedy ’695,
`
`states that LTSDs are formed “overlying selected ones of said sources, drains, and
`
`gates” (claims 30 and 32). Because metal interconnections must later be formed to
`
`have a functioning IC, the LTSD in these claims is FEOL. Ex. 1082, 27:18-19,
`
`141:6-17, 171:17-174:9.
`
`4
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`

`IPR2016-00387 (U.S. Patent 8,841,778)
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`devices.” Id., 8:31-39, FIG. 1c.5 It is FEOL applying Dr. Glew’s definition
`
`because “trench isolation” necessarily uses FEOL dielectrics. See Ex. 1082,
`
`125:19-126:10, 127:16-128:5.
`
`
`
`LTSD 204 is another FEOL dielectric because it is part of the “starting
`
`substrate structure,” adjacent to the silicon semiconductor, and formed before any
`
`interconnecting metallization. Ex. 1006, 18:63-19:64, FIG. 10a (LTSD 204 but no
`
`interconnecting metallization). LTSD 204 is also FEOL because it is formed
`
`during “MOSFET transistor” fabrication. See Ex. 1006, 18:63-64, 19:4-64 (LTSD
`
`204 is formed before doping and forming gate region 220/222 and gate oxide 232);
`
`Ex. 1082, 16:1-5, 142:3-5. In fact, after LTSD 204 formation, “trench isolation”—
`
`
`
` 5
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` Blue annotations herein added by Petitioner.
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`which is FEOL per Dr. Glew—is performed. Ex. 1006, 19:4-17, FIG. 10b; Ex.
`
`1082, 125:19-126:10, 127:16-128:5.
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`
`
`LTSD 178 is another FEOL dielectric formed adjacent to silicon
`
`semiconductor 176, before any interconnecting metallization. See Ex. 1006,
`
`17:15-18; FIG. 9a. LTSD 178 is FEOL because it is formed during the process of
`
`making transistors. See Ex. 1006, 17:8-55; 17:15-24 (after LTSD 178 formation,
`
`device wells 180 are formed); 17:43-46. In fact, after LTSD 178 is formed, two
`
`processes—contact formation and “trench isolation”—both FEOL per Dr. Glew,
`
`are performed. Id., 17:54-55; Ex. 1082, 125:19-126:10, 127:16-128:5, 147:3-5,
`
`147:14-15.
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`IPR2016-00387 (U.S. Patent 8,841,778)
`IPRZO16-00387 (U.S. Patent 8,841,778)
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`176
`
`Silicon layer 176
`
`LTSD layer 178
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`174
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`178
`
`Fig_9a
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`Device well 180
`
`LTSD layer 173
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`“'5
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`Silicon layer 176
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`LTSD 209 is another FEOL dielectric formed adjacent to silicon
`
`semiconductor 201 before any interconnecting metallization. See Ex. 1006, 18:51-
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`56. LTSD 209 is FEOL because it is formed during the process of making a
`
`transistor. Ex. 1006, 18:51-56 (LTSD 209 formed before electrodes 211/213); Ex.
`
`1082, 142:3-5.
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`LTSD 277 is another FEOL dielectric because it is formed directly adjacent
`
`to transistor “semiconductor layer 275” and source/gate/drain regions 269/271/273
`
`before any interconnecting metallization. Ex. 1006, 21:21-41; Ex. 1082, 27:18-20.
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`2.
`
`Prior Art Literature Proves That PECVD Is Used In FEOL
`
` Other prior art also disproves PO’s assertion that “PECVD cannot be used
`
`to produce FEOL dielectrics” (Resp., 24). See, e.g., Ex. 1083, 1025-26 (PECVD
`
`dielectrics are “suitable gate material for MOSFETs” with properties “comparable
`
`to the dry thermally grown oxide”); Ex. 1084, 17.6.2 (“a high quality thin PECVD
`
`gate oxide has been used in the fabrication of…CMOS devices” “comparable to
`
`thermal oxide devices without the need of high temperature process and oxidation
`
`steps”); Ex. 1090, 1957 (“use of…(PECVD) oxide as a PMD layer has been shown
`
`to result in reduced S/D dislocation density” and “lower defect densities than
`
`LPCVD oxides”); Ex. 1082, 142:3-5.
`
`3.
`
`PECVD Dielectrics Are Compatible With Silicon Substrates
`And High Temperature Processes
`
`a)
`
`High Temperature
`
`
`
`Leedy ’695 refutes PO’s assertion that PECVD dielectrics are incompatible
`
`with high-temperature processes (Resp., 27, 38, 39, 44). Leedy ’695 teaches
`
`performing high temperature silicon epitaxial growth (Ex. 1082, 107:19-108:9) on
`
`substrates having a LTSD, such as in FIGS. 12a-d (annotated below). See Ex.
`
`1006, 21:53-22:8 (citing Ex. 1088); Ex. 1006, 22:16-23:5, FIGS. 12a-d (epitaxial
`
`growth of transistor structures 294 and 296 on substrate having LTSD 282), 18:60-
`
`19:64, FIGS. 10a-d (epitaxial growth of silicon 220 and 222 on substrate having
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`LTSD 204), 18:11-50, FIGS. 9f-h (epitaxial growth 201 in the patterned opening
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`195 of LTSD 191); Ex. 1088, Abstract, 182 (epitaxial growth at 1000°C).
`
`
`
`
`
` Leedy ’695 also teaches depositing LTSDs before silicide formation, which
`
`contradicts PO’s argument that silicide formation is a high-temprature step that
`
`precludes having LTSDs in FEOL. Ex. 1082, 62:10-17; Ex. 1006, 19:48-64, FIGS.
`
`10c-d (silicidation of electrode 230 formed on LTSD 204).
`
`
`
`Further, PO’s reliance on Ex. 2169 for its argument that tensile stress
`
`PECVD films become compressive due to “FEOL heating steps and anneals” is
`
`misplaced. Resp., 66 (citing Ex. 2169, PO’s pp. 29-30). The cited passage from
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`12
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`Section “13.4.1.1.2 Low Temperature Oxide,” discusses how “low-temperature
`
`CVD oxide films” subsequently heated to 700°C-1000°C can become compressive.
`
`Ex. 2169, PO’s pp. 29. Another section of this exhibit (Section “13.4.1.1.1
`
`Plasma-Enhanced CVD (PECVD)…”) (Id., PO’s p. 28), which PO does not cite,
`
`addresses PECVD films but does not state that stress conversion occurs at high-
`
`temperatures. In fact, the low-temperature CVD section PO cited specifically
`
`distinguishes low-temperature CVD from PECVD. Id., PO’s pp. 29-30 (“[u]nlike
`
`PECVD….”). PO’s argument about Ex. 1040 (see Resp., 39) is similarly
`
`misplaced, as the cited evidence does not state that the disclosed SixNyHz dielectric
`
`(or any other PECVD dielectric) is formed in tensile stress and converted to
`
`compressive after heating. Ex. 1040, 192.
`
`This argument contradicts Leedy ’695’s disclosure that its LTSD “can
`
`withstand processing temperatures in excess of 400°C” and lists “annealing or
`
`epitaxial processing” such as “annealing or epitaxial processing.” Ex. 1006, 9:34-
`
`49; see also claim 14, 17:7-54, 45:49-56. Moreover, PO’s argument rests on an
`
`erroneous premise that a high-temperature anneal is necessary. Ex. 1083, 1021
`
`(“[L]ow temperature ([e.g.,] 450°C)” anneal can be used after depositing PECVD
`
`dielectrics).
`
`PO’s contention is also refuted by other claims in the ’778 Patent family.
`
`For example, claim 12 of U.S. Patent 8,907,499 (see IPR2016-00703) recites a
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`“circuit” having “a silicon-based dielectric layer formed on the thin semiconductor
`
`layer and having a stress of less than 5×108 dynes/cm2 tensile [i.e., an LTSD].”
`
`Ex. 1086, claim 12; see also claim 1. Dr. Glew confirmed that this type of
`
`dielectric layer is the FEOL. Ex. 1082, 27:18-20, 173:1-3. If PO’s argument
`
`regarding temperature were true, it would be impossible to practice this claim
`
`because FEOL processing would convert the LTSD to a compressive dielectric.
`
`b)
`
`Compatibility With Silicon Substrate
`
` Leedy ’695, by using PECVD to form LTSDs adjacent to semiconductor
`
`and circuit components—as discussed in Section II.A.1—likewise refutes PO’s
`
`assertion that PECVD dielectrics would not be “sufficiently pure,” would not
`
`“have the ability to adhere sufficiently to the silicon substrate,” or would “damage”
`
`the substrate. Resp. 62-63, 65. As PO admits, Leedy ’695’s use of PECVD to
`
`form LTSDs in contact with semiconductor and circuit components indicates such
`
`LTSDs must be “high-purity.” See id., 43 (“[I]f a silicon dioxide dielectric
`
`contacts circuit components, the silicon dioxide must be high-purity to not damage
`
`the circuit components.”), 46-47. That Leedy ’695 uses PECVD to form LTSDs
`
`adjacent semiconductor and circuit components indicates such dielectrics were
`
`sufficiently “pure,” “adhered to,” and did not unacceptably “damage” the
`
`semiconductor or circuit components.
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`PO cites Runyan (Ex. 2159) for its argument that “ions present in the
`
`plasma” of PECVD would damage the substrate. Resp., 45. Runyan, however,
`
`explains that PECVD can be performed using a “reactor geometry,” such that “the
`
`plasma is located away from the wafers,” preventing damage to the wafers. Ex.
`
`2159, 139.
`
`Dr. Glew’s admission that plasma-based etch processes are frequently used
`
`adjacent a silicon substrate further refutes the argument that PECVD is
`
`incompatible with silicon substrates. Ex. 1082, 130:21-132:11.
`
`4.
`
`Silicides Are Not Required—FEOL Dielectrics Need Not
`Undergo High-Temperature Processing
`
`
`
`PO contends that silicide formation at “high temperatures” was “necessary”
`
`and thus precludes use of LTSDs in the FEOL. Resp., 15. Not so. PO’s own
`
`evidence suggests “an aluminum alloy”—not a silicide—can be used to form
`
`contacts for transistor regions (e.g., source, drain, or gate). Ex. 2158, 81 (in “Step
`
`9: Layering Operation,” an “aluminum alloy” is deposited over the entire wafer in
`
`the contact holes to the source, gate, and drain areas). Further, Dr. Glew admitted
`
`that prior art devices “didn’t necessarily use silicides.” Ex. 1082, 71:7-10.
`
`
`
`Moreover, it was well-known that there are metals that could be used to
`
`contact silicon devices without forming silicides. Aluminum and aluminum:silicon
`
`alloy are two examples of “conventional ohmic-contact structures to silicon.” Ex.
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`2146, 102, 111. Such contacts are formed at low temperatures. Ex. 1082, 90:14-
`
`15 (“aluminum is limited to 450 °C”), 90:16-91:1; Ex. 2146, 113.
`
`
`
`Even assuming that silicide formation was necessary, it was known that a
`
`number of silicides could be formed at low temperatures (much lower than the
`
`700+°C PO alleges). See Ex. 1085, 389-92; Ex. 2146, 117 (“Platinum Silicide-to-
`
`Silicon Contact” “formed…at low temperatures (250-400 °C)”), 118 (Platinum-
`
`Silicide contacts “provide low contact resistivity”).
`
`These facts coupled with the fact that Bertin and Hsu do not mention, much
`
`less require, silicides, refute PO’s arguments.
`
`5.
`
` PECVD Was A Viable Process For Forming Silicon Dioxide
`And Silicon Nitride LTSDs
`
` While PO complains of purported drawbacks (Resp., 21-22) of PECVD
`
`silicon dioxide films, Leedy ’695 and third party literature confirm that PECVD
`
`was a viable process for forming both silicon dioxide and silicon nitride dielectric
`
`films. Ex. 1006, 11:25-65; Ex. 1083, 1025-26; Ex. 1084, Abstract, 17.6.2-3; Ex.
`
`1090, 1957.
`
`PO relies on Exhibits 2162 and 2159 in support of its position. Exhibit
`
`2162, PO’s pp. 301-303, reported a comparison of PECVD silicon dioxide with a
`
`polymer material, not with silicon dioxide prepared by an alternative process.
`
`Exhibit 2159 discusses CVD silicon dioxide, not PECVD silicon dioxide. Neither
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`exhibit allows any conclusion to be drawn regarding PECVD silicon dioxide as
`
`compared with silicon dioxide prepared by another process.
`
`III. THE CHALLENGED CLAIMS ARE OBVIOUS
`The test for obviousness is not whether the features of one reference may be
`
`bodily incorporated into another reference’s structure, but rather “what the
`
`combined teachings of the references would have suggested” to a POSA. In re
`
`Keller, 642 F.2d 413, 425 (CCPA 1981). PO ignores the Petition’s proper
`
`obviousness rationales.
`
`A. The Petition Establishes That A POSA Would Have Been
`Motivated To Combine Prior Art Teachings
`
` As Dr. Franzon explained, it was well known at the time of the alleged
`
`invention that reducing a film’s stress—whether compressive or tensile—was
`
`beneficial because it leads to reduced bending, a decreased likelihood of
`
`“mechanically induced problems,” and increased yield, among other advantages.
`
`Ex. 1002, ¶¶23, 26-27, 29-34, 37-38. Dr. Glew admitted that “one of skill in the
`
`art would understand that it wasn’t desirable to have excessive stress.” Ex. 1082,
`
`154:8-13; Ex. 1081, v, 8, 23. PO does not dispute that Leedy ’695 addresses this
`
`well-known desire by describing LTSDs for reducing stress. See, e.g., Pet., 17-19,
`
`20-23, 44-47; Ex. 1002, ¶¶101-14. Thus, a POSA would have been encouraged to
`
`look to Leedy ’695 when choosing a dielectric to use in the stacked circuit
`
`structures described in Bertin or Hsu. See Pet., 20-23, 44-47; Ex. 1002, ¶¶101-14.
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`In addition to the general knowledge that low stress is desirable, as
`
`explained in the Petition, Leedy ’695 describes many benefits of its LTSDs that
`
`would have motivated a POSA to use them in the stacked circuit structure taught
`
`by Bertin/Hsu:
`
`(1) enhancing structural integrity and surface flatness of stacked circuit
`
`structures (Pet., 21; Ex. 1002, ¶¶110, 124 (pp. 77), 125 (pp. 95));
`
`(2) reducing likelihood of heat damage (Pet., 22-23; Ex. 1002, ¶¶ 110-11);
`
`and
`
`(3) providing a dielectric that can withstand heat from subsequent processing
`
`(Pet., 22-23, 46; Ex. 1002, ¶¶110, 124 (pp. 77), 125 (pp. 95); Ex. 1082, 167:9-12).
`
`PO ignores these benefits. First, PO failed to rebut that Leedy ’695’s LTSD
`
`would have improved structural integrity and surface flatness of the stacked circuit
`
`structures taught by Bertin/Hsu. As shown, it was known, “[b]y 1990…[that] the
`
`way to avoid mechanical stress-related issues due to high stress films placed
`
`directly on the substrate was to use low tensile stress dielectrics.” See e.g., Ex.
`
`1002, ¶32 (citing Kobayashi (Ex. 1047)); see also id., ¶¶31, 33-44. Kobayashi
`
`discloses dielectric films with “preferably [] an internal stress of 10.0 x 108
`
`dyn[es]/cm2 or less in terms of tensile stress” formed on an “Si [silicon] substrate.”
`
`Ex. 1047, 4:7-9; see also id. Abstract, 2:20-30, 5:2-3.
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`IPR2016-00387 (U.S. Patent 8,841,778)
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`While Dr. Glew asserts that an LTSD has no “redeeming characteristics”
`
`unless it is freestanding (Ex. 1082, 167:1-168:3), such an assertion is unsupported