`Leedy
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,485,571 B2
`*Feb. 3, 2009
`
`US007485571B2
`
`(56)
`
`References Cited
`|U.S. PATENT DOCUMENTS
`2,915,722 A 12/1959 Foster ........................ 336/115
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`DE
`
`-
`
`-
`
`3/1983
`32 33 195
`(Continued)
`OTHER PUBLICATIONS
`“IC Tower Patent. Simple Technology Receives Patent on the IC
`Tower, a Stacked Memory Technology,” http://www.simpletech.
`com/whatsnew/memory/(a)60824.htm (1998).
`(Continued)
`Primary Examiner—Zandra V. Smith
`Assistant Examiner—Pamela E Perkins
`(74) Attorney, Agent, or Firm—Rope & Gray LLP, Jeffrey C.
`Aldridge; Matthew S. Bertenthal
`(57)
`ABSTRACT
`
`General purpose methods for the fabrication of integrated
`circuits from flexible membranes formed of very thin low
`stress dielectric materials, such as silicon dioxide or silicon
`nitride, and semiconductor layers. Semiconductor devices are
`formed in a semiconductor layer of the membrane. The semi
`conductor membrane layer is initially formed from a sub
`strate of standard thickness, and all but a thin surface layer of
`the substrate is then etched or polished away. In another
`version, the flexible membrane is used as support and elec
`trical interconnect for conventional integrated circuit die
`bonded thereto, with the interconnect formed in multiple
`layers in the membrane. Multiple die can be connected to one
`such membrane, which is then packaged as a multi-chip mod
`ule. Other applications are based on (circuit) membrane pro
`cessing for bipolar and MOSFET transistor fabrication, low
`impedance conductor interconnecting fabrication, flat panel
`displays, maskless (direct write) lithography, and 3DIC ?ab
`rication.
`
`198 Claims, 64 Drawing Sheets
`
`(54) METHOD OF MAKING AN INTEGRATED
`CIRCUIT
`(75) Inventor: Glenn J Leedy, Saline, MI (US)
`(73) Assignee: Elm Technology Corporation, Saline,
`MI (US
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 98 days.
`This patent is subject to a terminal dis-
`
`(*) Notice:
`
`claimer.
`
`21) Appl. No.: 10/665,757
`(21) App
`s
`(22) Filed:
`Sep.19, 2003
`(65)
`Prior Publication Data
`
`|US 2005/0176174 A1
`
`Aug. 11, 2005
`-
`- -
`Related U.S. Application Data
`(60) Continuation of application No. 09/775,597, filed on
`Feb. 5, 2001, now Pat. No. 6,682.981, which is a con
`tinuation of application No. 09/027,959, filed on Feb.
`23, 1998, now abandoned, which is a division of appli-
`? No 08/850,749 ???d on May 2, 1997, now Pat
`-
`-
`? s
`
`???
`
`... , ????
`No. 5,985,693, which is a continuation of application
`No. 08/315,905, filed on Sep. 30, 1994, now Pat. No.
`5,869,354, and a division of application No. 07/865,
`412, filed on Apr. 8, 1992, now Pat. No. 5,354,695.
`(51) Int. Cl.
`(2006.01)
`H0 HL 2 H/4763
`200 6. 01
`H0 HL 21/06)
`(
`.01)
`(2006.01)
`H0 HL 2 H/76
`(52) U.S. Cl. ............................. 438/626; 438/6: 438/53;
`438/406
`(58) Field of Classification Search ..................... 4386,
`438/17, 53. 406, 411, 479, 626
`See application file for complete search history.
`
`20
`
`
`
`% %
`
`18
`
`Page 1 of 97
`
`SAMSUNG ET AL. EXHIBIT 1089
`Samsung et al. v. Elm 3DS Innovations, LLC
`IPR2016-00387
`
`
`
`US 7,485,571 B2
`
`Page 2
`
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`.
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`Page 2 of 97
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`Page 2 of 97
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`
`
`US 7,485,571 B2
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`Page 3 of 97
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`1
`METHOD OF MAKING AN INTEGRATED
`CIRCUIT
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a continuation of commonly assigned
`U.S. patent application Ser. No. 09/775,597, filed Feb. 5,
`2001 , now U.S. Pat. No. 6,682,981, which is a continuation of
`U.S. patent application Ser. No. 09/027,959, filed Feb. 23,
`1998 now abandoned, which is a division of U.S. patent
`application Ser. No. 08/850,749, filed May 2, 1997, now U.S.
`Pat. No. 5,985,693, which is a continuation of U.S. patent
`application Ser.