IEEE ELECTRON DEVICE LETTERS, VOL. 11, NO. 5, MAY 1990
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`181
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`Confined Lateral Selective Epitaxial Growth of
`Silicon for Device Fabrication
`
`Abstract-A novel epitaxy technique, called confined lateral selective
`epitaxial growth (CLSEG), is introduced which produces wide, thin slabs
`of single-crystal silicon over insulator, using only conventional process-
`ing. As-grown films of CLSEG 0.9 pm thick, 8.0 pm wide, and 500 pm
`long were produced at 1000°C at reduced pressure. Junction diodes
`fabricated in CLSEG material show ideality factors of 1.05 with reverse
`leakage currents comparable to diodes built in SEC homoepitaxial
`material. Metal-gate p-channel MOSFET’s in CLSEG with channel
`dopings of 2 x 1OI6 c m - 3 exhibit average mobilities of 283 cm2/V-s and
`subthreshold slopes of 223 mV/decade.
`
`I. INTRODUCTION
`HE PUSH towards smaller active device size for faster
`
`T microelectronics is reaching several fundamental limits.
`
`improvements can still be achieved by
`Yet, significant
`reducing the area used for inter-device isolation. Silicon-on-
`insulator (SOI) is of particular promise due to its dielectric
`isolation, design transparency, and radiation hardness. Draw-
`backs of SO1 include difficulty of fabrication, wafer stress,
`defects in the silicon film, and total cost. An alternative to
`whole-wafer SO1 is the epitaxial lateral overgrowth (ELO)
`technique where single-crystal is grown out of a seed hole in
`an insulating mask layer both vertically to form homoepitaxy
`islands, and laterally to form local SO1 regions [l]. However,
`aspects ratios (lateral growth distance divided by vertical
`growth height) of local-SO1 E L 0 over thick oxides are limited
`to unity [2]. This requires that E L 0 silicon be thinned to
`extract the benefits of an SO1 technology. Thinning by
`planarization etches or by chemical-mechanical polishing have
`thus far resulted in low yields, and suffer from poor uniformity
`across a wafer.
`This paper presents a new selective epitaxy technique which
`produces thin, but wide films of single-crystal silicon on top of
`a dielectric insulating layer. This method is called confined
`lateral selective epitaxial growth (CLSEG), and consists of
`filling a cavity, whose walls are made of dielectric materials,
`with selective silicon epitaxy [3]. CLSEG is a new low-
`temperature epitaxial growth technique using only conven-
`tional silicon process equipment. It produces films of high
`uniformity, large aspect ratio for local SO1 isolation, device
`quality material, and has applications for the fabrication of
`advanced device structures.
`
`Manuscript received November 14, 1989; revised February 8, 1990. This
`work was supported by the Semiconductor Research Corporation under
`Contract 90-SJ-108 and by a General Motors Fellowship.
`The authors are with the School of Electrical Engineering, h r d u e
`University, West Lafayette, IN 47907.
`IEEE Log Number 9035477.
`
`SILICON NITRIDE
`TOP LAYER,
`
`SILICON SUBSTRATE
`
`(a)
`
`VIA HOLE
`
`I
`
`SILICON SUBSTRATE
`
`VIA HOLE .
`
`1
`
`SILICON SUBSTRATE
`
`I
`
`(C)
`Fig. 1. Key fabrication steps for CLSEG. (a) Layer formation and
`definition. (b) Definition of via hole and etch of sacrificial layer to form
`cavity. (c) Confined lateral selective epitaxial growth of silicon in the
`cavity
`
`11. FABRICATION
`in the
`The fabrication steps for CLSEG are illustrated
`silicon
`schematic cross section in Fig. 1. A thick layer of
`dioxide is thermally grown on a (100) silicon substrate, called
`the bottom-layer oxide. Then a seed hole is patterned through
`it, oriented along the (010) direction. A very thin layer of
`oxide is regrown in the seed hole to heal RIE damage and to
`protect against a silicon wet etch later in the process. Next a
`sacrificial layer of amorphous silicon is deposited and pat-
`terned to cover the seed hole and extend some lateral distance
`beyond it. The thickness and shape of the sacrificial layer
`establish the growth cavity dimensions. To provide a thermal
`oxide lining for the cavity, the sacrificial layer is partially
`oxidized at 1000°C to about 100 nm. This converts the
`amorphous silicon to polycrystalline silicon, but it still retains
`the surface smoothness helpful in reducing defects [4]. Then
`the entire structure is covered with a thin (110 nm) layer of
`stoichiometric silicon nitride for mechanical support of the top
`layer of the cavity as shown in Fig. l(a). Then via holes are
`etched through the nitride and oxide top layers, followed by a
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`0741-3106/90/0500-0181$01.00 O 1990 IEEE
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`Page 1 of 3
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`SAMSUNG ET AL. EXHIBIT 1088
`Samsung et al. v. Elm 3DS Innovations, LLC
`IPR2016-00387
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`

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`182
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`IEEE ELECTRON DEVICE LETTERS, VOL. 1 I , NO. 5 , MAY 1990
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`20
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`15
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`4
`W 3 8 10 E
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`BOlTOM OXIDE INTACT
`
`Fig. 2. Electron micrograph of cleaved CLSEG sample showing side and
`partial top view. Growth proceeded from left to right, and the bottom oxide
`layer has been removed. The as-grown film is 0.9 pm high and 7.63 pm
`wide, for an aspect ratio of 8.5.
`
`5
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`0
`
`selective isotropic etch to entirely remove the polysilicon
`sacrificial layer. An ethlyene diamine based solution at 90°C
`etched the polysilicon at about 1 pm/min. This leaves a cavity
`with the seed hole deep within, as illustrated in Fig. l(b). Once
`the thin protective oxide layer in the seed window is etched
`away, epitaxy process gases can enter the cavity through the
`via hole and growth can occur at the exposed silicon of the
`seed hole. To render CLSEG growth, the epitaxy gas
`composition, temperature, and reactor pressure are adjusted so
`that silicon deposition occurs only on silicon already present,
`and not on the dielectric walls of the cavity. In this manner, the
`cavity can fill cleanly from left to right, resulting in a thin but
`wide slab of single-crystal silicon over insulator, as shown in
`Fig. l(c).
`layer was 860 nm of
`For this work, the sacrificial
`amorphous silicon before crystalization and oxidation, while
`the bottom oxide thickness was 133 nm to avoid pinholes
`during growth [ 5 ] . The CLSEG was grown in a SiH2Cl2-HC1-
`H2 system at 1000°C and 50 torr, with the HC1-to-SiH2C12 gas
`ratio adjusted to give lateral growth rates of 0.2 to 0.25 pm/
`min. Phosphine gas was added to dope the epitaxy n-type to
`2 x 1016cm-3.
`To provide a standard of comparison for the device quality
`of CLSEG material, large-area homoepitaxy islands (also
`called SEG, for selective epitaxial growth) were grown from
`the substrate simultaneously with the CLSEG growth. Junc-
`tion diodes and metal-gate p-channel MOSFET’s were formed
`both in 8-pm-wide CLSEG films and in the homoepitaxy
`islands. Their I- I/ characteristics were then measured and
`compared [6]. To fabricate the devices after CLSEG growth,
`the silicon nitride and silicon dioxide top layers were etched
`away and a 75-nm-thick oxide was grown at 900°C. Boron-
`doped regions for diodes and MOSFET source/drains were
`formed by implantation, followed by an arsenic implantation
`to provide ohmic contact to the n-type epitaxy regions. A final
`oxidizing anneal was performed at 900°C to give a gate oxide
`thickness of 132 nm. Contact window areas were dry etched to
`90% of endpoint, then finished with a wet etch. The
`metallizaton (Al-Cu-Si) was 1 .O pm thick and formed the gate
`electrode for the MOSFET devices.
`
`111. RESULTS
`CLSEG lateral growth rates and the vertical growth rate of
`homoepitaxy islands are found to be equal within t 1 % for
`cavities 0.9 pm high, and independent of CLSEG cavity width
`to at least 12 pm. Fig. 2 is an electron micrograph of a cleaved
`sample of CLSEG showing the smooth top surface. Note that
`the seed hole is located at the left side, and growth has
`
`0
`
`1.00
`
`1.10
`
`1.20
`
`1.30
`
`1.40
`
`IDEALITY FACTOR (BIN SIZE=0.05)
`Fig. 3. Histogram of ideality factors for diodes in CLSEG silicon. Data
`taken from one diode per die in a 5 x 6 array of die. The value 4 = 0 is
`chosen for short-circuited devices.
`
`TABLE I
`AVERAGED DEVICE CHARACTERISTICS FOR P-CHANNEL METAL-GATE
`MOSFET’S IN CLSEG AND HOMOEPITAXIAL ISLAND SILICON MATERIAL
`
`proceeded to the right. The CLSEG film is 0.9 pm thick and
`has an aspect ratio of 8.5, a new result for as-grown films.
`Preliminary results indicate that CLSEG aspect ratios of at
`least 20 are possible with adequate cavity design.
`Electrical parameter extraction was used to characterize the
`crystal quality of CLSEG silicon and its applicability to device
`fabrication [6]. From junction diodes the ideality factor 17 was
`obtained by empirical matching of the forward diode curves to
`the Shockley equation:
`
`ID=IS(e4VD’?kT- 1)
`
`In processing the diodes, it was anticipated that incomplete
`bonding between the CLSEG silicon and the bottom oxide
`could result in large reverse leakage currents [4]. To evaluate
`this effect, some diodes had the bottom oxide completely
`etched away (with aqueous HF) prior to the 75-nm thermal
`oxidation. Fig. 3 shows a histogram of the diode ideality factor
`from a 5 x 6 array of die covering approximately 5 cm2.
`Results are shown for each of two wafers, one with the bottom
`oxide intact, and the other with the bottom layer removed.
`Values of 7 = 0 are chosen for diodes exhibiting short
`circuits. The average 7 value for the solid fill data of Fig. 3,
`from a wafer with the bottom oxide layer intact after CLSEG
`growth, is 1.05. The average value from the shaded fill data is
`7 = 1.14, from a wafer with the bottom oxide completely
`removed prior to the 75-nm oxide growth. Average reverse
`leakage currents measured at -3.0 V were -51.0 and
`- 234.5 pA for the oxide-intact and oxide-removed devices,
`respectively. Comparable values for diodes in the homoepi-
`taxy islands are 7 = 1.03 with reverse leakage currents of
`- 53.7 PA.
`P-channel MOSFET’s with a W / L ratio of 7.25 in both
`CLSEG and in homoepitaxy islands were tested to extract hole
`mobility, subthreshold slope, and leakage current with
`grounded gate and a drain-to-source voltage of - 2.5 V. These
`results are summarized in Table I, where each value is an
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`Page 2 of 3
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`SCHUBERT AND NEUDECK: CONFINED LATERAL SELECTIVE EPITAXIAL GROWTH
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`183
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`average from six devices. The threshold voltage for both type
`of devices is -4.6 V, and yields an interface fixed charge
`density of 4 X 10” cm-2. The values for mobility and
`subthreshold slope listed are consistent with the doping level
`o f 2 x 1 0 1 6 ~ ~ - 3 .
`
`IV. DISCUSSION
`The growth of CLSEG within an oxide-walled cavity forms
`single-crystal silicon suitable for the fabrication of devices.
`Near-unity values for the ideality factor show that recombina-
`tion processes are relatively insignificant in CLSEG films,
`indicating that thermal stress is not sufficient to degrade device
`performance. Reverse leakage currents for diodes in CLSEG
`with the bottom layer intact after the growth are virtually equal
`to those for the control devices in the homoepitaxy islands.
`Removal of the bottom oxide and reoxidation appreciably
`increase both the reverse leakage current and ideality factor in
`CLSEG diodes. This is presumably due to oxidation-induced
`stress at the corners of the CLSEG slab.
`The MOSFET data for interface charge density, carrier
`mobility, subthreshold behavior, and the small leakage current
`demonstrate that the CLSEG surface after reoxidation is as
`free of surface defects as the homoepitaxy. The relatively
`smooth topography of the amorphous-silicon sacrificial layer
`is important to the high mobility values. Previous results using
`LPCVD-deposited polysilicon as the sacrificial layer clearly
`showed a rough texture on top of the CLSEG, which can lead
`to growth defects and decreased mobilities through scattering.
`The close agreement between devices made in CLSEG and
`in homoepitaxy island silicon demonstrates the nearly equiva-
`lent material quality. Others have reported that devices in
`homoepitaxy islands (SEG) are equivalent to devices built in
`substrate silicon [6], so we infer that CLSEG material is of
`essentially equal quality to CZ-grown device-quality silicon
`substrates. A modification of the CLSEG concept can be used
`to obtain full, unpatterned SO1 wafers [7].
`
`V, CONCLUSIONS
`We have demonstrated for the first time SO1 aspect ratios of
`8.5 for as-grown silicon films using the CLSEG technique.
`CLSEG is achieved at low temperatures using conventionally
`available processing equipment and techniques. The film
`height is well-controlled and uniform across a substrate since it
`is set by the thickness of a vapor-deposited sacrifical layer.
`Junction diodes and metal-gate MOSFET’s in both CLSEG
`and homoepitaxial island silicon show nearly identical charac-
`teristics, indicating excellent material quality. The structural
`versatility and high crystal quality of this new CLSEG
`technique demonstrate the promise of the technology as a tool
`for advanced device isolation and the construction of novel
`device structures.
`
`ACKNOWLEDGMENT
`The authors gratefully acknowledge Delco Electronics
`Corporation for their invaluable support of this work.
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