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`‘ UNITED STATEE PATENT AND
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`OFFICE
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`In re application of:
`Serial No.:
`Filed;
`For;
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`Attorney Docket No.:
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`TINGP. YEN
`08/561,951
`November 22, 1995
`METAL PLUG LOCAL
`INTERCONNECT
`64,663-O04
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`Group Art Unit: 2503
`Examiner: WALLACE, V.
`In Response to Ofiice Action
`gfip/:rp 1996
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`REC ENED
`AUG 2 3 19%
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`P’
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`Certificate ofMailing (37CFR 1.8a)
`I hereby certify that this paper (along with any referred to as being attached or enclosed) is being deposited with the United
`States Postal Service on the date shown below with sufficient postage as first class mail in an envelope addressed to the Assistant
`Commissioner for Patents, Washington D.C. 20231.
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`Date:August 14, 1996 (Signature of person maili
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`Assistant Commissioner for Patents
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`Washington, D.C. 20231
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`Dear Sir:
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`A M E N D M E N T
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`In response to the Oflice Action mailed April 17, 1996, please consider the following
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`amendments and remarks regarding the above-identified application.
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`INTEL 1114
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`Please cancel claims 1 and 7, and replace with the new claims 13 and 14.
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`IN THE CLAIMS
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`/
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`A semiconductor structure comprising:
`1§\
`a sili on substrate having atop surface,
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`a diffiusi n region formed in said substrate adjacent to said top surface,
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`a polysilic
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`gate formed on the top surface of said substrate juxtaposed to but not
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`contacting said diffusion regi
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`ii,
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`an insulator layer ubstantially covering said polysilicon gate and said difliision region,
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`and
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`aiconducting plug at le
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`electrical communication between said
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`lysilicon gate and said difliision region.
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`t partially filling a via in said insulation layer, providing direct
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`local interconnect in a semiconductor structure,
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`14.
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`A method of forming
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`comprising the step of:
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`depositing an electrically conductin material in a via exposing at least a portion of
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`a gate and a portion of a diffusion region such that said
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`ectrically conducting material contacts and
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`provides electrical communication between said gate and aid diffusion region, said semiconductor
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`structure comprising said diffusion region in a silicon subst
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`te, said gate being on said substrate
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`juxtaposed to but not contacting said diffusion region, said via be g in an insulating material on said
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`gate.
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`Amend clai
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`s 2~6 an 8~l2 as follows:
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`1, d:/Xv/claim l", and substitutetherewith--claim 13--.
`Claim2 1i
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`Claim‘ , line
`etc “
`im 1", and substitute therewith --claim 13--.
`Claim 4,
`' e 1 del e“cl 'm 1", and substitute therewith --claim 13--.
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`Claim
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`l, del<%:m 1", and substitutetherewith--claim 13--.
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`, line 1, delete “claim 1", and substitute therewith --claim 13--
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`Line 4, delete “a molybdenum”, and substitute therewith --, molybdenum
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`’
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`Claim 1
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`, line 3, delete “and molybdenum” , and substitute therewith --, molybdenum
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`and tungsten-- /
`andtungsten-—.
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`/
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`Add new claims l5~l7.
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`\2
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`A semiconductor structure according to claima1v3,’wherein said conducting
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`l
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`plug comprises an outer glue layer and a plug material therein.
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`H
`.16
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`l
`A semiconductor structure according to claim 1'3,’wherein said polysilicon gate
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`and said diffusion region being exposed in said via in the absence of said conducting plug.
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`*1
`\5
`A method according to claim 14: wherein said gate is a polysilicon gate.
`Pf
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`R E M A R K S
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`Claims 1 and 7 have been canceled. New claims l3~l7 have been added. Thus claims
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`2~6 and 8~17 are now pending. No new matter is added by the present amendment.
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`Support for the amendment to claims 6 and 12 can be found in the specification at p.
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`10, lines 10-11; p. 11, step 24; p. 12, step 17 and p. 13, step 24.
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`Support for claim 15 can be found in the specification at p. 11, steps 23~24; p. 13,
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`steps 23~24; p. 12, steps 16~17 and Figure 3B.
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`Rejection Under 35 USC §102(a)
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`The rejection of Claims 1~12 under 35 USC §102(a) as being anticipated by Kinoshita,
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`US. Patent No. 5,453,640, is respectfully traversed.
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`Kinoshita teaches a Contact hole formed in an insulating layer over a diffiision region,
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`and a conducting tungsten plug fills the contact hole. Kinoshita further teaches a block of static
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`memory cells using CMOS transistors, wherein metal interconnections, e.g.,ground lines for the
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`CMOS transistors, are simplified by using buried layers in the substrate. Buried tungsten contacts
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`in the memory cell form connections of the n-MOS and p—MOS transistor diffusion layers to
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`underlying layers of opposite conductivities. Kinoshita further uses supply voltage or ground
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`potential to each buried layer from the substrate surface by using additional buried contacts which
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`are made at convenient locations outside the memory block, As shown in Kinoshita’s Figure 5, the
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`diffusion region 46 and the polysilicon gate electrode 26 are adjacent but not in contact with each
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`other. A tungsten contact plug fills the contact hole 32 for making electrical contact only with the
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`diffusion region 46 (and not with the gate electrode 26).
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`The applicant’s claims 1~l2 are not anticipated by Kinoshita ‘640. To anticipate a
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`claim of a patent, a single source must contain all its essential elements. See, e. g., Tights, Inc. v.
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`Acme—McCrar)g Corg, 191 USPQ 305 (4th Cir. 1976),
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`Kinoshita fails to teach a plugthat contacts and provides electrical communication
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`between a polysilicon gate and a diflhsion region in a via opening exposing the gate and the diffusion
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`region in the absence of the plug.
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`Instead insulating layer 38 of silicon oxide or silicon nitride
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`prevents polysilicon gate electrode 26 from being exposable or exposed in contact hole 32 (see Figure
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`5 of Kinoshita).
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`Therefore, Kinoshita does not anticipate the present invention. Withdrawal of the
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`rejections of claims 1~l2 under 35 USC §l02(a) is respectfiilly requested.
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`Rejection under 35 USC §102(b)
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`The rejection of Claims 1~12 under 35 USC §lO2(b) as being anticipated by
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`Nishigoori, US. Patent No..5,245,210, is respectfully traversed.
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`Nishigoori 210 discloses a MOS type semiconductor device which has a contact hole
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`opened in a layer of insulating material. This first contact hole has a length similar to the width of the
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`corresponding source/drain dilfusion regions. A refractory metal is then deposited to fill the contact
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`hole. As shown in Figure 2b ofNishigoori, polysilicon gate electrode 4 is insulated from the diflilsion
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`regions 5 and 7 by gate oxide 4, side-wall oxide 7 and insulating layer 8. A contact plug is formed
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`in contact hole 12 for making electrical contact to the diffusion region 7. The contact plug in contact
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`hole 12 is insulated from the gate electrode 4 by the insulating layer 8 and the side-wall oxide 6.
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`Therefore Nishigoori does not disclose or suggest a plug contacting and providing
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`electrical communication between a polysilicon gate electrode and a difiusion region. Consequently,
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`Nishigoori does not anticipate the present invention.
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`Therefore, withdrawal of the rejection of claims 1~l2 under 35 USC §lO2(b) in view
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`of Nishigoori ‘2l0 is respectfully requested.
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`Based on the foregoing, it is respectfully submitted that all of the pending claims in
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`the present application are in condition for allowance and such action at an early date is respectfully
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`solicited.
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`The Examiner is respectfiilly invited to call the applicant’s representative at his Detroit,
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`Michigan Ofiice at (313) 962-4790 should it be desirable to do so to expedite allowance of the
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`present application.
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`Respectfully submitted,
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`BARNES, KISSEL
`WHITT
`O
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`‘
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`RAISCH, CHOATE,
`& HULBERT, P.C.
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`By:
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`___,‘
`
`dy W. Tung
`Registration No. 31, 311
`Telephone: (313) 962-4790
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`RWT:bp