2:)D_D l)
`
`man Review
`
`THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`Application of:
`
`Ting P. Yen
`
`Serial No.:
`
`08/561,951
`
`Title:
`
`Filed:
`
`METAL PLUG LOCAL INTERCONNECT
`
`November 22, 1995
`
`
`
`Attorney Docket No.:
`
`O325.00004
`
`Examiner:
`
`Art Unit:
`
`V. Wallace
`
`2503
`
`In Response To:
`
`Office Action mailed November 7, 1996
`
`AMENDMENT PQBSUANT TQ §7 §,F.R. § 1,11§
`
`Box AF
`Assistant Commissioner for Patents
`Washington, D.C. 20231
`
`Sir:
`
`In response to the Office Action mailed November 7, 1996,
`
`please consider the following amendment and remarks regarding the
`
`above—captioned patent application to place the patent application
`
`in condition for allowance.
`
`5 3
`
`2 E
`
`3
`E9383
`
`IN HE
`
`LAIMS
`
`Please amend the claims as follows:
`
`.
`gfi
`E
`(AMENDED) A semiconductor structure comprising:%
`13.
`a silicon substrate having a top surface,
`EE
`
`1
`
`
`
`

`
`a diffusion region formed in said substrate adjacent to
`
`said top surface,
`
`a polysilicon gate formed on the top surface of said
`
`substrate juxtaposed to but not contacting said diffusion region,
`
`a sidewall spacer adjacent to said polysilieep gate and
`
`d
`
`ove
`
`ai diffusi n
`
`an
`
`insulator
`
`layer
`
`substantially
`
`covering
`
`said
`
`polysilicon gate and said diffusion region, and
`
`a conducting plug at
`
`least partially filling a via in
`
`said insulation layer that exposes said sidewall spage;
`
`in the
`
`absepce pf said epndpptipg pigg,
`
`said conducting plug providing-
`
`direct electrical communication between said polysilicon gate and
`
`said diffusion region.
`
`14.
`
`(AMENDED) A method of forming a local interconnect
`
`in a semiconductor structure, comprising the step of:
`
`depositing an electrically conducting material in a via
`
`exposing at least a portion of a gate.
`
`a sidewall spacer adjaeent
`
`to said gate and a portion of a diffusion region such that said
`
`electrically conducting material contacts and provides electrical
`
`communication between said gate and said diffusion region, said
`
`semiconductor structure comprising said diffusion region in a
`
`silicon substrate, said gate being on said substrate juxtaposed to
`
`

`
`but not contacting said diffusion region,
`
`said sidewall spacer
`
`ein
`
`i
`
`osed ab ve
`
`id diffusion r
`
`io , said via being in an
`
`insulating material on said gate.
`
`S PPO T F R
`
`TS
`
`Support for the above amendments can be found in FIG. 3B
`
`as originally filed along with United States Patents 4,566,175;
`
`4,878,100; 4,962,060; 5,202,279; 5,286,674; and 5,521,118 and Wolf,
`
`Silicon Processing for the VLSI Era, Volume 2, pp. 144-145, 212-
`
`214, and 354-355 filed with the accompanying Information Disclosure
`
`Statement.
`
`R E M A R K S
`
`Rejection Under 35 U.S.C. § 1D2{e)
`
`The rejection of claims 2-6, 8-14 and 16-17 under 35
`
`U.S.C.
`
`§
`
`lO2(e)
`
`as being anticipated by United States Patent
`
`5,541,434 (hereinafter “Nicholls et a1.”) is respectfully traversed
`
`and should be withdrawn.
`
`Nicholls et al. discloses a contact
`
`for electrically
`
`connecting adjacent portions within a
`
`semiconductor device.
`
`Nicholls et al. discloses a silicon substrate 52,
`
`a diffusion
`
`region 70,
`
`a polysilicon gate 56 which does not physically touch
`
`the diffusion region 70,
`
`a dielectric region 74, a contact via 76
`
`and an electrically conducting plug 80. Nicholls et al. does not,
`
`however, disclose a sidewall spacer adjacent
`
`to the polysilicon
`
`

`
`gate 56 and disposed above the diffusion region 70 in the via
`
`containing the electrically conducting plug 80.
`
`In fact, Nicholls
`
`et al. discusses etching the sidewall
`
`spacer out of
`
`the‘ via
`
`containing the conducting plug,
`
`thus appearing to lead one of
`
`ordinary skill in the art away retaining a side wall spacer in this
`
`position.
`
`(Column 5,
`
`lines 15-20.)
`
`Claims 13 and 14, as amended, recite a sidewall spacer
`
`adjacent to the polysilicon gate and disposed above the diffusion
`
`region in the via containing the conducting plug. Therefore,
`
`the
`
`present claims 13 and 14 overcome the rejection under 35 U.S.C.
`
`§
`
`102(e).
`
`REJECTIONS
`
`E
`
`.
`
`C. 103
`
`The rejection of Claim 15 under 35 U.S.C.
`
`§ l03(a) as
`
`being unpatentable over Nicholls et al.
`
`in view of United States
`
`Patent
`
`5,313,089
`
`(hereinafter
`
`“Jones,
`
`Jr.”)
`
`is
`
`respectfully
`
`traversed.
`
`Jones, Jr. discloses a semiconductive device including a
`
`conductive plug region 32. Glue layers are generically identified
`
`as being used in conductive plug technology.
`
`Jones
`
`is
`
`silent with regard to a
`
`conducting plug
`
`providing electrical communication between a polysilicon gate and
`
`a diffusion region.
`
`Therefore,
`
`Jones,
`
`Jr.
`
`fails to cure the
`
`

`
`deficiencies of Nicholls et al. with regard to the presently
`
`claimed invention.
`
`Furthermore, one ordinary skill
`
`in the art
`
`would not be motivated to include a sidewall spacer adjacent to a
`
`polysilicon gate and disposed above a different region in a via
`
`containing or to subsequently contain a conducting plug. One might
`
`reasonably expect a sidewall spacer to reduce the available surface
`
`area for direct ohmic contact between the polysilicon gate and the
`
`diffusion region thus
`
`reducing the
`
`likelihood for
`
`success,
`
`particularly when the sidewall spacer comprises an oxide, a well-
`
`known electrical
`
`insulator
`
`(see, e.g., Wolf).
`
`Therefore,
`
`the
`
`rejection under 35 U.S.C. § lO3(a) should be withdrawn.
`
`

`
`Accordingly,
`
`the present application is in condition for
`
`allowance.
`
`Early and favorable action by the Examiner
`
`is
`
`respectfully solicited.
`
`The Examiner
`
`is
`
`respectfully invited to call
`
`the
`
`Applicant's
`
`representative should it be deemed beneficial
`
`to
`
`further advance prosecution of the application.
`
`If any additional fees are due, please charge our Deposit
`
`Account No. 02-2712.
`
`Respectfully submitted,
`
`BLISS MCGLYNN, P.C.
`
`
`
`
` David J. Simo lli
`Registration No. 36,680
`2075 West Big Beaver Road, Suite 600
`Troy, MI
`48084-3443
`(248) 649-6090
`
`Dated:
`
`Docket No.: 0325.00004
`
`

`
`
`
`SERIAL NUMBER:
`
`08/561,951
`
`FILED:
`FOR:
`ART UNIT:
`
`November 22, 1995
`METAL PLUG LOCAL INTERCONNECT
`2503
`
`EXAMINER:
`
`V. Wallace
`
`ASSISTANT COMMISSIONER FOR PATENTS
`Washington, D.C. 20231
`Sir:
`
`7’/61
`
`Attorney Docket:
`
`(}325.00004
`
`TRANSMTITAL
`RESPONSE
`EXTENSION OF TIME REQUEST
`
`AND
`
`(IF REQUIRED)
`
`.
`_
`initial Review
`
`I
`
`
`
`‘L. ,
`
`Enclosed please find an amendment, Information Disclosure Statement with cited references and a postcard along‘\'Iv‘i'th-—'1.t’he fee
`calculation below:
`FEE CALCULATI N FOR ENCLOSED AND EXTENSION RE I UEST I A
`
`Claims Remaining
`
`Highest No.
`Previous
`
`Extra
`
`Rate
`
`Additional
`Fee
`
`0
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`xsmo
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`$0-00
`
`Towlclaims
`Independent
`$ 0.00
`x $ 80.00
`0
`=
`3
`10 minus
`Claim.s
`
`11Mull‘ le im irstA cled
`00
`.
`+
`TOTAL IF NOT SMALL ENTITY $ 0 00
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`[
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`]
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`[ X ]
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`SMALL ENTITY STATUS - If applicable, divide by 2 .
`[
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`Verified statement enclosed, if not previously filed.
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`.$ 0.00
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`Applicant also requests a? month extension of time
`for response to the outstanding Office Action. The fee is .
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`O 00
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`.$ 2§Q,§2Q
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`Fee set forth in 37 C.F.R. 1.17 (p) for Information Disclosure
`under 37 C.F.R. 1.97 (c) .
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`. $ 230.91)
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`The Commissioner is hereby authorized to charge any overpayment or underpayment of the above fee associated with this
`Communication to Deposit Account No. 02-2712. A duplicate copy of this sheet is attached.
`'
`
`BLISS MCGLYNN, P.C.
`
`2075 W. Big Beaver, Suite 600
`Troy, MI 48084-3443
`(248) 649-6090
`
`By:
`
`ss
`1 seph G. B
`Reg No.: _fi_3§;_
`
`I hereby certify that this letter, the response or amendment attached hereto are being deposited with the United States Postal
`Service as first class mail in an envelope addressed to Commissioner of Patents and Trademarks, Washington, D.C. 20231, on
`June
`'1 97 .
`_
`‘
`
`By:
`
`Theres a A. Wilmoth