Ting P. Yen
`
`-
`
`Serial No.:
`
`08/900,047
`
`/ /
`
`Title:
`
`Filed:
`
`I
`
`METAL PLUG LOCAL INTERCONNECT
`
`July 24, 1997
`
`Attorney Docket No.:
`
`0325.00l24
`
`Examiner:
`
`Art Unit:
`
`V. Wallace
`
`2503
`
`In Response To:
`
`Office Action mailed October 3, 1997
`
`RESPONSE
`
`Assistant Commissioner for Patents
`
`Washington, D.C. 20231
`
`Sir:
`
`In response to the Office Action mailed October 3, 1997,
`
`please consider the following remarks regarding the above-captioned
`
`patent application.
`
`R E M A R K S
`
`The presently claimed invention Concerns a semiconductor
`
`structure comprising a silicon substrate having a top surface, a
`
`diffusion region formed in said substrate adjacent
`
`to said top
`
`1
`
`IN'l"I~ll . 1006
`
`
`
`

`
`surface,
`
`a polysilicon gate formed on the top surface ofi
`
`the
`
`substrate juxtaposed to but not contacting said diffiusion region,
`
`a sidewall spacer adjacent to the polysilicon gate and disposed
`
`above
`
`the diffusion region,
`
`an insulator
`
`layer substantially
`
`covering the polysilicon gate and the diffusion region, and a
`
`conducting plug at least partially filling a via in said insulation
`
`layer that exposes
`
`the sidewall spacer
`
`in the absence of
`
`the
`
`conducting plug.
`
`The conducting plug provides direct electrical
`
`communication between the polysilicon gate and the diffusion
`
`region.
`
`t
`
`n
`
`3 U.S C
`
`The rejection of claims 3-6, 9-14 and 16-17 under 35
`
`U.S.C.
`
`§ 102[e) as being anticipated by Sugiyama U.S. Patent No.
`
`5,600,170 is respectfully traversed.
`
`As evidenced by the attached Declaration (the executed
`
`version of which will be filed at
`
`the earliest opportunity)
`
`the
`
`present
`
`invention was conceived prior
`
`to the filing date of
`
`Sugiyama. Therefore,
`
`this ground of rejection is unsustainable,
`
`and should be withdrawn.
`
`

`
`EJECTI N‘
`
`R
`
`5
`
`The rejection of Claims 2,
`
`8 and 15 under 35 U.S.C.
`
`§
`
`103(a} as being unpatentable over Sugiyama et al.
`
`in View of Jones,
`
`Jr.
`
`(U.S. Patent No. 5,313,089) has been obviated in view of the
`
`attached Declaration under 37 C.P.R. 1.131 and should be withdrawn.
`
`Jones alone does not render the presently pending claims
`
`2,
`
`8 and 15 obvious.
`
`Jones discloses a capacitor and memory cell
`
`formed therefrom. Nothing disclosed by Jones describes or suggests
`
`the via recited in the present claims. Therefore this ground of
`
`rejection should be withdrawn.
`
`Accordingly,
`
`the present application is in condition for
`
`allowance.
`
`Early and
`
`favorable action by the Examiner
`
`is
`
`respectfully solicited.
`
`

`
`H
`
`;
`
`m:n1vId
`
`11 6x98
`
`.
`u
`4.08pm,
`
`.3. ELISE M:m_YNN_ ,,_c_: P.n. 10
`
`San’: by: was ucavruu, sac.
`
`2-ea use 3299;
`
`01 2:35:93
`
`_.55P!l;JetlEx ms Page one
`
`The Examiner
`
`is respectfully invited to call
`
`the
`
`Applicant’:
`
`representative should it be deemed boneticial
`
`to
`
`turther advance prosecution of the application.
`
`It any nddibioxnl
`
`flees arc due. please change our Depcsit.
`
`Account No. 02-2712 .
`
`Reapactful ly aulamfl. 1:1: ed .
`
`
`
`BLISS MCGLYNN, P.C.
`
`flfnol’-6-J\D—
`
`o. 34‘, 600
`
`Esf.
`
`
`
`(2485 649-6090
`
`Dated:
`
`..aIan:.u£L.§....H.3£._..__._
`
`Docket £10.: D335_.00l2¢
`
`Ihmayamflymfigfiiumnmemsponuwmmhnauwmheahumnunbehidflwihdmfimsuuiwd iuws
`Postal scninufiu-m:lustmaiJhuanenv:iop:amra:sedmAuiItanI CommissionerforPaIe_un,Wanmgmn, D.C.
`wB1.on -
`
`
`
`

`
`H9033-V913!
`
`‘ll BIQH 4:06PM;
`
`-3- BLIS-3 MCGLYNN, F'.C.;
`
`Fags 11
`
`Sent "ray: sues ucenmn, v.o.
`
`249 349 5299;
`
`01/osma
`
`5Pu;J3¢-fix ma Page mu
`6'/§‘fl 2:4;-3
`
`l)335.lJD12 I m RE Appummn o1=:
`
`samm. NUMBER:
`
`Ting P. vai
`03900.04?
`
`Ju1y24. 199':
`FILED:
`ma-m. PLUG LOCAL mmncounam '
`ma:
`2503
`an-r unrr;
`Wallace. v.
`Examnan:
`Asslswmr COMMISSIONER FOR PATENTS
`wnningwn, D.C. 2023:
`Sir:
`
`attorney Docket:
`
`xssronss mmsurrnu mu
`EXTENSION OF TIME REQUI2 :1‘
`
`as nnqunm
`
`Rgffijgf-MERE}
`; JAM E 5 __FW._-' la
`GR
`,
`{.3Ur'~J‘
`“ "dag
`
`E.1-wlmod please find In amandnmcnt, Mfninvlc Undet 3'3 C.F.R. 1.131 and a postcard aloog with the fee calculnicn below:
`..
`.
`.
`:
`.- 1;‘:
`E!-'
`
`
`
`TOTAL IF NOT SMALL ENTITY S Um
`
`[
`1
`
`[
`
`1
`
`}
`]
`
`]
`
`1
`
`SMALL BN'l'1TY STATUS -. If Ipplicablo. divi:1c,b;r 2 .
`Vmifiod statement enclosed, if not previously filul.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`. .
`
`Applicant also re.-qucsts e __ rrunnth cmonsion of time
`for raaponaa to {he outstanding Ofiice Action. The toe in .
`
`.
`
`.
`
`.
`
`.
`
`.
`
`Feesez fm-:b1.n3?C.F.R. 1.11 (p) for Elzforxnltionliiscioaura
`1.|nde'r'37C.F.R.l.r!'(¢).
`.
`.
`.
`. . ,
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`. _ .
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`. .£L00____._
`
`. s_.u.nn.____
`
`TOTALFEE .
`
`.
`
`.
`
`_
`
`_
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`The Cg;-an-dggjangr L] um” aumorjggd to charge my owrpayrncnl or u.nd¢rpa)rrncnt of the about fee uaaocinu cl with this
`Cn Io De-posit Amount No. 02-2712. A duplicllc copy of this sheet is mashed.
`
`2075 w. Big Beave1',Suile6OO
`Tm. MI 43034-3“:
`(143) 649-6090
`
`-
`
`By
`
`Buss McGl.YNN. p.c.
`
`hm Mlgu-.1 Maw
`Res No: 12.133’...
`
`Afld/N.-D_ 5&7’ 9k-Du; esz.
`‘W’ 3‘; 50°
`
`I haxeby certify Lhm Lhls loner. tho response or amandrrmus attached! hereto are Ming dtpfliilflfl W111! 91¢ Uflilfli 5'-SW WW1
`Service as firs: elm mail in an mvelopc addressed to Assistant Commission: for Patents. Washington. D.C- 2023] . on
` -
`
`By:
`
`ulie A. fiarber
`
`

`
`Ge
`
`'3
`
`-
`
`_
`
`~2 as
`
`I
`I
`
`
`)
`2503
`Art Unit:
`i
`Wallace, V.
`Examiner:
`i
`App1icant(s): Ting P. Yen
`;
`Serial No;
`08f900,047
`;
`Filing Date:
`July 24, 1997
`For:
`METAL PLUG LOCAL INTERCONNECT;
`
`in
`
`TRANSMITTAL
`
`RECEWED
`FEB 0 6 I998
`GROUP 250
`
`Assistant Commissioner for Patents
`
`Washington, D.C. 20231
`
`Sir:
`
`Enclosed is an executed Declaration of Jeff Watt Under 37
`
`C.F.R. 1.131, Exhibit A, and Jeff Watt's curriculum vitae.
`
`Respectfully submitted,
`
`BLISS MCGLYNN, P.C.
`
`
`
`Christoph r P. Maiorana
`Registration No. P-42,829
`2075 West Big Beaver Road, Suite 600
`Troy, MI
`48084-3443
`(248) 649-6090
`
`Dated:
`
`Jangggy 23, 1325
`
`Docket No.: O325.00124
`
`I hereby certify that Lhis correspondence is being deposited with theUnired States Postal Service as first class mail
`in an envelope addressed to Assistant Commissioner for Patents. Washington. D.C. 20231. n 8.
`
`
`
`Julie A. Barber
`
`

`
`$5/Cr
`Vgufifir.
`I)
`T\/5~’rQB/
`
`Declaration of Jeff Watt
`Under 37 C.F.R. 1.131
`'
`
`) ) ) J ) )
`
`}
`
`} ) )
`
`For:
`
`METAL PLUG LOCAL INTERCONNECT
`
`)
`Tu"__#
`
`Assistant Commissioner for Patents
`
`Washington, D.C. 20231
`
`Dear Sir:
`
`1, Jeffrey Watt, hereby declare and state:
`
`1.
`
`2.
`
`My curriculum vitae is attached hereto as Appendix 1.
`
`I have been employed by Cypress Semiconductor Corporation since flz where
`
`my current job title is fjEHBEL QC "TECH NIC4 -C.
`
`ST/FFF,
`
`3.
`
`I have read the above-identified patent application and the subsequent amendment
`
`to the claims thereto filed on June 9, 1997. I understand the contents of said patent application and
`
`said arnendment.
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`2503
`
`Art Unit:
`
`Exarniner:
`
`Wallace, V.
`
`Applicant(s): Ting P. Yen
`
`Serial No.:
`
`0s;9oo,o47
`
`Filing Date:
`
`July 24, 1997
`
`

`
`4.
`
`I understand that the invention claimed in the above-identified patent application
`
`CCIDCBITISI
`
`(A)
`
`a semiconductor structure comprising:
`
`a silicon substrate having a top surface,
`
`a diffusion region fonned in the substrate adjacent to the top surface,
`
`a polysilicon gate formed on the top surface of the substrate juxtaposed to, but not
`
`contacting, the diffitsion region,
`
`a sidewall spacer adj accnt to the polysilicon gate and disposed above the diffusion
`
`region,
`
`and
`
`an insulator layer substantially covering the polysilioon gate and the diffusion region,
`
`a conducting plug at least partially filling 3 via in the insulation layer that exposes the
`
`sidewall spacer in the absence of the conducting plug, the conducting plug providing direct electrical
`
`communication between the polysilicon gate and the diffiision region; and
`
`(B)
`
`a method of forming a local interconnect in a semiconductor structure,
`
`comprising the step of:
`
`depositing an electrically conducting material in a via exposing at least a portion of
`
`a gate, a sidewall spacer adjacent to the gate and a portion of a diffusion region such that the
`
`electrically conducting material contacts and provides electrical communication between the gate
`
`and the diffusion region, the semiconductor structure comprising the diffusion region in a silicon
`
`substrate, the gate being on the substrate juxtaposed to but not contacting the diffusion region, the
`
`

`
`sidewall spacer being disposed above the diffusion region, the via being in an insulating material on
`
`the gate.
`
`5.
`
`Prior to June 7, 1995, Iwitnessed, read and understood an Invention Disclosure Form
`
`(copy attached hereto as Exhibit A) describing the subject matter claimed in the above—identified
`
`patent application.
`
`6.
`
`In my opinion, the Invention Disclosure Form that I witnessed describes the claimed
`
`invention and conveys infonnation suflicient to enable one skilled in the relevant art to make and
`
`use the claimed invention.
`
`7.
`
`I declare that all statements made herein of my own knowledge are true and that all
`
`statements made on information and belief are believed to be true; and further that these statements
`
`were made with the lcnowledge that willfitl false statements and the like so made are punishable by
`
`fine or imprisonment, or both, under Section 100] of‘ Title 18 of the United States Code and that
`
`such willful false statements may jeopardize the validity of this application orarry patent issuing
`
`thereon.
`
`
`
`Date
`
`

`
`j Tinsren
`
`EKH I B (T H-
`_
`_
`Metal Plug Local Shunt Patent Disclosure
`
`Invention Objective:
`The purpose of this invention is to provide a cheaper method of strapping transistor gates to both N+ :9;
`P+ diffusion by using metal plugs which are, in general. already designed into sub—rnetal contacts. By
`employing the contact plugs for strapping purpose no additional process steps are necessary.
`
`Current Method:
`
`In order to strap from gate poly to both N+ and 13+ diffusion using traditional buried contacts requires
`a complex set of process additions. The reason for this is that gate poly requires to be doped both 13+
`and N+, depending on the diffusion doping the poly is strapping to. Further more to minimize inter-
`diiiiision between 11+ and P+ doping in poly, extra process steps are required to lower diffiisivity. This
`is even more diflicult as design rules are scaled to deep sub-micron range. Other disadvantages are:
`- to avoid dopant penetration into channel region, P+ doped poly needs to be implanted with very low
`energy 1311 instead of EF2 (to avoid F+ enhanced dopant difiusion]; poor manufacturahility.
`- For salicidod poly: WSix case: this approach does not allow in-situ deposited doped polyfWS'1x
`TiSix case:
`this apprach makes it dimcnll to match P+ doped and N+ doped polycide
`sheet resistance, plus where N+ and P+ poly is suppose to be oonnected
`as we have learned : there will be a BREAK in the polycicle.
`Other available method of strapping gate poly to both N+ and 1’+ diffusion:
`- another obvious method used today is to use a metallic local interconnect strap to shunt from the
`gate to diffusion. However, this requires: 1) insulating layer between LI and gate 2) open via in insulator
`3) deposit LI layer 4] pattern LI layer. In addition from a topological point of view. this requires
`a. lot mdre layout area than a buried contact at the intersection of gate to difihsion.
`
`New Method:
`
`(Assun1ing— sub-metal plugged contacts by design)
`By placing a metallic plugged contact where poly is required to shunt to di.fi‘usion. contacts to both P+
`and N+ difiusion can be achieved independent of poly doping Topologically, this will require no more
`layout area than the traditional buried contact. This method has potential process step savings of 8-11
`steps over Trad. BC and 6-8 steps over snapping LI.
`
`
`Top View
`
`Traditional BC
`
`Met. Plug BC
`
`LI Strap
`
`
`
`

`
`
`
`
`
` lllllllllllllllllhlllll
`M|||Il|||l||l|
`
`
`
`
`illlillllllifilfl
`
`X-Section
`Tradifinnal BC
`
`
`Process Step Count:
`
`thin poly
`-1
`BC1 task
`-1
`BC1 etch
`
`[BC imp] msk)
`{BC P+ impl)
`(BC N+ impl}
`Amcrp Si dep
`N+ Impl
`P+ poly msk
`13+ poly impl
`Si Recryst 3h.r+
`Wsix dep
`Nit;'BPSG
`
`-1
`-1
`-1
`-1
`-1
`-1
`-1
`-1
`
`-
`
`'
`
`[nsitu dope Pol}-fwsix
`NMBPSG
`
`Contact mskfetch
`
`Contact mskfctch
`
`-Insitu Polyfwsix
`NRIBPSG (ILD1}
`Licon mask
`Licon etch
`
`Glue/‘LI dep
`(W-plug)
`(WEB)
`Li mask
`Li etch
`
`ILD2 dep
`Contact mskfetch
`
`1
`1
`
`1
`1
`1
`1
`1
`
`1
`
`Glue2 dcp
`Glue dep
`Gin: dep
`W-depz
`W-plug
`W-plug
`WEB
`WEB
`WEB2
`
`Metall
`Metal]
`Metal]
`
`Summary
`Current Technology
`
`‘.1 Technology
`
`|
`Plug BC
`5 Step Delta. Estim from"Cun-em”
`mgr
`u
`Low=
`I
`Step Delta Estim £rum'LI Tcchn”
`Hi3h=
`I
`Low=
`'
`
`
`
`11
`
`

`
`Jeffrey T. Watt
`
`Cypress Semiconductor
`3901 North First Street
`San Jose, CA 95134
`(408) 943-2916
`
`SUMMARY:
`
`Silicon process and device expert with over 3 years of industrial experience in the design. develop-
`ment. characterization, modeling and reliability of MOS transistors in advanced CMOS processes.
`
`EXPERIENCE:
`
`1997-Present: Member of Technical Staff, Advanced Development
`Cypress Semiconductor Corp., San Jose, CA
`Responsible for development of transistors for 0.18 um generation process technology.
`1993-1997: Device Engineering Manager
`Cypress Semiconductor Corp., San Jose, CA
`Leader of group responsible for development of HSPICE models for transistors and interconnects.
`development of ESD protection structures and design rules. development of design rules to meet
`latchup specifications and process development for MOS transistor modules on platform CMOS
`SRAM technologies. Specific accomplishments include:
`Developed transistor processes for Cypress 0.5. 0.4 and 0.35 um CMOS SRAM technologies.
`Established methodology and delivcrables for transistor development.
`Established methodology for incremental product shrinks for reduced die cost.
`Provided support to product Lines on device issues.
`Determined root cause for E08 failures in burn-in and qual stresses. Developed process moni-
`tor and design rules for reduce EOS fallout with no impact on process cost.
`Developed novel BSD protection devices to meet HBM and CDM requirements on salicided
`and non-salicided technologies.
`1989-1993: Senior Device Engineer,
`Cypress Semiconductor, San Jose, CA
`Responsible for transistor development. electrical design rule generation, electrical test su-ucture
`design. E.SDllatcl1-up design rules. Specific accomplishments include:
`Developed high-voltage transistor for 0.8 um PROM technology
`Developed transistor process for 0.65 um CMOS SRAM technology.
`Developed high-performance 0.6 um transistors for SPARC microprocessor.
`Supervised two technicians operating the ESDflatcl1—up qualification testing and failure analy-
`sis lab.
`
`Developed BSD protection devices for all 0.8 and 0.65 um technologies including BiCMOS,
`SRAM, Logic. PROM and PLD.
`Developed design rules to protect against CDM ESD. thereby reducing baclcend yield loss for
`ESD to ~0%.
`
`12
`
`

`
`EDUCATION
`
`1989: Ph.D., Electrical Engineering, Stanford University, Stanford, CA
`NSERC Postgraduate Scholarship 1984-1987
`‘Thesis: “Modeling the Performance of Liquid-Nitrogen Cooled CMOS"
`Adviser: James D. Plummet
`
`1984: M.S., Electrical Engineering, Stanford University, Stanford, CA
`Imperial Oil Graduate Research Fellowship 1983-1986
`Sir James Lougheed Award of Distinction 1983-1985
`
`1983: 13.5., Electrical Engineering, Queen’s University, Kingston, Canada
`B.S. in Elecnical Engineering
`Governor Genera1’s Gold Medal 1983
`
`PUBLICATIONS:
`
`F‘. N. Trofimenlcoff, R. H. Johnson, J. W. Haslett and J. '1'. Watt. “Image Theory Analysis of Fields
`Due to a Step in the Current on a Long Line on the Surface of the Earth." IEEE Trans. Geosci.
`Remote Sensing, vol. GE-22, March 1984.
`J. T, Watt, B. J. Fishbein and J. D. Plummet, "A Low-Temperature NMOS Technology with
`Cesium-Implanted Load Devices.” IEEE Trans. Electron Devices. vol. ED-34. January 1987.
`A. K. Henning, N. N. Chan. J. T. Watt and J. D. -Plummet, “Substrate Current at Cryogenic Tem-
`peratures: Measurements and a 'Dwo-Dimensional Model for CMOS Technology,” IEEE Traits.
`Electron Devices. vol. ED-34, January 1987.
`B. J. Fishbein, J. '1". Watt and J. D. Plummet, "Time Resolved Annealing of Interface Traps in Pol-
`ysilicon Gate MOS Capacitors.” I. Eleclrochem. Soc., 134(3), March 1987.
`J. T. Watt and J. D. Plummet, “Efficient Numerical Simulation of the High-Frequency MOS
`Capacitance," [BEE Trans. Electron Devices. Vol. ED-34. October 1987.
`J. 'T'. Watt. 13. J. Fishhein and J. D. Plummet, “Characterization of Surface Mobility in M05 Struc-
`tures Containing Interfacial Cesium lons," IEEE ‘Dans. Electron Devices, vol. 36, January 1989.
`J. 'T‘. Watt and J. D. Plummet. “The Effect of Interconnection Resistance on the Performance of
`Liquid-Nitrogen Cooled CMOS Circuits." IEEE Trans. Electron Devices. vol. 36. August 1989.
`J. T. Watt and J. D. Plummet. “Dispersion of MOS Capacitance-Voltage Characteristics Resulting
`from the Random Channel Dopant Ion Distribution," IEEB'I‘rans. Electron Devices. vol. 41,
`November 1994.
`
`CONFERENCE PRESENTATIONS:
`
`“Universal Mobility-Field Curves for Electrons and Holes in M05 Inversion Layers." 1987 Sym-
`posium on VLSI Technology, Karuizawa, Japan.
`“Effect of Interconnection Delay on Liquid-Nitrogen Temperature CMOS Circuit Performance."
`1987 International Electron Devices Meeting, Washington, DC.
`"Surface Potential_Fluctuations in MOS Devices Induced by the Random Distribution of Channel
`Dopant Ions," 1988 Device Research Conference, Boulder, CO.
`"A Hot-Carrier Triggered SCR for Smart Power Bus ESD Protection," 1995 international Electron
`Devices Meeting. Washington, DC.
`
`13