United States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,475,240
`
`Sakamoto
`
`[45] Date of Patent:
`
`Dec. 12, 1995
`
`lllllllllllllllllllllll||||||||||||||||||||llllllllllllllllllllllllllll
`USOO547524OA
`
`0204171
`0186051
`0006855
`0040133
`0132317
`0015620
`0073666
`0271663
`
`Japan ..................................... .. 257/67
`12/1982
`Japan ..................................... .. 257/67
`9/1985
`Japan.
`1/1986
`Japan.
`9/1986
`Japan.
`6/1987
`Japan.
`1/1990
`Japan ..................................... 257/903
`3/1990
`Japan.
`11/1990
`OTHER PUBLICATIONS
`
`“A Memory Cell with Polysilicon Thin Film Transistor
`(TFT) for a 4Mbit SRAM”, Tsutsurni et al., Institute of
`Electronics and Communication Engineers of Japan Tech-
`nical Report, vol. 90, No. 48, pp. 7-13.
`“A New CMOS SRAM Cell with Fully Planarizing Tech-
`nology”, Narita et al., 1987 Symposium on VLSI Technol-
`ogy Digest of Technical Papers, pp. 103-104.
`“Trench Self—A1igned EPROM Technology”, Sekiya et al.,
`1986 Symposium on VLSI Technology Digest of Techical
`Papers, pp. 87-88.
`“A High—Perforrnance SRAM Memory Cell with LDD—TFT
`Loads”, Tsutsumi et al., 1991 Symposium on VLSI Tech-
`nology Digest of Technical Papers, pp. 23-24.
`
`Primary Examiner—William Mintel
`Assistant Examiner-—Peter Toby Brown
`Attorney, Agent, or Firm—Lowe, Price, LeBlanc & Becker
`
`[57]
`
`ABSTRACT
`
`A silicon layer in a lower layer and an interconnection layer
`arranged in an upper layer are electrically connected through
`an opening for contact. A silicon plug layer having the same
`conductivity type as that of the silicon layer is embedded in
`the opening. The silicon plug layer is embedded in the
`opening by an etch back method after deposited using a
`CVD method. The interconnection layer in the upper layer
`has conductivity type diiferent from that of the silicon plug
`layer. A refractory metal silicide layer is formed between the
`upper interconnection layer and the silicon plug layer.
`
`The refractory metal silicide layer prevents pn junction from
`being formed between the upper interconnection layer and
`the silicon plug layer.
`
`9 Claims, 23 Drawing Sheets
`
`[54] CONTACT STRUCTURE OF‘ AN
`INTERCONNECTION LAYER FOR A
`SEMICONDUCTOR DEVICE AND A
`MULTILAYER INTERCONNECTION SRAM
`
`[75]
`
`Inventor:
`
`Osamu Sakamoto, Hyogo, Japan
`
`[73]
`
`Assignee:
`
`Mitsubishi Denki Kabushiki Kaisha,
`Tokyo, Japan
`
`[21]
`
`[22]
`
`Appl. No.:
`Filed:
`
`293,771
`
`Aug. 19, 1994
`
`Related U.S. Application Data
`
`[63]
`
`Continuation of Ser. No. 845,980, Mar. 4, 1992, abandoned.
`
`[30]
`
`Foreign Application Priority Data
`Mar. 15, 1991
`Jan. 14, 1992
`
`[JP]
`[JP]
`
`Japan .................................... 3-050954
`
`Japan
`4-005222
`
`[51]
`
`[52] U.S. Cl.
`
`Int. Cl.5 ......................... H01L 27/11; H01L 29/786;
`H01L 29/417; H01L 29/43
`.............................. 257/67; 257/69; 257/377;
`257/384; 257/755; 257/756; 257/903
`[58] Field of Search ................................ .. 257/51, 67——69,
`257/369, 377, 754-756, 903, 904, 752,
`382-384, 385
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`.............................. 257/755
`11/1988 Ning et al.
`.
`257/303
`11/1988 Morie et a1.
`437/51
`5/1989 Wahlslrom
`257/752
`11/1989 Ishii
`.............
`257/752
`10/1990 Welch et al.
`257/401
`8/1991 Kumarnoto et al.
`257/756
`10/1991 Egawa et al.
`...... ..
`3/1993 Sivan ...................................... 257/756
`
`
`
`4,785,341
`4,786,954
`4,829,018
`4,884,121
`4,966,865
`5,041,884
`5,061,983
`5,198,683
`
`FOREIGN PATENT DOCUMENTS
`
`0163132
`0281711
`0380327
`
`4/1985 European Pat. Off. .
`1/1987 European Pat. Off. .
`1/1990 European Pat. Off. .
`
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`U.S. Patent
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`Dec. 12, 1995
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`U.S. Patent
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`Dec. 12, 1995
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`5,475,240
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`FIG. 2
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`U.S. Patent
`
`Dec. 12, 1995
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`U.S. Patent
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`FIG. 27
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`FIG_ 29
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`PRIOR ART
`
`

`
`U.S. Patent
`
`Dec. 12, 1995
`
`Sheet 23 of 23
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`5,475,240
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`1
`CONTACT STRUCTURE OF AN
`INTERCONNECTION LAYER FOR A
`SEMICONDUCTOR DEVICE AND A
`MULTILAYER INTERCONNECTION SRAM
`
`This application is a continuation of application Ser. No.
`07/845,980 filed Mar. 4, 1992, now abandoned.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to improvement of a contact
`structure of an interconnection in a region having steps in a
`semiconductor device having a multilayer interconnection
`structure.
`
`2. Description of the Background Art
`In the field of a semiconductor device, increase of inte-
`gration density and miniaturization of an element structure
`are required. In order to meet such requirements, a structure
`is conceived in which a plurality of elements are stacked
`three-dimensionally on a surface of a semiconductor sub-
`strate. Such a stacked type semiconductor device increases
`integration density of a main surface of the semiconductor
`substrate; however, it has been pointed out that several
`problems arise from the fact that an interconnection layer is
`arranged on a region having steps.
`As one example of a semiconductor device having a
`structure in which semiconductor elements are stacked on a
`substrate, a structure of an SRAM (Static Random Access
`Memory) will be described. FIGS. 26 through 28 show a
`structure of a memory cell of a CMOS type SRAM using a
`thin film transistor as a load, which is shown in “A Memory
`Cell with Polysilicon Thin Film Transistor (TI-71‘) for a 4
`Mbit SRAM”, Tsutsumi et al., Institute of Electronics and
`Communication Engineers of Japan Technical Report, Vol.
`90, No. 48, p7—pl 3. FIG. 29 is an equivalent circuit diagram
`of a memory cell of the SRAM. Referring to FIG. 29, a
`memory cell of a CMOS type SRAM has a pair of CMOS
`inverters. One CMOS inverter has an 11 channel MOS drive
`transistor 20a and a p channel MOS thin film load transistor
`21a. The other CMOS inverter has an 11 channel MOS drive
`transistor 20b and a p channel MOS thin film load transistor
`21b. The gates of transistors 20a, 21a of said one CMOS
`inverter are cross connected to a store node 25b common to
`transistors 20b, 21b of said the other CMOS inverter, and the
`gates of transistors 20b, 21b of said the other CMOS inverter
`are cross-connected to a stored node 25a common to tran-
`sistors 20a, 21a of said one CMOS inverter to constitute a
`flip-flop circuit. The sources of p channel MOS thin film
`load transistors 21a, 21b are connected to a power supply 23.
`Each of the sources of n channel MOS drive transistors 20a,
`20b is connected to ground. Store nodes 25a, 25b of the
`flip-flop circuit are connected respectively to n channel
`MOS transfer transistors 22a, 22b. The gates of n channel
`MOS transfer transistors 22a, 22b are connected to a word
`line 27. The drain regions of 11 channel MOS transfer
`transistors 22a, 22b are respectively connected to bit lines
`26a, 26b.
`An operation of writing information into a memory cell
`will be described. For example, if store node 25a is set at a
`ground potential, and store node 25b at a power supply
`potential then bit line 26a is set at a ground level, and bit line
`26b at a power supply level. N channel MOS transfer
`transistors 22a, 22b are turned on by applying a prescribed
`potential to word line 27.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`An operation of reading information from a memory cell
`will be described. Bit lines 26a, 26b are connected to a sense
`amplifier circuit. Under the condition, word line 27 is
`supplied with a prescribed potential to turn on n channel
`MOS transfer transistors 22a, 22b. As a result, potentials of
`store nodes 25a, 25b are read to bit lines 26a, 26b.
`A specific structure of a memory cell of an SRAM will be
`described with reference to FIGS. 26 through 28. FIGS. 26
`and 27 are plan structural views of a memory cell. For
`convenience, the memory cell is divided into a lower layer
`portion and an upper layer portion of a substrate to show a
`plan structure of the lower layer portion of the memory cell
`in FIG. 26 and a plan structure of the upper layer portion in
`FIG. 27. FIG. 28 is a sectional structural view taken along
`line X—-X in FIGS. 26 and 27 . Referring to FIGS. 26
`through 28, the memory cell of an SRAM comprises n
`channel MOS drive transistors 20a, 20b and n channel MOS
`transfer transistors 22a, 22b, etc. in a lower region closer to
`a surface of a silicon substrate 1. P channel MOS thin film
`load transistors 21a, 21b are arranged in an upper region
`formed on a main surface of silicon substrate 1 with an
`interlevel insulating layer 9 interposed.
`Referring mainly to FIG. 28, a p well region 2 is formed
`on a surface of silicon substrate 1. A field oxide film 4 and
`
`a p+ isolation region 3 are formed in an isolation region on
`a main surface of p well region 2. An n channel MOS drive
`transistor 20:: and an n channel MOS transfer transistor 22b
`
`each comprises n+ source/drain regions 7, 7, a gate oxide
`film 5 and gate electrode 6. Gate electrode 6 has a polycide
`structure formed of a polycrystalline silicon layer 6a and a
`metal silicide film 6b which was formed on a polycrystalline
`silicon layer 6a.
`The surface of silicon substrate 1 is covered with a thick
`interlevel insulating layer 9. The p channel thin film load
`transistor 21!; is formed on a surface of interlevel insulating
`layer 9. A thin film transistor 14 comprises a gate electrode
`8b formed on the surface of interlevel insulating layer 9, a
`gate oxide film 13 covering a surface of gate electrode 8b,
`p+ source/drain regions 12a, 12c, and a charmel region 12b.
`P* source/drain regions 12a, 12c and channel region 12b are
`formed in a thin polycrystalline silicon layer having a
`thickness of about 20 nm. Gate elecnode 8b includes impu-
`rity of p type.
`An interconnection structure of store node 25b in which
`11 channel MOS drive transistor 20a is formed in a lower
`layer, 11 charmel MOS transfer transistor 22b, and p channel
`MOS thin film load transistor 21b are formed in an upper
`layer will be described. An opening 16 is formed in inter-
`level insulating layer 9. Inside opening 16, gate electrode 6
`of n channel MOS drive transistor 20a and one of n+
`source/drain regions 7 of n channel MOS transfer transistor
`22b is exposed. An interconnection layer 8a of polycrystal-
`line silicon is formed inside opening 16 and connected
`simultaneously to gate electrode 6 of 11 channel MOS drive
`transistor 20a and n* source/drain region 7 of n channel
`MOS transfer transistor 22b. Such a contact structure is
`termed shared contact. A portion of interconnection layer 8a
`extends to the surface of interlevel insulating layer 9. A
`polycrystalline silicon layer constituting a p+ source/drain
`region 12a of p channel MOS thin film load transistor 21b
`is connected to a surface of the interconnection layer 8a.
`Interconnection layer 8a is formed of polycrystalline silicon,
`and p type impurity is included therein to provide conduc-
`tivity. At the bottom portion of opening 16, a titanium
`silicide layer 11 is formed between interconnection layer 8a
`and source/drain region 7. Titanium silicide layer 11 pre-
`vents the formation of pn junction caused by direct connec-
`
`

`
`5 ,475 ,240
`
`3
`tion of interconnection layer of p type 8a and source/drain
`region of n type 7. A structure this type is termed a direct
`contact structure in which interconnection layer 8a arranged
`on the surface of interlevel insulating layer 9 is connected to
`a lower layer, for example, an impurity region formed on the
`silicon substrate, through opening 16.
`However, when a direct contact structure is formed to
`have large differences of level such as interconnection layer
`8a used for the above mentioned memory cell of an SRAM,
`there is a problem that patterning of an interconnection layer
`is difficult. FIG. 30 is a sectional view showing a manufac-
`turing step of forming interconnection layer 8a shown in
`FIG. 27. After opening 16 is formed in interlevel insulating
`layer 9, polycrystalline silicon layer 8 is deposited on the
`whole surface using, for example, a CVD method. A resist
`is applied onto a surface of the polycrystalline silicon layer
`8. The resist is developed to have a prescribed pattern shape
`after exposure, using a photolithography method, to form a
`resist mask. A polycrystalline silicon layer 8 is etched using
`a resist mask, and interconnection layer 8a and gate elec-
`trode 8b of thin film transistor 14 are formed.
`
`Polycrystalline silicon layer 8 is formed on the surface of
`interlevel insulating layer 9 having steps as shown. There are
`large steps of the polycrystalline silicon layer in the vicinity
`of opening 16. It is extremely difiicult to form a very small
`resist mask on the surface of polycrystalline silicon layer 8
`having such large steps, using an exposure technology. A
`recent exposure device particularly tends to reduce depth of
`focus. Therefore, a resolution of the resist mask deteriorates,
`which causes a problem that a pattern of interconnection
`layer 8a formed of the polycrystalline silicon layer becomes
`indistinct. Degradation of precision of an interconnection
`pattern hinders miniaturization of interconnection and
`impairs reliability of interconnection.
`
`SUMMARY OF THE INVENTION
`
`One object of the present invention is to provide an
`interconnection structure which enhances reliability of a
`multilayer interconnection structure including a contact por-
`tion having large steps.
`Another object of the present invention is to provide an
`interconnection structure in which conductive regions of
`different conductivity types are connected to provide fine
`ohmic contact.
`'
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`Another object of the present invention is to improve
`contact property of an interconnection arranged in a region
`having steps in a memory cell of an SRAM having a thin
`film transistor as a load.
`
`Yet another object of the present invention is to improve
`patterning precision of an interconnection arranged in a
`region having steps in a memory cell of an SRAM having a
`thin film transistor as a load.
`
`Still another object of the present invention is to provide
`a method of manufacturing an interconnection having an
`interconnection structure suitable for improving patterning
`precision of an interconnection arranged in a region having
`steps.
`In one aspect of the present invention, a semiconductor
`device comprises a silicon layer and an interlevel insulating
`layer formed on a surface of the silicon layer and having a
`contact hole. A silicon plug layer is embedded within the
`contact hole. On the interlevel insulating layer, an intercon-
`nection layer of polycrystalline silicon is formed. An inter-
`mediate conductive layer is formed between the intercon-
`nection layer and the surface of the silicon layer for
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`decreasing a breakdown voltage of a pn junction portion
`therebetween.
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`The silicon plug layer is embedded within the contact
`hole, so that the interconnection layer arranged on the
`surface of the interlevel insulating layer is formed on the flat
`surface of the silicon plug layer even in a region of the
`contact hole. Consequently, patterning precision of the inter-
`connection layer is improved. In case that silicon plug layer
`and the interconnection layer have different conductivity
`types, the intermediate conductive layer of refractory metal
`or the like is interposed between the silicon plug layer and
`the interconnection layer so that, the formation of pn junc-
`tion is prevented or the breakdown voltage of the pn junction
`portion is reduced. In case that the conductivity type of the
`silicon plug layer is dilferent from that of a connecting
`portion of a silicon substrate, by interposing the intermediate
`conductive layer therebetween, the formation of pn junction
`is prevented or the breakdown voltage of the pn junction
`portion is reduced.
`In another aspect of the present invention, an SRAM
`includes a memory cell having a pair of first and second
`CMOS inverters connected so as to constitute a flip-flop
`circuit and first and second MOS transfer transistors con-
`nected respectively to node points of the flip-flop circuit.
`The first CMOS inverter comprises a first MOS drive
`transistor of a first conductivity type formed on a main
`surface of a silicon substrate, and a first thin film transistor
`of a second conductivity type formed on a surface of an
`interlevel insulating layer formed on the main surface of the
`silicon substrate. The second CMOS inverter comprises a
`second MOS drive transistor of the first conductivity type
`formed on the main surface of the silicon substrate, and a
`second thin film transistor of the second conductivity type
`formed on the surface of the interlevel insulating layer.
`Furthermore, a first MOS transfer transistor and a second
`MOS transfer transistor are formed on the main surface of
`the silicon substrate. A gate electrode of the first MOS drive
`transistor, a source/drain region of the second MOS transfer
`transistor, and a source/drain region of the second thin film
`transistor are connected to each other through a first inter-
`connection structure. A gate electrode of the second MOS
`drive transistor, a source/drain region of the first MOS
`transfer transistor, a source/drain region of the first thin film
`transistor are connected to each other through a second
`interconnection structure. The first interconnection structure
`comprises a silicon plug layer embedded within an opening
`formed in the interlevel insulating layer and connected to
`both gate electrode of the first MOS drive transistor and
`source/drain region of the second MOS transfer transistor,
`and an interconnection layer of polycrystalline silicon layer
`extending on the surface of the interlevel insulating layer. An
`intermediate conductive layer for reducing a breakdown
`voltage of a pn junction portion is formed between the
`interconnection layer and the silicon plug layer or between
`the silicon plug layer and the source/drain region of the
`second MOS transfer transistor. The second interconnection
`structure comprises a silicon plug layer embedded within an
`opening formed in the interlevel insulating layer and con-
`nected to both gate electrode of the second MOS drive
`transistor and source/drain region of the first MOS transfer
`transistor, and an interconnection layer of polycrystalline
`silicon extending on the surface of the interlevel insulating
`layer. An intermediate conductive layer for reducing a
`breakdown voltage of a pn junction portion is formed
`between the interconnection layer and the silicon plug layer,
`or between the silicon plug layer and the source/drain region
`of the first MOS transfer transistor.
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`In a further aspect of the present invention, a method of
`manufacturing a semiconductor device includes the follow-
`ing steps. First, an interlevel insulating layer is formed on a
`surface of a first silicon layer. An opening reaching the
`surface of the first silicon layer is formed in the interlevel
`insulating layer. A second silicon layer is formed on a
`surface of the interlevel insulating layer and in the opening.
`The second silicon layer is etched back to form a silicon plug
`layer of the second silicon layer formed within the opening.
`Impurity is then introduced into the silicon plug layer. A
`refractory metal layer is formed on surfaces of the interlevel
`insulating layer and the silicon plug layer, and heat treated
`to form a refractory metal silicide layer only on the surface
`of the silicon plug layer, and an unreacted portion of the
`refractory metal layer is removed. A polycrystalline silicon
`layer is formed on surfaces of the interlevel insulating layer
`and the refractory metal silicide layer and patterned to form
`an interconnection layer.
`In yet another aspect of the present invention, a manu-
`facturing method comprises the following steps. First, an
`interlevel insulating layer is formed on a surface of a first
`silicon layer. An opening reaching the surface of the first
`silicon layer is then formed in the interlevel insulating layer.
`A refractory metal silicide layer is formed only on the
`surface of the first silicon layer. A second silicon layer is then
`formed on a surface of the interlevel insulating layer and
`within the opening. The second silicon layer is etched back,
`and a silicon plug layer of the second silicon layer is formed
`within the opening. Impurities are introduced into the silicon
`plug layer. On the surfaces of the interlevel insulating layer
`and the silicon plug layer, a polycrystalline silicon layer is
`formed and patterned to form an interconnection layer.
`In still another aspect of the present invention, a manu-
`facturing method of a serrriconductor device comprises the
`following steps. An interlevel insulating layer is formed on
`a surface of a first silicon layer. An opening reaching the
`surface of the first silicon layer is then formed in the
`interlevel insulating layer. A second silicon layer is formed
`on a surface of the interlevel insulating layer and within the
`opening. The second silicon layer is etched back, and a
`silicon plug layer of the second silicon layer is formed
`within the opening. Impurities are introduced into the silicon
`plug layer. On a surface of the silicon plug layer, an impurity
`layer of a high concentration including impurities in a
`concentration higher than that of impurities included in the
`silicon plug layer. On the surfaces of the interlevel insulating
`layer and the impurity layer of a high concentration, a
`polycrystalline silicon layer is formed and patterned to form
`an interconnection layer.
`In the above manufacturing method, the silicon plug layer
`is formed using an etch back method within the contact hole,
`so that
`the surfaces of the silicon plug layer and the
`interlevel insulating layer can be readily planarized.
`The foregoing and other objects, features, aspects and
`advantages of the present
`invention will become more
`apparent from the following detailed description of the
`present
`invention when taken in conjunction with the
`accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a sectional structural view of a memory cell of
`an SRAM in accordance with a first embodiment of the
`present invention.
`FIGS. 2 through 9 are sectional structural views showing
`manufacturing steps of the memory cell of the SRAM shown
`in FIG. 1.
`
`6
`FIG. 10 is a sectional structural view of a memory cell of
`an SRAM in accordance with a second embodiment of the
`present invention.
`FIGS. 11 and 12 are sectional structural views showing
`major manufacturing steps of the memory cell of the SRAM
`shown in FIG. 10.
`
`FIG. 13 is a sectional structural view of a memory cell of
`an SRAM according to a third embodiment of the present
`invention.
`
`FIGS. 14 through 19 are sectional structural views show-
`ing main manufacturing steps of the memory cell shown in
`FIG. 13.
`
`FIG. 20 is a sectional structural view of a memory cell of
`an SRAM according to a fourth embodiment of the present
`invention.
`
`FIGS. 21 through 24 are section structural views showing
`main manufacturing steps of the memory cell shown in FIG.
`20.
`
`FIG. 25 is a sectional structural View of a memory cell of
`an SRAM in accordance with a fifth embodiment of the
`present invention.
`FIG. 26 is a plan structural view showing a plan structure
`of a lower portion of a memory cell of a conventional
`SRAM.
`
`FIG. 27 is a plan structural view showing a plan structure
`of an upper portion of the memory cell of the conventional
`SRAM.
`
`FIG. 28 is a sectional structural view of the memory cell
`taken along line X—X in FIGS. 26 and 27.
`FIG. 29 is an equivalent circuit diagram of the memory
`cell of the conventional SRAM.
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`FIG. 30 is a sectional structural view showing one of the
`manufacturing steps of the memory cell shown in FIG. 28.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
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`FIG. 1 shows a sectional structure taken at the same
`positionas the position at which the sectional structure of
`FIG. 28 showing a conventional SRAM is taken. The
`sectional structure of the memory cell shown in FIG. 1 is the
`same as the sectional structure of a conventional memory
`cell shown in FIG. 28 except for a structure of direct contact.
`Hence, the direct contact structure will be mainly explained
`in the following, and as for structures of the other portions,
`the description of the background art should be referred to.
`Direct contact portion 10 includes an n type polycrystal-
`line silicon plug layer 15, a titanium silicide layer 11 and a
`p type polycrystalline silicon interconnection layer 8a. An
`opening 16 is formed in an interlevel insulating layer 9. An
`n+ source/drain region 7 of an 11 channel MOS transfer
`transistor 22b and a gate electrode 6 of an 11 channel MOS
`drive transistor 20a are exposed at the bottom of opening 16.
`A plug layer 15 of polycrystalline silicon directly connected
`to the n““ source/drain region 7 and gate electrode 6 is
`embedded within opening 16. N type impurity such as
`phosphorous (P), arsenic (As), etc. is introduced into poly-
`crystalline silicon plug layer 15 in order to provide conduc-
`tivity. A titanium silicide layer (intermediate conductive
`layer) 11 is formed on a surface of polycrystalline silicon
`plug layer 15. An interconnection layer 8a of polycrystalline
`silicon is formed on a surface of titanium silicide layer 11.
`P type impurity is introduced into interconnection layer 8a.
`Thus, the direct contact structure of interconnection layer
`8a with source/drain region 7 and gate electrode 6 improves
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`flatness of interconnection layer 8a, because polycrystalline
`silicon plug layer 15 is embedded within the opening 16.
`Furthermore, ohmic contact of interconnection layer 8a,
`polycrystalline silicon plug layer 15, and source/drain region
`7 can be obtained by having titanium silicide layer 11
`interposed between interconnection layer 8a and polycrys-
`talline silicon plug layer 15. That is because titanium silicide
`layer 11 prevents the formation of pn junction caused by
`direct connection of p type interconnection layer 8a and 11
`type polycrystalline silicon plug layer 15. A thickness of
`titanium silicide layer 11 is preferably in the range of 13 to
`200 nm. If the thickness of the titanium silicide layer is 13
`nm or less, a problem such as a formation of pin holes within
`the film arises.
`
`Steps of manufacturing the memory cell of the SRAM
`shown in FIG. 1 will be described.
`
`Referring to FIG. 2, p type impurity is implanted in a main
`surface of a silicon substrate 1 using, for example, an ion
`implantation method. Subsequently, implanted p type impu-
`rity is diffused to the depth of about 2-3 pm from the main
`surface of substrate 1 by heat treatment to form a p well 2.
`A field oxide film 4 and p”’ isolation layer 3 are formed on
`a prescribed region of a surface of p well 2 for isolation.
`Oxide films 5 of 12 nm—l5 nm thickness are formed on the
`
`surface of p well 2 using, for example, a thermal oxidation
`method. Oxide films 5 form gate oxide films 5,5 of MOS
`transistors 20a, 22b. A polycide film formed of polycrys-
`talline silicon 6a and refractory metal silicide 6b formed
`thereon is deposited on a surface of oxide film 5. The
`polycide film is patterned to a prescribed shape using a
`photolithography method and an etching method to form
`gate electrodes 6, 6 of MOS transistors 20a, 22b. N type
`impurity ion of a dose of 4x105 ions/cm2 is implanted into
`p well 2 by an ion implantation method using the patterned
`gate electrodes 6 as masks. Subsequently, heat treatment is
`performed to activate impurity ions implanted into p well 2.
`Thus, n+ source/drain regions 7 of four MOS transistors 20a,
`20b, 22a, 22b are formed. By following the above steps, n
`channel MOS drive lransistors 20a, 20b and n charmel MOS
`transfer transistors 22a, 2211 are formed. Subsequently, a
`BPSG (BoroPhospho Silicate Glass) film is deposited on the
`whole surface of silicon substrate 1 using, for example, an
`atmospheric pressure CVD (Chemical Vapor Deposition)
`method. The BPSG is softened and reflowed by heat treat-
`ment, so that a surface of the BPSG film is planarized. In this
`step, an interlevel insulating layer 9 having a planarized
`surface is formed. An opening 16 for direct contact is formed
`in interlevel insulating layer 9 using a photolithography
`method, formation of the opening 16 leaving a sidewall
`spacer 9‘ from the interlevel insulating layer 9, and an
`etching method. For the etching method to form opening 16,
`for example, a reactive ion etching method is used.
`Referring to FIG. 3, a polycrystalline silicon layer 15a not
`doped with impurity is formed on a surface of interlevel
`insulating layer 9 using LPCVD (Low Pressure Chemical
`Vapor Deposition) method. Polycrystalline silicon layer 15a
`is deposited so thick as to fill opening 16 completely and
`make a surface of itself substantially flat in an upper portion
`of opening 16. A thickness more than a half of a maximum
`diameter of opening 16 is required as a standard of a
`thickness of polycrystalline silicon layer 15:: to fill opening
`16 completely.
`Referring to FIG. 4, a polycrystalline silicon layer 15a is
`etched, leaving a portion of the polycrystalline silicon layer
`only within opening 16 using an etch back method. Isotropic
`etching is used for the etching. In isotropic etching, poly-
`crystalline silicon layer 15a is isotropically etched on the
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`surface of interlevel insulating layer 9, but in the upper
`portion of opening 16, it is etched flat. As a result, only in
`opening 16, polycrystall