Trials@uspto.gov
`571-272-7822
`
`
`
`Paper 12
`Date Entered: June 8, 2016
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`
`
`
`
`DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-00289
`Patent 5,965,924
`____________
`
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`McNAMARA, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`571-272-7822
`
`
`
`Paper 12
`Date Entered: June 8, 2016
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`
`
`
`
`DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-00289
`Patent 5,965,924
`____________
`
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`McNAMARA, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`IPR2016-00289
`Patent 5,965,924
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`
`BACKGROUND
`
`Intel Corporation (“Petitioner”) filed a petition, Paper 2 (“Pet.”), to
`institute an inter partes review of claims 1–6, 13, 14, and 16 (the
`“challenged claims”) of U.S. Patent No. 5,965,924 (“the ’924 Patent”). 35
`U.S.C. § 311. DSS Technology Management, Inc. (“Patent Owner”) waived
`filing a Preliminary Response. Paper 7. We have jurisdiction under 37
`C.F.R. § 42.4(a) and 35 U.S.C. § 314, which provides that an inter partes
`review may not be instituted unless the information presented in the Petition
`“shows that there is a reasonable likelihood that the petitioner would prevail
`with respect to at least 1 of the claims challenged in the petition.” Having
`considered the arguments and the associated evidence presented in the
`Petition, for the reasons described below, we institute inter partes review 1–
`6, 13, 14, and 16.
`
`
`REAL PARTIES IN INTEREST
`Petitioner identifies itself as the only real party-in-interest. Pet. 7.
`
`PENDING LITIGATION
`The parties state that Patent Owner has asserted the ’924 Patent in the
`following litigation: (1) DSS Technology Management, Inc. v. Intel Corp.,
`No. 6:15-CV-130-RWS (E.D. Tex. filed Feb. 16, 2015); and (2) DSS
`Technology Management, Inc. v. Qualcomm Inc., No. 6:15-CV-692-JRG
`(E.D. Tex. filed July 16, 2015). Pet. 7; Paper 6, at 2.
`Petitioner notes that it has filed a separate petition for inter partes
`review of claims 7–12, 15, and 17 of the ’924 Patent. Pet. 7. That
`proceeding has been designated IPR2016-00290. Paper 6, at 3.
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`THE ’924 PATENT (EXHIBIT 1001)
`The ’924 Patent relates to semiconductor fabrication in general, and in
`particular concerns a metal plug local interconnect that is formed in the same
`process of forming metal plugs that are already designed as sub-metal
`plugged contacts. Ex. 1001, col. 1, ll. 9–11. The ’924 Patent discloses that
`in semiconductor fabrication, it is often necessary to make a local
`interconnect between a gate polysilicon layer to N+ or P+ diffusion regions.
`Id. at col. 1, ll. 16–17. According to the ’924 Patent, conventionally such
`local interconnects were fabricated using buried contacts, as shown in
`Figures 1A and 1B of the ’924 Patent (id. at col. 1, l. 25–col. 2, l. 11) or with
`a metallic local interconnect strap to shunt from a gate polysilicon to a
`diffusion region, as illustrated in Figures 2A and 2B of the ’924 Patent (id. at
`col. 2, l. 12–41).
`The ’924 Patent discloses a semiconductor structure in which a
`diffusion region is formed in a silicon substrate and a polysilicon gate is
`formed on the top surface of the silicon substrate adjacent to, but not
`contacting, the diffusion region. Ex. 1001, col. 3, ll. 1–6, 14–18. A layer of
`insulating material is then deposited on top of the polysilicon gate and the
`diffusion region. Id. at col. 3, ll. 6–7, 19–20. A via opening is formed in the
`insulating material to expose a portion of the polysilicon gate and a portion
`of the diffusion region. Id. at col. 3, ll. 7–8, 20–22. An electrically
`conducting material is deposited to at least partially fill the via opening to
`provide an electrical connection between the polysilicon gate and the
`diffusion region. Id. at col. 3, ll. 8–11, 23–27.
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`ILLUSTRATIVE CLAIM
`1. A semiconductor structure comprising:
`a silicon substrate having a top surface,
`a diffusion region formed in said substrate adjacent to said
`top surface,
`a gate formed on the top surface of said substrate
`juxtaposed to but not contacting said diffusion region,
`a sidewall spacer adjacent to said gate and disposed above
`said diffusion region,
`an insulator layer substantially covering said gate and said
`diffusion region, and
`a conducting plug at least partially filling a via in said
`insulation layer that exposes said sidewall spacer in the
`absence of said conducting plug, said conducting plug
`providing direct electrical communication between
`said gate and said diffusion region.
`
`ART CITED IN PETITIONER’S CHALLENGES
`
`Petitioner cites the following references in its challenges to
`patentability:
`
`Sakamoto, U.S. Patent No. 5,475,240 issued Dec. 12, 1995, Ex. 1003
`(“Sakamoto”); and
`
`Cederbaum et al., U.S. Patent No. 5,100,817 issued Mar. 31, 1992,
`Ex. 1004 (“Cederbaum”).
`
`CHALLENGES ASSERTED IN PETITION
`Claims
`Statutory Basis
`Challenge
`Anticipation by
`1–3, 14, and 16
`35 U.S.C. § 102(e)
`Sakamoto
`Obviousness over the
`combination of
`Sakamoto and
`Cederbaum
`
`35 U.S.C. § 103
`
`4–6, and 13
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`CLAIM CONSTRUCTION
`The ’924 Patent issued from an application that was a continuation of
`Appl. No. 08/561,951 filed on Nov. 22, 1995. Thus, the ’924 Patent is
`expired. We construe the claims of an expired patent in accordance with the
`standard set forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005)
`(en banc). See In re Rambus, 694 F.3d 42, 46 (Fed. Cir. 2012) (“While
`claims are generally given their broadest possible scope during prosecution,
`the Board’s review of the claims of an expired patent is similar to that of a
`district court’s review.”). “In determining the meaning of the disputed claim
`limitation, we look principally to the intrinsic evidence of record, examining
`the claim language itself, the written description, and the prosecution
`history, if in evidence.” DePuy Spine, Inc. v. Medtronic Sofamor Danek,
`Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips, 415 F.3d at
`1312–17). Only those terms that are in controversy need to be construed,
`and only to the extent necessary to resolve the controversy. Vivid Techs.,
`Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`The only term Petitioner proposes we construe is “diffusion region
`formed in said substrate.” Petitioner proposes that we construe this term to
`mean “conductive terminal region, such as a source or drain, that contains
`dopants implanted in the silicon substrate.” Pet. 25. Petitioner states that in
`the co-pending litigation Patent Owner has proposed “diffusion region
`formed in said substrate” be construed to mean a “conductive terminal
`region such as a source or drain formed in said substrate.” Id. Petitioner
`cites the portion of the ’924 Patent specification referencing Figures 3A and
`3B that discloses that diffusion regions 70 and 72 of either N+ or P+ doping
`are formed by an ion implantation in the surface of the silicon substrate 74 in
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`which a photoresist layer is used as an ion implantation mask. Id. at 26
`(citing Ex. 1001, col. 3, ll. 46–51); Ex. 1001, col. 3, ll. 46–55. Petitioner
`also cites the Declaration of Dr. John C. Bravman, Ex. 1002 (“Bravman
`Decl.”), for the proposition that, at the time of the invention, one of ordinary
`skill in the art would have understood that a diffusion region is a conductive
`terminal region, such as a source or drain, that contains dopants implanted in
`the substrate. Pet. 27 (citing Bravman Decl. ¶ 65).
`The subject matter of the claims concerns a local interconnect
`between a gate and a diffusion region. For purposes of this decision, we
`need not further construe the term “diffusion region formed in said
`substrate.”
`
`ANALYSIS OF PETITIONER’S PRIOR ART CHALLENGES
`
`
`Introduction
`A claim is unpatentable under 35 U.S.C. § 102 if a prior art reference
`discloses every limitation of the claimed invention, either explicitly or
`inherently. Glaxo Inc. v. Novopharm Ltd., 52 F.3d 1043, 1047 (Fed. Cir.
`1995); see MEHL/Biophile Int’l Corp. v. Milgraum, 192 F.3d 1362, 1365
`(Fed. Cir. 1999) (“[t]o anticipate, a single reference must teach every
`limitation of the claimed invention”; any limitation not explicitly taught
`must be inherently taught); In re Baxter Travenol Labs., 952 F.2d 388, 390
`(Fed. Cir. 1991) (the dispositive question is “whether one skilled in the art
`would reasonably understand or infer” that a reference teaches or discloses
`all of the elements of the claimed invention); Continental Can Co. USA v.
`Monsanto Co., 948 F.2d 1264, 1268–69 (Fed. Cir. 1991) (to anticipate,
`every element of the claims must appear in a single prior art reference, or if
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`not expressly shown, then demonstrated to be known to persons experienced
`in the field of technology).
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art; and (4) objective evidence of
`nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`Anticipation By Sakamoto
`Petitioner contends that Sakamoto not only is directed to the same
`problem as that addressed by the ’924 Patent, i.e., connecting different
`transistor portions together, but also that Sakamoto discloses the same
`solution as that found in the ’924 Patent, i.e., using a single plug. Pet. 21.
`Sakamoto “relates to improvement of a contact structure of an
`interconnection in a region having steps in a semiconductor device having a
`multilayer interconnection structure.” Ex. 1003, col. 1, ll. 12–16. Petitioner
`provides the following figure comparing an annotated version of Figure 1 of
`Sakamoto on the left with an annotated version of Figure 3B of the ’924
`Patent on the right:
`
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`Petitioner’s comparison of Sakamoto Fig. 1
` and ’924 Patent Figure 3B
`Pet. 22. Petitioner contends that Sakamoto discloses a plug filling an
`opening having a sidewall spacer that electrically connects a diffusion region
`to a gate, as claimed in the ’924 Patent. Id. Petitioner addresses each of the
`limitations of the claims challenged as anticipated by Sakamoto and
`discusses why specific features of Sakamoto are anticipatory. Id. at 29–48.
`Turning to claim 1, Petitioner notes that Sakamoto’s static random
`access memory (SRAM) is a semiconductor structure. Pet. 29–30 (citing
`Ex. 1003, col. 1, ll. 13–16; Bravman Decl. ¶ 70). Petitioner next addresses
`the structure of Sakamoto’s substrate. Id. at 30–40. Claim 1 recites the
`following elements as designated by Petitioner: (a) a silicon substrate
`having a top surface, (b) a diffusion region formed in said substrate adjacent
`said top surface [of said substrate], (c) a gate formed on the top surface of
`said substrate juxtaposed to but not contacting said diffusion region; (d) a
`sidewall spacer adjacent to said gate and disposed above said diffusion
`region, (e) an insulator layer substantially covering said gate and said
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`diffusion region, and (f) a conducting plug at least partially filling a via in
`said insulation layer that exposes said sidewall spacer in the absence of said
`conducting plug, said conducting plug providing direct electrical
`communication between said gate and said diffusion region.
`Figure 1 of Sakamoto delineates a main silicon substrate 1 and a p-
`well region 2 above it. Petitioner acknowledges that Figure 1 of Sakamoto
`illustrates a p-well region 2, but contends that the p-well region is part of the
`silicon substrate. Id. at 30. Petitioner argues that p-well region 2 is formed
`below the top surface of silicon substrate and a source/drain region 7 is
`formed in the silicon substrate below the top surface of p-well region 2. Id.
`at 34. Petitioner provides the further annotated version of Figure 1 of
`Sakamoto shown below:
`
`
`
`Annotated version of Figure 1 in Petition
`Id. Petitioner contends that p-well region 2 is part of the silicon substrate
`because p-well region 2 is formed in the surface of the substrate. Id. at 30
`(citing Ex. 1003, col. 7, ll. 17–21 (disclosing that a “p type impurity is
`implanted in a main surface of a silicon substrate” and that the “implanted p
`type impurity is diffused to the depth of about 2–3 µm from the main surface
`of substrate 1 by heat treatment to form a p well 2”)). Petitioner also notes
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`that during prosecution, the applicant for the ’924 Patent did not dispute the
`Examiner’s assertion that a diffusion region is formed within a silicon
`substrate and argued that the cited reference (Kinoshita) disclosed buried
`ground layers in the substrate. Id. at 31–32 (citing Ex. 1013 and Ex. 1014).
`Petitioner further contends that in at least one embodiment (the fifth
`embodiment shown in Figure 25), Sakamoto does not delineate the p-well
`region, stating that an n-type impurity region is formed on a surface of the
`silicon substrate. Id. at 32–33 (citing Ex. 1003, col 12, ll. 57–58). It is
`unclear if there is a distinction to be drawn between Sakamoto’s first four
`embodiments, which all delineate p-well region 2 and Sakamoto’s fifth
`embodiment in which p-well region 2 is not shown. However, for purposes
`of this Decision, we accept Petitioner’s contention that the implanted p-well
`region is part of the silicon substrate.
`Based on this analysis, we are persuaded by Petitioner’s argument that
`Sakamoto discloses element (a) a silicon substrate with a top surface. As to
`element (b), we are persuaded by Petitioner’s argument that Sakamoto
`discloses a diffusion region formed in said substrate. Element (b) also
`recites that the diffusion region is adjacent said top surface. Having accepted
`Petitioner’s contention that the p-well region is part of the substrate, Figure 1
`of Sakamoto illustrates a diffusion region in the form of source/drain region
`7 adjacent to the top surface of the substrate.
`Element (c) of claim 1, as designated by Petitioner, recites “a gate
`formed on the top surface of said substrate juxtaposed to but not contacting
`said diffusion region.” Figure 1 of Sakamoto illustrates field oxide film 4
`and p+ isolation layer 3 formed on a prescribed region of a surface of p-well
`2 for isolation. Ex. 1003, col. 7, ll. 22–23. Oxide film 5 is formed on the
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`surface of the p-well 2. Id. at col. 7, ll. 23–24. A polycide film of
`polysilicon and refractory metal silicide is deposited on the surface of oxide
`film 5 and patterned to form gate electrode 6. Id. at col. 7, ll. 24–31.
`Petitioner contends that the placement of the gate electrode in
`Sakamoto over a field oxide layer constitutes forming the gate on the top
`layer of the substrate because the applicant for the ’924 Patent relied on
`conception of the same physical construct during prosecution in a
`Declaration under 37 C.F.R. § 1.131 (“Rule 131 Declaration”). Pet. 37 n.7
`(citing Ex. 1006, Ex. A).1 The specification of the ’924 Patent does not
`discuss forming the gate electrode on the substrate in detail, stating only that
`a photoresist layer used to pattern and etch openings for the diffusion
`regions is removed and that polysilicon then deposited on substrate 74 is
`etched to form gate electrode 74. Ex. 1001, col. 3, ll. 49–58. In this context,
`the statements in applicant’s Rule 131 Declaration provide context to the
`meaning of “a gate formed on the top surface of the substrate.” In order to
`antedate a reference, Patent Owner demonstrated an invention in which the
`gate electrode is formed over a field oxide layer. Therefore, for purposes of
`this Decision and on the current record, we agree with Petitioner that taken
`in the proper context, notwithstanding the presence of the field oxide layer 4
`and field oxide film 5, Sakamoto discloses the gate electrode formed on the
`top surface of the substrate.
`Petitioner also argues that the gate in Sakamoto is juxtaposed from but
`is not in direct contact with the diffusion region, as recited in claim 1. Pet.
`38–40. Petitioner contends that oxide film 5 separates the gate from the
`
`
`1 Petitioner appears to be citing to the center figure at the top of page 11 of
`Ex. 1006.
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`diffusion region, noting that there would be no need for the claimed plug to
`connect the gate and the diffusion region if this were not the case. Id. at 39.
`Sakamoto states:
`The sectional structure of the memory cell shown in FIG. 1 [of
`Sakamoto] is the same as the sectional structure of a
`conventional memory cell shown in FIG. 28 except for a
`structure of direct contact. . . .
`
`Direct contact portion 10 includes an n type
`polycrystalline silicon plug layer 15 . . . directly connected to
`the n+ source/drain region 7 and gate electrode 6 . . . embedded
`within opening 16.
`
`Ex. 1003, col. 6, ll. 42–58. Figures 1 and 28 in Sakamoto illustrate that
`because of the presence of oxide film 5 there is no direct contact between
`gate 6 and source/drain region 7.
`Petitioner designates as element (d) of claim 1 the recitation “a
`sidewall spacer adjacent to said gate and disposed above said diffusion
`region.” Pet. 40. Petitioner designates as element (e) of claim 1 the
`recitation of “an insulator layer substantially covering said gate and said
`diffusion region.” Id. at 42. Petitioner cites insulating layer 9 shown in
`Figure 1 of Sakamoto as disclosing element (e) of claim 1 of the ’924 Patent.
`Id. Petitioner cites sidewall spacer 9’ in Figure 1 of Sakamoto as disclosing
`the claimed sidewall spacer. Id. at 40–41. Sakamoto discloses interlevel
`insulating layer 9 disposed above the gate and diffusion region and that an
`opening 16 for direct contact formed using a photolithography method
`leaves sidewall spacer 9’. Ex. 1003, col. 7, ll. 47–51.
`Petitioner designates as element (f) of claim 1 the recitation “a
`conducting plug at least partially filling a via in said insulation layer that
`exposes said sidewall spacer in the absence of said conducting plug, said
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`conducting plug providing direct electrical communication between said
`gate and said diffusion region.” Pet. 43. As Petitioner notes (id. at 43–45),
`Sakamoto discloses an n type polycrystalline silicon plug layer 15 to connect
`directly the source/drain region and gate electrode. Ex. 1003, col. 6, ll. 42–
`58. Based on this analysis and on the current record at this stage of the
`proceeding, Petitioner has demonstrated that Sakamoto discloses all of the
`elements of claim 1.
`Claim 2 depends from claim 1 and recites that the diffusion region is
`an N+ or P+ region. Petitioner notes that Sakamoto discloses the diffusion
`region as an N+ region because it expressly refers to an n+ source drain
`region 7. Id. at 45–46.
`Claim 3 depends from claim 1 and recites that the insulator layer is
`formed of material selected from the group consisting of silicon oxide and
`silicon nitride. Petitioner cites Sakamoto’s disclosure of softening and
`reflowing BoroPhosphoSilicate Glass (BPSG) film to form insulating layer
`9, stating that BPSG is a type of silicon oxide. Id. at 46 (citing Bravman
`Decl. ¶ 90; Ex. 1015, at 185).2
`Claim 14 depends from claim 1 and recites the further limitation “said
`polysilicon gate and said diffusion region being exposed in said via in the
`absence of said conducting plug.” Petitioner notes that this feature is
`disclosed in at least Figure 1 of Sakamoto. Id. at 47.
`Claim 16 depends from claim 1 and recites “said gate comprises
`polysilicon.” Petitioner notes that Sakamoto discloses the gate electrode 6 is
`
`
`2 Although Petitioner does not cite Ex. 1015 as a basis for its challenge that
`claim 2 is anticipated by Sakamoto, we understand Petitioner’s citation to
`demonstrate that one of ordinary skill would infer the limitation is disclosed
`by Sakamoto. In re Baxter Travenol Labs., 952 F.2d at 390.
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`formed of polycrystalline silicon, which is another name for polysilicon. Id.
`at 48.
`
`In consideration of the above, Petitioner has demonstrated a
`reasonable likelihood that it will prevail in its challenge to claims 1–3, 14,
`and 16 as anticipated by Sakamoto and we institute a trial on this ground.
`Obviousness Over Sakamoto and Cederbaum
`Petitioner contends that claims 4–6 and 13 are obvious over the
`combination of Sakamoto and Cederbaum. Comparing Figure 7 of
`Cederbaum to Figure 3B of the ’924 Patent, Petitioner contends that
`Cederbaum discloses a structure that includes components arranged in a way
`that is identical to those of Fig. 3B of the ’924 Patent. Pet. 23. The figure
`below is Petitioner’s comparison of Fig 7 of Cederbaum on the left and
`Figure 3B of the ’924 Patent on the right.
`
`
`
`Petitioner’s Comparison of Fig. 7 of Cederbaum
`to Fig 3B of the ’924 Patent
`Id. Petitioner emphasizes that, like the ’924 Patent, Cederbaum concerns the
`use of a contact stud or conducting plug to fill an opening with a sidewall
`spacer to directly connect a source/drain region to a gate electrode. Id. at
`23–24.
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`According to Petitioner, one of ordinary skill would have been
`motivated to combine the teachings of Cederbaum with those of Sakamoto
`because they both teach the same type of device and are directed to the same
`problem, i.e., stacking transistors in an SRAM. Pet. 51. Petitioner points
`out that Cederbaum and Sakamoto also disclose nearly identical structures
`with nearly identical components, with both employing an electrically
`conducting plug within an opening that contains a sidewall spacer to directly
`connect a diffusion region to a gate. Id. at 52–53. Petitioner cites
`Cederbaum’s disclosure of materials, such as refractory metals, to be used in
`forming the conductive plug and Sakamoto’s discussion of the advantages to
`using a conductive plug of increased conductivity. Id. at 53–54. Thus,
`Petitioner contends it would have been obvious to one of ordinary skill to
`replace the polycrystalline plug 15 of Sakamoto with a refractory metal plug
`of tungsten, as disclosed by Cederbaum. Id. at 51. This feature (“said
`electrically conducting plug is a refractory metal plug”) is recited in claim 5
`of the ’924 Patent. Claim 4 recites a metal plug and claim 6 recites the
`electrically conducting plug is formed of a material selected for the group
`consisting of titanium, tantalum, molybdenum, and tungsten. Petitioner cites
`Cederbaum’s disclosure at column 9, lines 31–65 as disclosing a tungsten
`conducting plug. Id. at 49–50.
`Claim 13 of the ’924 Patent depends from claim 1 and recites the
`further limitation “said conducting plug comprises an outer glue layer and a
`plug material therein.” Petitioner cites Cederbaum as disclosing an outer
`glue titanium nitride (TiN) layer and an inner plug material, i.e., tungsten.
`Pet. 55. Petitioner contends that one of ordinary skill would have
`understood that because the TiN is deposited in opening 28 of Cederbaum
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`before the tungsten is deposited, the TiN layer is an outer glue layer and the
`tungsten is the inner plug material. Id at 55–56 (citing Ex. 1004, col. 9, ll.
`31–47). Petitioner further notes that Cederbaum discloses the TiN layer acts
`as an outer glue layer because it improves adhesion of the inner tungsten
`layer. Id. at 56 (citing Ex. 1004, col. 9, ll. 36–43).
`In consideration of the above, we are persuaded that Petitioner has
`demonstrated a reasonable likelihood it will succeed in its challenge to
`claims 4–6 and 13 as obvious over the combination of Sakamoto and
`Cederbaum and we institute a trial on this ground.
`
`SUMMARY
`For the reasons discussed above, we are persuaded that Petitioner has
`demonstrated a reasonable likelihood that it will succeed on the following
`challenges to patentability:
`Claims 1–3, 14 and 16 as anticipated under 35 U.S.C. § 102(e) by
`Sakamoto; and
`Claims 4–6 and 13 as obvious under 35 U.S.C. § 103(a) over the
`combination of Sakamoto and Cederbaum.
`
`
`ORDER
`In consideration of the foregoing, it is hereby:
`ORDERED that pursuant to 35 U.S.C. § 314(a) an inter partes review
`of the ’924 Patent is hereby instituted, commencing on the entry date of this
`Order, and pursuant to 35 U.S.C. § 314(c) and 37 C.F.R. § 42.4, notice is
`hereby given of the institution of a trial.
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`
`FURTHER ORDERED that the trial is limited to the following
`grounds and no other grounds are authorized:
`Claims 1–3, 14 and 16 as anticipated under 35 U.S.C. § 102(e) by
`Sakamoto; and
`Claims 4–6 and 13 as obvious under 35 U.S.C. § 103(a) over the
`combination of Sakamoto and Cederbaum
`FURTHER ORDERED that the trial will be conducted in accordance
`with the accompanying Scheduling Order. In the event that an initial
`conference call has been requested or scheduled, the parties are directed to
`the Office Trial Practice Guide, 77 Fed. Reg. 48,756, 48,765–66 (Aug. 14,
`2012), for guidance in preparing for the initial conference call, and should
`come prepared to discuss any proposed changes to the scheduling order
`entered herewith and any motions the parties anticipate filing during the
`trial.
`
`
`
`
`
`17
`
`
`
`IPR2016-00289
`Patent 5,965,924
`
`
`
`PETITIONER:
`
`Grant K. Rowan
`Yung-Hoon Ha
`Wilmer Cutler Pickering Hale and Dorr, LLP
`grant.rowan@wilmerhale.com
`yung-hoon.ha@wilmerhale.com
`
`
`
`PATENT OWNER:
`
`
`
`Andriy Lytvyn
`Anton J. Hopen
`Nicholas Pfeifer
`Smith & Hopen, P.A.
`andriy.lytvyn@smithhopen.com
`anton.hopen@smithhopen.com
`nicholas.pfeifer@smithhopen.com
`
`
`
`
`
`
`18
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