Our Reference: 16820.P097
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`APPLICATION FOR UNITED STATES PATENT
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`FOR
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`METHOD FOR ELIMINATING LATERAL SPACER
`EROSION ON ENCLOSED CONTACT TOPOGRAPHIES
`DURING RF SPUTTER CLEANING
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`\.
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`Inventors:
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`JAMES E. NULTY
`CHRISTOPHER I. PETTI
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`Prepared by:
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`BLAKELY SOKOLOFF TAYLOR & ZAFMAN
`12400 Wilshina Boulevard
`Seventh Floor
`Los Angeles. CA 90025
`(310) 207-3800
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`
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`I hereby certify that this correspondence is
`being deposited with the United States Postal
`Service as Express Mail (Label No: 1g '79:. us‘: ‘:5 7-
`in an envelope addressed to: Commissioner of Patents
`and
`arks
`‘ gton, D.C. 20231 on:
`$94
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`1397
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`Na me
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`/2/22 /9;"
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`Date
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`INTEL 1 109
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`The invention relates to semiconductor device processes, and more
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`particularly, to improved methods for etching openings in insulating layers and a
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`semiconductor device with well defined contact openings.
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`Bggkggggggj Qf thg Invention
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`In the fabrication of semiconductor devices, numerous conductive device
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`regions and layers are formed in or on a semiconductor substrate. The conductive
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`regions and layers of the device are isolated from one another by a dielectric.
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`Examples of dielectrics include silicon dioxide, SiO2, tetraethyl orthosilicate glass
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`("TEOS"), silicon nitrides, SixNy, silicon oxynitrides, SiOxNy(I-I2), and silicon
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`dioxide/silicon nitride/silicon dioxide ("ONO"). The dielectrics may be grown, or
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`may be deposited by physical deposition (e.g., sputtering) or by a variety of chemical
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`deposition methods and chernistries (e.g., chemical vapor deposition ("CVD")).
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`Additionally, the dielectrics may be undoped or may be doped, for example with
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`boron, phosphorous, or both, to form, for example, borophosphosilicate glass
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`("BPSG"), phosphosilicated glass ("PSG"), and borophosphosilicate tetraethyl
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`orthosilicate glass ("BP'l"EOS").
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`At sev a1 stages of the fabrication of semiconductor devices, it is necessary to
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`make openings in
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`e dielectric to allow for contact to underlying regions or layers.
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`Generally, an opening hrough a dielectric exposing a diffusion region or an
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`opening through a dielect ‘c layer between polysilicon and the first metal layer is
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`called a "contact opening", w ' e an opening in other oxide layers such as an
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`nin throu h an intermetal di ectric la er is referred to as a "via". For ur oses
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`of the cla‘
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`ed invention, henceforth "contact opening" or "contact region" will be
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`used to refer
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`contact openings and/ or via. The opening may expose a device
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`region within th silicon substrate, such as a source or drain, or may expose some
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`other layer or stru
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`interconnect layer, or
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`ucture such as a gate. After the opening has been formed
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`re, for example, an underlying metallization layer, local
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`exposing a portion of the egion or layer to be contacted, the opening is generally
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`cleaned with a sputter etch eg, a Radio-Frequency ("RF") sputter etch, and then the
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`opening is filled with a cond xtive material deposited in the opening and in
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`electrical contact with the uncle
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`r yingggiczn_o_r_Jay£:.~
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`To form the openings a patterning layer of photoresist is first formed over the
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`dielectric layer having openings corresponding to the regions of the dielectric where
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`the dielectric layer openings are to be formed.
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`In most modern processes a dry etch
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`is then performed wherein the wafer is exposed to a plasma, formed in a flow of one
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`or more gases. Typically, one or more halocarbons and] or one or more other
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`halogenated compounds are used as the etchant gas. For example, CF4, CHF3 (Freon
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`23), SF5, NF3, and other gases may be used as the etchant gas. Additionally, gases
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`such as 02, Ar, N2, and others may be added to the gas flow. The particular gas
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`mixture used will depend on, for example, the characteristics of the dielectric being
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`etched, the stage of processing, the etch tool being used, and the desired etch
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`characteristics, i.e., etch rate, sidewall slope, anisotropy, etc.
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`Many of the etch characteristics are generally believed to be affected by
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`polymer residues that deposit during the etch. For this reason, the fluorine to
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`carbon (F/C) ratio in the plasma is considered an important determinant in the etch.
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`In general, a plasma with a high F/C ratio will have a faster etch rate than a plasma
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`25 with a low F/C ratio. At very low rates, i.e., high carbon content, polymer
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`deposition occurs and etching ceases. The etch rate as a function of the F / C ratio is
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`typically different for different materials. The difference is used to create a selective
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`etch, by using a gas mixture that puts the F/ C ratio in the plasma at a value tlmt
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`leads to etching at a reasonable rate for one material, and that leads to no etching or
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`polymer deposition for another. For example, an etchant that has an etch rate ratio
`or a selectivity ratio of two to one for silicon nitride compared to silicon dioxide is
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`5
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`an effective stripper of silicon nitride from the semiconductor substrate. because it
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`will selectively strip silicon nitride over silicon dioxide on a substrate surface. An
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`etchant that has an etch rate ratio or a selectivity ratio of 0.85 to one for silicon
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`nitride compared to silicon dioxide is not considered an effective stripper of silicon
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`nitride from the semiconductor substrate because the etchant will not effectively
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`strip silicon nitride to the exclusion of silicon dioxide.
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`The selectivity of the etch process is a useful parameter for monitoring the
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`process based on the etch rate characteristic of the particular etchant. As noted
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`above, particular etchants or etchant chemistries attack different materials at
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`different etch rates. With respect to dielectrics, for example, particular etchants
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`attack silicon dioxide, BPTEOS, TEOS, and silicon nitride dielectrics at different rates.
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`To make openings in a substrate comprising a Contact region surrounded by
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`different dielectric layers, e.g., a dielectric layer of TEOS surrounded by a dielectric
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`layer of silicon nitride, a process will utilize different etchants to make openings
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`29
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`through the different dielectrics. Thus, the different E‘td‘l rates of particular dielectric
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`layers for anuetchant may be used to monitor the creation of an opening through a
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`dielectric layer.
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`Further, by adjusting the feed gases, the taper of the sidewall in the etched
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`opening of the dielectric can be varied.
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`If a low sidewall angle is desired, the
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`chemistry is adjusted to try to cause some polymer buildup on the sidewall.
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`Conversely, if a steep sidewall angle is desired, the chemistry is adjusted totry to
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`/ prevent polymer buildup on the sidewall. Varying the etch gas pressure, for
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`example, has a significant effect on the shape of the opening. This is because the
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`etchant ions generally arrive in a direction perpendicular to the substrate surface,
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`and hence strike the bottom surfaces of the unmasked substrate. The sidewalls of
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`etched openings, meanwhile, are subjected to little or no bombardment. By
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`increasing the pressure of the etch gas, the bombardment directed toward the
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`sidewalls is increased; by decreasing the pressure of the etch gas, the bombardment
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`directed toward the sidewalls is decreased. The changing of the etch chemistry is
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`also directly related to selectivity. Etchants that provide a near 90° sidewall angle are
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`generally not highly selective while highly selective etches typically produce a
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`sloped sidewall.
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`Following the dielectric etch(es) and prior to any conductive material
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`contact region is removed or cleaned through a non-chemical sputter etch, e.g., an
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`RF sputter etch.
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`In addition to alleviating the contact region of native oxide, the
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` deposition in a contact region, native oxide on top of the conducting layers in the
` of the sputter etch must be carefully monitored so as not to excessively erode the
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`sputter etch can erode any insulating dielectric layer or layers. Thus, the parameters
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`insulating dielectric layer(s) and expose other underlying conductive material.
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`Exposing insulated conductive material adjacent to the conductive material in the
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`contact region results in poor quality contacts or a short circuit through the
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`underlying conductive material. For a thorough discussion of oxide etching, see 5.
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`Wolf and R.N. Tauber, Silicon Prgggssing fgr the VLSI Era Vol. 1, pp. 539-85 (1986).
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`—
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`The precedki discussion focused on the making of openings, e.g., contact
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`fit
`' openings, in dielectri
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`material on a semiconductor substrate. The same principles
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`are used in constructin device regions with a dielectric layer or layers, As
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`7.5
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`ing of discreet devices on a semiconductor substrate
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`geometries shrink, the for
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`becomes more sp
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`alizedr Specialized deposition and etching techniques permit
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`translates into larger memor rating speeds, and reduced production costs.
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`the density of semicondu
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`elements on a single chip to greatly increase, which
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`A typical metal oxide semiconductor (MOS) transistor, e.g., NMOS or PMOS
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`5
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`transistor, generally includes sourceldrain regions in a substrate, and a gate
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`electrode formed above the substrate between the source/ drain regions and
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`separated from the substrate by a relatively thin dielectric. Contact structures can be
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`inserted to the source/ drain regions and interlays can overlie the contact structures
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`and connect neighboring contact structures. These contact structures to the
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`diffusion region are isolated from the adjacent gate by dielectric spacer or shoulder
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`portions. The dielectric spacer or shoulder portions also isolate the gate from the
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`diffusion region.
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`Conventional contact structures limit the area of the diffusion region, because
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`the contact hole is aligned to these regions with a separate masking step, and extra
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`area must be allocated for misalignment. Proper alignment is necessary to avoid
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`shorting the contact structure to the gate or the diffusion well. The larger contact
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`area means a smaller density of elements on a structure. The larger contact area is
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`also responsible for increased diffusion-to~substrate junction capacitance, which
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`limits device speed.
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`A self-aligned contact eliminates the alignment problems associated with’
`conventional contact structures and increases the device density ‘of a structure. A
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`self-aligned contact is a contact to a source or drain diffusion region. A self—aligned
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`contact is useful in compact geometries because it can overlap a conducting area to
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`which it is not supposed to make electrical contact and can overlap the edge of a
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`diffusion region without shorting out to the well beneath Consequently, less
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`contact area is needed and gates or conductive material lines, e.g., polysilicon lines,
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`can be moved closer together allowing more gates or lines on a given substrate than
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`traditional contacts.
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`e 1 illustrates a self-aligned contact between two gate structures. Figure
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`1(A) is a
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`anar top view of the contact. Figure 1(8) is a planar cross-sectional view
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`of a self-ali
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`ed contact between a pair of gates taken through line 1(8) of Figure
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`1(A). Figure ,1 C) is a planar cross-sectional view of a self-aligned contact between a
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`pair of gates tak
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`through line 1(C) of Figure 1(A).
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`contact is a contact to a source or drain diffusion region (n+
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`or p+ silicon) 140 that
`n overlap the edge of the diffusion region 140 without
`shorting out to the well b
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`in Figure 1(C), the contact 130 does not lie directly
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`eath the diffusion region 140. This can be seen most
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`illustratively through Figure C).
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`in the diffusion region 140, but misaligned and slightly overlaps the field oxide.
`In this illustration, the self-aligned ontact is not directly over the diffusion region
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`but extends over (i.e., overlaps) a wel
`short to the well portion 170 because th self-aligned contact is separated from the
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`rtjon 170. The self-aligned contact does not
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`well 170 by the field oxide.
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`The self-aligned Contact 130 is separate
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`110 by an encapsulating dielectric layer 120 such
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`from a conducting polysilicon layer
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`at the Contact 130 can also overlap
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`the polysilicon layer 110 without making electrical
`The polysilicon layer 110 is separated from the source drain diffusion region 140 by
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`ntact to the layer 110 or gate.
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`a dielectric spacer or shoulder 150 of the same or differe t dielectric material as the
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`dielectric layer 120 directly above the conducting polysilic
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`A distinct dielectric etch stop layer 125 overlies the enca sulating dielectric
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`layer 120. The etch stop layer 125 permits subsequent etching of he substrate
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`structuring and
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`without ris of exposing the device structures and layers because the device
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`ers are protected from excessive etching by the etch stop layer.
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`The diffusion contac ’
`self—aligning because the structure can be etched to the
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`substrate over the source
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`5
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`protects the polysilicdn layer
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`ain diffusion region 140 while the dielectric spacer 150
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`0. Even if a photoresist that protects the polysilicon
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`layer 110 from the etchant is misa '
`dielectric spacer 150gprevents ShOf €
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`ed with respect to the polysiiicon layer 110, the
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`polysilicon layer 110 when the contact 130
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`is provided for the diffusion region 140.
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`/\
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`to protect uncle
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`ing regions, like the etch stop layer and the first insulating layer.
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`Figure 2 demonstr
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`es a typical prior art process of forming a self-aligned Contact
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`region adjacent to a ga
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`.
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`In Figure 2(A), a gate oxide layer 210 is formed on a
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`substrate 200 with a cond cting layer, for example a polysilicon layer 220, overlying
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`the gate oxide layer 210, and n insulating layer, for example a TEOS layer 230,
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`overlying the polysilicon layer
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`0. Adjacent to the polysilicon layer is a contact
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`opening region 270. The polysilico layer 220 is separated from the contact region
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`270 by an insulating spacer portion, foi\example a TEOS spacer portion 235. A
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`25
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`the TEOS layer 230 and the contact region 2
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`. A blanket layer, for example a doped
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`insulating layer like a BPTEOS layer 250, plana
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`overlies the etch stop layer 240.
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`separate insulating or etch stop layer, foi'\&z:rriple a silicon nitride layer 240 overlies
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`In Figure ?.(A), a co tact opening 270 has been
`opened through the BPTEOS layer 250. The etchant utili
`d to make the opening
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`had a high selectivity toward BPTEOS relative to silicon ni
`' e. When the contact
`\\
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`A layer of photoresist material 280 overlies t
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`planarized BPTEOS layer 250
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`to expose the contact opening 270.
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`openin was through the BPTEOS material, the etchant did not etch or did not
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`effectively
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`ch the silicon nitride layer 240 material. Hence the description of the
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`er 240 as an etch stop layer. The silicon nitride etch stop layer
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`protected the uncle ying TEOS layer so that the polysilicon remains completely
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`5
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`encapsulated.
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`igure 2(A) illustrates an etch 260 to remove the silicon nitride etch stop layer
`0 20. In t
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`etch illustrated in Figure 2(A), a high selectivity etch toward silicon
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`nitride relati e to the underlying TEOS layer 230 material is practiced to efficiently
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`etch the silicon 'tride l_ayer and to protect the underlying TEOS layer 230 from the
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`etchant. An exam le of a high selectivity etch recipe to effectively strip silicon
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`nitride as compared
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`the TEOS layer is 30 sccm CI~l.‘F3 and 30 sccm 02 at 60 mtorr
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`2(8).
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` nitride compared to TEOS material, owever, left the TEOS layer 230 with a spacer
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`and 100 watts of power. The result of the highuselectivity etch is illustrated in Figure
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`Figure 2(B) shows that
`e silicon nitride selective etch effectively removed
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`opening 270. The selective etch for silicon
`silicon nitride 240 from the conta
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`portion 235 wherein the spacer portion ' sloping or tapered toward the contact
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`opening. This result follows even where
`e spacer portion 235 is originally
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`substantially rectangular as in Figure 2(A).
`etch of the overlying etch stop layer will transf
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`e properties of the highly selective
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`In a_ substantiallyrectangular spacer
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`into a sloped spacer.
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`lfigure__g(B) presents a polys‘ ‘con layer 220 encapsulated in a
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`A spacer portion 235 having an angle 290 that is less than 5°.
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`TEOS layer 230 with a spacer portion 235 adjacent to
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`In addition to providing stopping points or selectjvi
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`between materials, the
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`use of high selectivity etches to form sloped spacer portions is
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`e preferred practice
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`because the slo ed shape will result in good step coverage by the metal that is
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`deposited into it. The filling of Contact openings or gaps (i.e., gap fill) is an
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`important considera "on because it relates directly to the reliability of a device.
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`If an
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`opening is not complet
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`created, a subsequent corguctive material deposit can fill the gap which can lead to
`shorting. Sloped contact ope '
`because the transition between oped structures and openings is smooth compared
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`filled with a insulative material, for example, and a gap is
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`gs are easier to completely fill than boxy structures
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`to the abrupt transitions between b xy structures and openings. Because of concerns
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`for complete gap fill and good step co erage, industry preference is for sloped spacers
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`and planar deposition layers similar to t
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`t shown in Figure 2(b).
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`20
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`described abov will attack and erode a portion of the insulating spacer surrounding
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`the conducting po tion and adjacent to the contact region. Figure 3 presents a prior
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`art substrate with a
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`te and a contact region undergoing an RF sputter etch.
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`In
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`Figure 3, a gate oxide 3
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`is formed on a substrate 300 with a polysilicon layer 320
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`overlying the gate oxide 3
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`and an insulating layer, for example a TEOS layer 330
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`overlying the polysilicon laye 320. A distinct insulating layer, for example a silicon
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`nitride etch stop layer 340, overl
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`5 the TEOS layer 330 and this etch stop layer 340 is
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`covered by a third insulating layer, or example a BPTEOS blanket layer 350.
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`Adjacent to the gate is a contact regio 360. An etch of the silicon nitride etch stop
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`layer 340 with a high selectivity etch for
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`ilicon nitride relative to the underlying
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`TEOS layer material produced a gate with a loping or tapered spacer portion 370 of
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`TEOS material, illustrated in ghost lines. A su sequent RF sputter etch is utilized to
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`clean the contact region 360.
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`though brief and designed to clean the contact region, the RF sputter etch
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`sputter etch 380.
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`‘Bec
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`e the spacer portion 370 is sloping or diagonal, a significant
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`surface area portion of
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`spacer portion 370 is directly exposed to the high-energy
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`particles from the RF spurt
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`etch 380. Further, with sloping spacers, or spacers
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`having an angle relative to th
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`ubstrate surface of less than 85° the vertical portion
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`of the dielectric layer ((i.e., that p tion above the polysilicon gate) decreases much
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`less than the diagonal portion of the
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`acer.
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`In terms of measuring TEOS material
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`removal during the RF sputter etch in Fi
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`e 3, the difference between d] and d2 is
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`greater than the difference between 1:} and
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`. Thus, in conventional prior art self-
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`aligned contact structures, the diagonal thickne s of the TEOS spacer, rather than the
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`15
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`vertical thickness of the TEOS layer, determines
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`e minimum insulating layer
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`thickness for the gate.
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`For gate structures havin minimum diagonal insulative spacer portions of
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`500 A or less, the result of the sput
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`r etch 380 is that the sputter etch 380 laterally
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`erodes the diagonal portion of the TE
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`layer 370 adjacent to the contact region to a
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`point where the polysilicon 320 is no lon er isolated from the contact region 360 by
`In that case, there is a
`ort circuit through the underlying
`conductive material when the contact openin is filled with conductive material.
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`an insulating layer.
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`This result follows because the conventional RF
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`utter etch utilized for cleaning
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`the contact region results in an approximately 2006 O A loss of the spacer material.
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`75
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`Further, process margins generally require that the de 'ce spacer have a final
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`minimum thickness (after all etches, doping, and deposits of at least 500 A. Thus,
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`ent sensitivity for conventional small feature size structures,
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`to eliminate alig
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`than 500 13. requires that the pre-etch-stop—etch spacer be bigger or
`portion of mar
`thicker to yield a
`effective spacer after the etching processes. In such cases, the
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`structures must be
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`parated a distance such that the contact area opening is
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`sufficient enough for n effective contact. This spacing requirement directly limits
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`the number of structure that can be included on a device.
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`structures, particularly str
`tures utilizing self-aligned contacts, the width of contact
`openings is approximately 0. microns at the top of the planarized layer and 0.2
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`In small feature size
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`microns at the base of the conta t opening. Figure 3 indicates the difference in
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`contact opening widths for the sa
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`e contact in prior art structures. w1 represents
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`the width at the top of the planarize layer and wz represents the width at the base
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`of the contact opening. Further, an asp ct ratio can be defined as the height of a
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`20
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`structure (field oxide plus conductive lay
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`plus first insulative layer plus etch stop
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`layer, if any) relative to the width of the ba
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`of a contact opening (i.e., the distance
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`between adjacent spacers). Typical aspect ratio for self-aligned contact structures
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`target ratios of 1.0-2.4. This prior art range is not chievable with any device
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`25
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`less than 1000 A and preferably on the order of 500 A.
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`reliability. To achieve aspect ratios of 1.0-2.4 requir 5 minimum spacer portions of
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`s noted above, the
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`minimum spacer portions required for aspect ratios of 1. -2.4 cannot withstand the
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`sputter etch an will result in the exposure of the underlying polysilicon gate and
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`short circuiting w
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`the contact.
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`There is a need forcost effective structures wherein the individual devices
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`are as close together as possible while maintaining device reliability and an adequate
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`process margin and assuring complete gap fill. There is a need for a device and for a
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`process to manufacture such a device whereby there is provided a contact opening
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`with no alignment sensitivity relative to a gate electrode or other structure and
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`whereby the gate electrode does not fall within the contact opening but remains
`isolated from the contact opening by an insulating layer. The process must be
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`10
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`compatible with gate electrode insulating spacers of less than 500 15.. The device
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`resulting from the needed process should be capable of maintaining high quality
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`contacts between the conductive material in the contact region and the adjacent
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`conductive gate or other structure.
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`The invention relates to a process for minimizing lateral spacer erosion of an
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`insulating 1
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`er on an enclosed contact region is disclosed and a device including a
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`contact ope ' with a small alignment tolerance relative to a gate electrode or
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`5
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`other structure.
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`e process provides high quality contacts between a conductive
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`material in the con ct region and a device region, such as a source or drain, or some
`other layer or stru
`conductive layer on the semiconductor body adjacent a contact region. This is
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`e. The process comprises the well known step of forming a
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`followed by the forming
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`
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`a first insulating layer adjacent said conductive layer and
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`the contact region. A select cl area is masked with photoresist and the first
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`insulating layer and the cond ctive layer are etched to form a device structure, such
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`as a gate, adjacent the contact re ion. Next, insulating lateral spacers are added to
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`the device structure to isolate the onductive portion of the device. The insulating
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`spacers are etched so that the devic comprises an insulating layer overlying a
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`conductive layer with a lateral spacer ortion adjacent the contact region wherein
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`the spacer portion has a substantially re angular profile. A distinct insulating layer
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`or etch stop layer is then formed adjacent
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`the first insulating layer and over the
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`contact region. A third insulating layer or bl nket layer is then optionally formed
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`over the etch stop layer. The blanket layer may r may not be planarized.
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`20
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`If a blanket layer is included, an etchant is utilized to etch a contact opening
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`through the exposed portion of the blanket layer to the etch stop layer. Next, a
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`second etch or etch-stop etch is performed to remove the etch stop layer material
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`from the contact region. The etch-stop etch is also almost completely anisotropic,
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`meaning that the etchant etches in one clirection——in this case, vertically (or
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`perpendicular relative to the substrate surface) rather than horizontally. The etch
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`removes the etch stop insulating layer and retains the substantially rectangular
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`lateral spacer portion of the first insulating layer. The anisotropic etch etches
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`primarily the exposed etch stop material that lies normal to the direction of the etch.
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`Thus, the etch removes the etch stop material covering the area of the contact
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`5
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`region but does not significantly etch the etch stop material adjacent to the spacer(s).
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`The etch stop layer on the spacer adds dielectric thickness between the conductive
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`layer and any contacting conductor.
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`In general, the etching conditions utilized for
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`the etch-stop etch have a low selectivity for etching the etch stop layer compared to
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`the underlying insulating material.
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`10
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`The etch-stop etch may be followed by a sputter etch to clean the contact
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`region. Unlike prior art processes whereby the sputter etch erodes the underlying
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`sloping lateral spacer portion of the first insulating layer adjacent to the conducting
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`layer, the sputter etch does not significantly erode the substantially rectangular
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`lateral spacer of the first insulating layer, thus allowing the conductive layer of the
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`device structure to remain completely isolated or insulated by a spacer comprised of
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`the first insulating layer and some etch stop layer material.
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`The structure contemplated by the invention is an effective device for small
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`feature size structures, particularly self—aligned contacts. The structure consists of
`first and second conducting layers spaced apart by a region with an area defined in
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`20
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`the substrate; an insulating layer encapsulating each conductive layer, wherein the
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`insulating layer includes lateral spacer portions; and an etch stop layer adjacent the
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`insulating layer and over the first and second conducting layers. The invention
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`contemplates that the structure region has a first width between the first and second
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`conducting layers, and a second width between the lateral spacer portions of the
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`insulating layer adjacent to the first and second conducting layers, wherein the
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`region has an aspect ratio of 1.0-2.4. The aspect ratio is defined as the height of the
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`apparatus relative to the second width of the region. Thus, the invention
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`contemplates larger contact openings for effective contacts, reduced device feature
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`size, and increased device density, while maintaining aspect ratios similar to larger,
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`less dense devices in the prior art. The invention further contemplates that the
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`structure has a minimum insulating layer thickness of 400 A and that this
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`minimum thickness is determined by the thickness of the insulating layer deposited
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`vertically on the structure.
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`The device is capable of maintaining high quality, reliable contacts between
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`the conductive material in the contact region and the underlying device region,
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`10
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`such as a source or drain, or some other layer or structure. The device contemplates
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`minimum contact ‘opening base widths of 0.2 microns and minimum Contact
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`opening widths of 0.5 microns when measured from the top of a planarized layer,
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`and aspect ratios (i.e., height of structure including the etch stop layer relative to the
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`width of the base of a contact opening between the spacers) on the order of 1.0-2.4.
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`Additional features and benefits of the invention will become apparent from
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`the detailed description, figures, and claims set forth below.
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`The features, aspects, and advantages of the present invention will become
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`more thoroughly apparent from the following detailed description, appended
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`claims, and accompanying drawings in Which:
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`566!
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`e 1 is a planar view of a self-aligned contact to diffusion. Figure 1(A) is a
`Fi
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`planar top vi
`of a self-aligned contact. Figure 1(B) is a crosssecfional planar side
`view of a self-ah
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`1(C) is a cross-secti
`al planar side view of a self-aligned contact to diffusion
`through line 1(C) of Fi ure MA).
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`opening formation. Figure 2(
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`Figure 2 is a cross—se tional side View of the formation of a prior art contact
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`illustrates a high selectivity etch of an etch stop
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`ustrates the results of that etch.
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` insulating layer, and Figure 2(B}
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`15
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`Figure 3 is a cross-sectional sid view of the formation of a prior art contact
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`opening formation during a sputter clea ‘ng etch.
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`Figure 3 is a cro
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`sectional view of an example of a semiconductor device
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`during fabrication upon
`
`hich the invention may be practiced.
`
`Figure 4 presents a cross-sectional planar side view of the preparation of a
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`series of gates on a semiconductor substrate surface.
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`Figure 4(A) illustrates a cross-sectional planar side view of an insulating layer
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`20
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`adjacent to a conducting layer, both layers overlying two diffusion regions.
`
`Figure 4(B) illustrates a cross-sectional planar side view of a series of gates
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`consisting of insulating material adjacent conducting material.
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`Figure 4(C) illustrates a cross~sectional planar side view of the deposition of
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`additional insulating material over the series of gates, the additional insulating
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`material to be used for the formation of spacer portions adjacent the contact or
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`diffusion regions.
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`5
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`Figure 4(D) illustrates a cross-sectional planar side view of a series of gates
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`completely encapsulated in insulating material wherein the spacers of the
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`insulating material adjacent the contact or diffusion regions have substantially
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`rectangular profiles.
`
`B) illustrates a cross-sectional planar side view of a series of gates
`Figure
`p,t(\>
`10
`encapsulated wit
`'nsu.lating material and an insulating etch stop layer overlying_
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` the insulating materia
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`
`
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`Figure 4(F) illustrates a ross-sectional planar side view of a series of gates
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`encapsulated with insulating rnat
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`"al and an insulating etch stop layer overlying
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`the insulating material, wherein the cl usion region is implanted to include a
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`15
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`silicide.
`
`Figure 4(G) illustrates a cross—sectional planar side view of a series of gates
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`encapsulated with insulating material, an etch stop layer overlying the insulating
`
`material, and a distinct planarized insulating layer overlying the etch stop layer.
`
`Figure 4(H) illustrates a cross-sectional planar side view of a series of gates
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`20
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`encapsulated with insulating material, an etch stop layer overlying the insulating
`
`material, a distinct planarized insulating blanket layer overlying the etch stop layer,
`
`and a photoresist patterning layer deposited over the blanket layer.
`
`Figure 4(1) illustrates a cros -sectional planar side view of a series of gates
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`M9“ ;encapsulated with insulating mate
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`1, an etch stop layer overlying the insulating
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`material, a dis
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`ct planarized insulating blanket layer overlying the etch stop layer,
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`and contact openin
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`etch through the .blanket layer above the diffusion region.
`
` moss-sectional planar side view of a series of gates
`encapsulated with insulating
`terial, an etch stop layer overlying the insulating
`
`5 material, a distinct planarized ins
`
`ting blanket layer overlying the etch stop layer,
`
`and a contact opening to a diffusion r
`
`‘on and a second contact opening through
`
`the blanket layer but separated from the
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`' fusion region by an etch stop layer.
`
`Figure 4(K) illustrates a close-up cross-sectional planar side view of a circled
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`portion of Figure 4(]