U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
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`DOCKET NO.: 0107131-00351US3
`Filed on behalf of Intel Corporation
`By: Grant K. Rowan, Reg. No. 41,278
`Yung-Hoon Ha, Reg. No. 56,368
`Wilmer Cutler Pickering Hale and Dorr LLP
`1875 Pennsylvania Ave., NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: Grant.Rowan@wilmerhale.com
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` Yung-Hoon.Ha@wilmerhale.com
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
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`
`
`
`
`INTEL CORPORATION
`Petitioner
`
`v.
`
`DSS Technology Management, Inc.
`Patent Owner
`
`Case IPR2016-00287
`
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,784,552
`CHALLENGING CLAIMS 1-7
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`TABLE OF CONTENTS
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`Introduction ......................................................................................................... 1 
`I. 
`II.  Mandatory Notices .............................................................................................. 6 
`A.  Real Party-in-Interest .................................................................................... 6 
`B.  Related Matters .............................................................................................. 7 
`C.  Counsel .......................................................................................................... 7 
`D.  Service Information ....................................................................................... 7 
`III.  Certification of Grounds for Standing .............................................................. 8 
`IV.  Overview of Challenge and Relief Requested ................................................. 8 
`A.  Prior Art Patents and Printed Publications .................................................... 8 
`B.  Grounds for Challenge .................................................................................. 9 
`V.  Technology Background ..................................................................................... 9 
`A.  Basic Structure of Transistors ....................................................................... 9 
`B.  Overview of Transistor Fabrication ............................................................ 11 
`1. 
`Formation of Transistor Components ...................................................... 11 
`2. 
`Etching to Create Contact Openings ........................................................ 12 
`VI.  Overview of the ’552 Patent ........................................................................... 16 
`A.  The Alleged Problem in the Art .................................................................. 16 
`B.  The Alleged ’552 Patent Invention ............................................................. 19 
`C. 
`Prosecution History ..................................................................................... 21 
`VII.  Overview of the Primary Prior Art References .............................................. 24 
`A.  Summary of the Prior Art ............................................................................ 24 
`B.  Overview of Heath (Ex. 1003) .................................................................... 25 
`C.  Overview of Supporting References ........................................................... 27 
`1.  Hawley (Ex. 1004) ................................................................................... 27 
`2.  Overview of Chappell (Ex. 1005) ............................................................ 27 
`3.  Overview of Dennison (Ex. 1006) ........................................................... 28 
`VIII.  Claim Construction ...................................................................................... 29 
`IX.  Level of Ordinary Skill In The Art ................................................................. 35 
`X.  Specific Grounds for Petition ............................................................................ 35 
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`A.  Ground 1: Claims 1-2, 4-7 are Anticipated by Heath ................................ 36 
`1. 
`Independent Claim 1 ................................................................................ 36 
`2.  Claim 2: “The semiconductor apparatus of claim 1 wherein said etch
`stop material comprises silicon nitride” ............................................................ 43 
`3.  Claim 4: “The structure of claim 1, wherein the insulating spacer has a
`surface portion in the contact region without overlaying etch stop material” .. 43 
`4.  Claim 5: “The structure of claim 4, wherein the insulating spacer surface
`portion without overlying etch stop material comprises an insulating spacer
`surface portion most distant from said substrate” ............................................. 44 
`5.  Claim 6: “The structure of claim 1, further comprising a second
`insulating layer on the etch stop layer and over the conductive layer” ............ 45 
`6.  Claim 7: “The structure of claim 6, further comprising a second
`conductive material in the contact region” ....................................................... 46 
`B.  Ground 2: Claim 3 Would Have Been Obvious Over Heath in View of
`Hawley and Chappell ............................................................................................ 47 
`1.  Claim 3: “The semiconductor apparatus of claim 1 wherein said etch
`stop material comprises silicon dioxide” .......................................................... 47 
`C.  Ground 3: Claims 1-2, 4-7 Would Have Been Obvious Over Heath in
`View of Dennison ................................................................................................. 50 
`1.  Heath, in combination with Dennison, renders the claims obvious under
`an overly narrow construction of the “angle” limitation—e.g., limiting it to a
`particular portion of the “side” of the insulating spacer—recited in claim 1
`(element 1(f)) .................................................................................................... 50 
`D.  Ground 4: Claim 3 Would Have Been Obvious Over Heath in View of
`Dennison, Hawley and Chappell .......................................................................... 60 
`XI.  Conclusion ...................................................................................................... 60 
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`Intel Corporation (“Intel”) respectfully requests Inter Partes Review of
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`claims 1-7 of U.S. Patent No. 6,784,552 (the “’552 patent”) (Ex. 1001) pursuant to
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`35 U.S.C. §§ 311-19 and 37 C.F.R. § 42.1 et seq.
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`I. INTRODUCTION
`The ’552 patent purports to provide a novel approach to semiconductor
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`manufacturing but instead merely duplicates a well-known technique patented by
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`inventor Barbara Heath nearly a decade before the alleged invention.
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`The ’552 patent is directed to the manufacture of transistors used in
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`semiconductor products such as microprocessors and memory. Transistors are one
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`of the basic building blocks of semiconductors—they are microscopic switches
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`that turn on and off to allow semiconductors to process data. Transistors include
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`various components and “contacts” that are used to connect a component of one
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`transistor to a component of another transistor. The ’552 patent is directed to a
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`particular technique for the formation of “contact openings”—openings created
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`through the layers of a semiconductor device so that a contact can be formed
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`between components.
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`The patent asserts that prior art techniques for forming these contact
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`openings resulted in an unacceptably high risk of creating unintentional
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`connections (and thus a short-circuit) between the contacts and nearby components.
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`Specifically, the patent explains that prior art techniques used non-conducting
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`“sidewall spacers” between contact openings and nearby components to prevent
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`unintentional connections. But the patent notes that during the process of creating
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`the openings, these sidewall spacers could become sloped. According to the patent,
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`a sloped sidewall spacer is particularly susceptible to erosion in subsequent
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`fabrication steps such that it can be worn down to the point that the contact
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`opening and a nearby component can make an unintentional connection:
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`’552 patent, Fig. 2(B)
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`’552 patent, Fig. 3
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`In Fig. 2(B), described as “Prior Art,” the patent shows a contact opening
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`270, a sidewall spacer 235 that has become sloped as a result of the creation of the
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`contact opening, and a nearby component 220. In Fig. 3, also described as “Prior
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`Art,” the patent shows that in a subsequent step, the sloped sidewall spacer has
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`become eroded from the dotted line (370) to the solid line, such that nearby
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`component 320 (a “gate”) is now exposed to the contact opening. According to the
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`patent, this unintentional connection between the component and the contact
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`opening would result in a short-circuit and thus a non-functioning transistor.
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`The patent purports to solve this problem by using a process that prevents
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`the sidewall spacer from becoming sloped and instead retains the spacer’s
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`“substantially rectangular” shape. ’552 at 13:4-10. Specifically, the patent
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`describes using an admittedly known type of “anisotropic etchant”—a material
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`used to “etch” or create openings in the fabrication process—that etches only
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`vertically relative to the substrate surface. According to the patent, the use of such
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`an etchant avoids the problem of creating a sloped sidewall spacer and instead
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`“retains the substantially rectangular lateral spacer portion” of the spacer. ’552 at
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`7:45-51 (“…The etch removes the etch stop insulating layer and retains the
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`substantially rectangular lateral spacer portion of the first insulating layer.”).1
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`’552 patent, Fig. 4(J)
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`’552 patent, Fig. 4(K)
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`As shown in the figures above, after the use of the etchant, the sidewall
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`spacer (lateral spacer portion 420) has sides that are vertical relative to the
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`substrate surface (i.e., the spacer retains its “substantially rectangular”
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`shape). ’552 at 12:54-13:10. As a result, according to the patent, the sidewall
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`spacer is less susceptible to erosion in subsequent fabrication steps and thus the
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`1 All emphasis and annotations added unless otherwise indicated.
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`risk of unintentional connection (and short-circuit) with nearby components is
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`reduced. ’552 at 7:62-8:3 (“Unlike prior art processes . . . the sputter etch does not
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`significantly erode the substantially rectangular lateral spacer of the first insulating
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`layer, thus allowing the conductive layer of the device structure to remain
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`completely isolated or insulated by a spacer . . .”). The patent thus claims to solve
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`the problem of a short-circuit between a contact and nearby component by using a
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`process that “retains the substantially rectangular” shape of a sidewall spacer. ’552
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`at 13:9-10.
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`But well before December 1995—the ’552 patent’s claimed priority date2—
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`others had already solved precisely the same problem in precisely the same way.
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`For example, U.S. Patent No. 4,686,000 (“Heath”) (Ex. 1003)—filed nearly ten
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`years before the parent application for the ’552 patent was filed—describes the use
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`of a process that retains the substantially rectangular shape of a sidewall spacer
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`during the formation of a contact opening in a transistor. Heath at Abstract (“An
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`improved process for self-aligned contact window formation in an integrated
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`circuit leaves a ‘Stick’ of etch stop on vertical sidewall surfaces to be protected.”).
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`2 The prior assignee claimed a priority date prior to April 21, 1995 during
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`prosecution of the parent application, U.S. Patent No. 6,066,555 (the “’555
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`patent”). ’555 Decl. Under 37 C.F.R. 1.131, Feb. 25, 1999 (Ex. 1011) at 3. In any
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`case, the cited references are prior art and invalidate the ’552 patent.
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`Specifically, just like the ’552 patent, Heath describes the need to retain the
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`“vertical” sides of a lateral spacer in order to avoid unintentional connection (and
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`thus a short-circuit) with nearby components. Heath at 11:1-15 (explaining that a
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`“substantially vertical” edge protects against erosion that could cause a short
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`circuit). And just like the ’552 patent, Heath describes etching “anisotropic[ally]”
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`in a vertical direction to maintain the substantially vertical sidewalls of a lateral
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`spacer. Heath at 5:25-35 (“Summary of the Invention[:] These and several other
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`objects and advantages are obtained by providing a self-aligned contact process
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`which involves establishing gate electrodes and/or isolation edges which are
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`substantially vertical with respect to the substrate surface …”); 10:2-11 (“[T]he
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`part of layer 10 between dashed lines 56 is removed leaving a vertical stick 10a of
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`layer 10. . . . Some oxide 24 will remain on the top of gate electrode 16 even after
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`the etch exposes the source/drain region 20 within the contact window, and
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`because the nitride removal is anisotropic [i.e., it can etch vertically], the ‘stick’
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`10a will remain on the side, so no short to electrode 16 can occur.”). This is
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`shown in Fig. 8C of Heath below:
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`Fig. 8C shows a contact opening (pink) that has been formed by etching
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`anisotropically in the downward direction towards the substrate. The anisotropic
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`downward etch results in a vertical etch stop layer 10a (purple) adjacent to a
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`vertical (i.e., substantially rectangular) insulating spacer 16a (brown). Heath at
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`10:1-47.
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`Heath thus discloses the allegedly novel concept of the ’552 patent. Indeed,
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`a side-by-side comparison of the ’552 and Heath figures shows that they describe
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`structures that are identical in all relevant respects:
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`’552 patent, Fig. 4(L)
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`Heath, Fig. 8C
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`As shown, both include: a contact opening (pink); a nearby component (a
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`gate electrode shown in blue) that needs to remain isolated from the opening; and
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`sidewall spacers (brown) that have retained their “substantially rectangular” shape
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`(i.e., both have sides that are vertical relative to the substrate surface).
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`Accordingly, Heath—which was not before the Patent Office during
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`prosecution of the ’552 patent—alone, or in combination with other prior art
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`described below, anticipates and/or renders obvious claims 1-7 of the ’552 patent.
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`II. MANDATORY NOTICES
`A. Real Party-in-Interest
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`Intel Corporation (“Petitioner”) is the real party-in-interest.
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`B. Related Matters
`The ’552 patent is currently being asserted by the Patent Owner in the
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`following cases: DSS Tech. Mgmt., Inc. v. Intel Corp. et al., Civil Action No.
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`6:15-CV-130-JRG (E.D. Tex. 2015); DSS Tech. Mgmt., Inc. v. Samsung
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`Electronics Co., Ltd. et al., 15-cv-690 (E.D. Tex. 2015); DSS Tech. Mgmt., Inc. v.
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`SK Hynix, Inc. et al., 15-cv-691 (E.D. Tex. 2015); and DSS Tech. Mgmt., Inc. v.
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`Qualcomm Inc., 15-cv-692 (E.D. Tex. 2015). The Petitioner is filing a separate
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`inter partes review petition for claims 8-12 of the ’552 patent. Additionally, the
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`Patent Owner is suing Petitioner and other parties under U.S. Patent No. 5,965,924.
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`The Petitioner is filing separate inter partes review petitions for the ’924 patent.
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`The below-listed claims of the ’552 patent are presently the subject of a petition for
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`inter partes review styled SK hynix Inc. et al. v. DSS Tech. Mgm’t, Inc., filed
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`November 12, 2015 and assigned Case No. IPR2016-00192.
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`C. Counsel
`Lead Counsel: Grant K. Rowan (Registration No. 41,278). Backup Counsel:
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`Yung-Hoon Ha (Registration No. 56,368), Michael J. Summersgill (pro hac vice to
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`be requested), Louis W. Tompros (pro hac vice to be requested).
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`D. Service Information
`E-mail: Grant.Rowan@wilmerhale.com; Yung-Hoon. Ha@wilmerhale.com
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`Post and hand delivery: Wilmer, Cutler, Pickering, Hale and Dorr, LLP
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`1875 Pennsylvania Ave., NW
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`Washington, DC 20006
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`Telephone: 202-663-6000 Fax: 202-663-6363
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`III. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
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`review is sought is available for inter partes review and that Petitioner is not
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`barred or estopped from requesting an inter partes review challenging the patent
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`claims on the grounds identified in this Petition.
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`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
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`claims 1-7 of U.S. Patent No. 6,784,552 (Ex. 1001).
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`A. Prior Art Patents and Printed Publications
`The ’552 patent was filed March 31, 2000 and is a divisional of U.S. Patent
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`Appl. No. 08/577,751, filed on December 22, 1995, now U.S. Patent No. 6,066,555
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`(the “’555 patent”) (Ex. 1007). Petitioner relies upon the patents and printed
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`publications listed in the Table of Exhibits, including:
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`1. Heath, U.S. Patent No. 4,686,000 (“Heath”) (Ex. 1003), which is prior
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`art under at least 35 U.S.C. §§ 102(a) and (b).3
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`3 Because the ’552 patent issued prior to the AIA, Petitioner has used the pre-AIA
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`statutory framework to refer to the prior art.
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`2. European Patent Publ. No. 0592078 (“Hawley”) (Ex. 1004), which is
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`prior art under at least 35 U.S.C. §§ 102(a) and (b).
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`3. U.S. Patent No. 5,541,427 (“Chappell”) (Ex. 1005), which is prior art
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`under at least 35 U.S.C. § 102(e).
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`4. U.S. Patent No. 5,338,700 (“Dennison”) (Ex. 1006), which is prior art
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`under at least 35 U.S.C. §§ 102(a) and (b).
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`B. Grounds for Challenge
`Petitioner requests cancellation of claims 1-7 of the ’552 patent (“challenged
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`claims”) as unpatentable under 35 U.S.C. §§ 102 and/or 103. This Petition,
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`supported by the declaration of John C. Bravman, Ph.D. (“Decl.”) (Ex. 1002),
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`demonstrates that there is a reasonable likelihood that Petitioner will prevail with
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`respect to at least one challenged claim and that each challenged claim is not
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`patentable. See 35 U.S.C. § 314(a). The grounds for the petition are as follows:
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`Ground 1: claims 1-2, 4-7 are anticipated by Heath; Ground 2: claim 3 would
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`have been obvious over Heath in view of Hawley and Chappell; Ground 3: claims
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`1-2, 4-7 would have been obvious over Heath in view of Dennison; and Ground 4:
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`claim 3 would have been obvious over Heath in view of Dennison, Hawley and
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`Chappell.
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`V. TECHNOLOGY BACKGROUND
`A. Basic Structure of Transistors
`The ’552 patent relates to the field of semiconductor integrated circuit
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`manufacturing. Semiconductor integrated circuits, such as microprocessors and
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`computer memory, are typically made up of hundreds of millions (and in some
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`cases) billions of microscopic structures called transistors. Transistors act as
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`microscopic switches that turn on and off at extraordinarily high rates to enable
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`aggregations of transistors (and other components) to process data. Decl. ¶ 27.
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`As shown in the figure below, transistors typically include three primary
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`“electrodes” or “terminals”—a gate, a source, and a drain—embedded in or on a
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`dielectric substrate and surrounded by other dielectric materials:
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`The source and drain regions (also referred to as “diffusion regions”) are transistor
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`components that emit (source) and receive (drain) current when the transistor is
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`“on.” The gate electrode is a terminal that can have a voltage applied to it that in
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`turn causes a current to flow between the source and drain. Decl. ¶¶ 28-29.
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`The gate, source and drain of a transistor typically need to be connected to
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`other components to form an electrical circuit. The ’552 patent refers to the
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`components used to make these connections as “contacts.” Contacts consist of one
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`or more conducting materials (e.g., a metal) that allow current to flow between
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`transistor components. In many cases, it is important to maintain electrical
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`isolation between contacts and other nearby components (such as a gate electrode)
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`so that current that is supposed to flow to other parts of the circuit does not instead
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`flow to these nearby components (e.g., the gate). As described in more detail
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`below, devices called sidewall spacers can be formed between the contact and the
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`nearby components to maintain this electrical isolation. Decl. ¶ 30.
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`B. Overview of Transistor Fabrication
`1. Formation of Transistor Components
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`Transistor fabrication typically starts with a silicon substrate. In typical
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`planar transistors, source and drain regions (“diffusion regions”) are created by
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`implanting regions of the substrate with ions (charged atomic particles) of different
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`materials—called “dopants” or “impurities”—to make those regions conductive.
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`(Once implanted the ions become neutral atoms.) This process—referred to as
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`“doping” because it dopes the silicon substrate with atomic particles that have
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`additional charge carriers—is shown below:
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`Structures can then be formed above the substrate by depositing layers of
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`other materials onto the substrate. A gate electrode, for example, is formed by first
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`growing or depositing a “gate oxide” (an insulator) on the substrate followed by
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`depositing a conductive material (metal or polysilicon) on top of the gate oxide.
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`The conductive material acts as the gate and the gate oxide creates a layer of
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`isolation between the gate and the source/drain regions (“S/D regions” or
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`“diffusion regions”). Decl. ¶¶ 31-32.
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`Insulating materials may then be deposited around and over the gate and the
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`S/D regions to maintain electrical isolation where desired. Sidewall spacers, for
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`instance, can be formed on each side of the gate electrode as shown below:
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`As was known as of the time of the alleged ’552 invention, such sidewall spacers
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`help to prevent direct electrical contact between the gate electrode and nearby
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`components and thus help to prevent short-circuits. Decl. ¶ 33.
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`2. Etching to Create Contact Openings
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`Gate electrodes and S/D regions of transistors must typically be connected to
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`other components in the semiconductor device. These connections are made using
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`“contacts”—connections between components that allow electrical signals to pass
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`between the components. Contacts are formed by creating openings through the
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`layers of a semiconductor device (i.e. “contact openings”) and then filling the
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`openings with a conductive material. Fig. 4(J) of the ’552 patent shows a fully-
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`formed contact opening 460, while Fig. 4(L) shows the contact opening after it has
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`been filled with a conductive material 480 (pink) to form the contact:
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`The process of removing material to create contact openings is known as “etching.”
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`To perform etching, semiconductor manufacturers use “etchants.” As was known
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`at the time of the alleged ’552 invention, etchants have various known properties
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`that can be chosen depending on the type of etching desired. Decl. ¶ 34.
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`Etching can be performed “isotropically” or “anisotropically.” An isotropic
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`etch will etch material in all directions (e.g., both vertically and horizontally with
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`respect to the substrate surface). An anisotropic etch will etch material more
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`effectively in a particular direction (e.g., vertically but not horizontally relative to
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`the substrate surface). Decl. ¶ 35.
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`Etching can also be “wet” or “dry.” Wet etching refers to etching in which
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`the etchant is a liquid, which will dissolve through a particular material to create a
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`contact opening. Dry etching—sometimes based on the physical process known as
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`“sputtering”—is etching away material by using a gas or plasma to bombard the
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`material to be etched with ions. Generally, wet etching is used to perform isotropic
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`etching (i.e., all directions) and dry etching is used to perform anisotropic etching
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
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`(i.e., one direction). Decl. ¶ 36.
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`Etchants can also be “selective” or “non-selective.” The “selectivity” of an
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`etchant refers to its effectiveness at etching away one type of material versus
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`another type of material. A highly-selective etchant relative to a particular material
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`will etch away that material at a much faster rate than a different type of material.
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`A non-selective etchant will etch away both types of materials at approximately the
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`same rate. See, e.g., ’552 at 2:12-21; see also id. at 4:66-5:2. The same etchant
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`can behave as either a selective or non-selective etchant depending on the material
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`being etched, the processing conditions, and other parameters of the etching
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`process. Decl. ¶ 37. For example, an etchant that is selective as to one material
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`can be non-selective as to another. Id.
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`As was well-known at the time of the ’552 patent, contact openings of
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`various shapes and sizes can be created depending on the etching method chosen.
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`As shown in Figs. 4(H) and 4(I) of the ’552 patent, the etchant removes material to
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`create an “opening” in the layers of a semiconductor device. Fig. 4(H) show a
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`transistor structure with insulating material 450 (green) covering the diffusion
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`regions 445 (orange). Fig. 4(I) shows the same structure after the insulating
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`material has been etched to create contact openings 460 and 465 which extend
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`down towards the diffusion regions:
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
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`Decl. ¶ 38.
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`As was also well known, “etch stop layers” (material 440 in Figs. 4(H) and
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`4(I)) can be used to avoid etching areas not intended to be removed. An etch stop
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`layer, as its name suggests, effectively stops an etchant from further eroding or
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`removing material once the etching process reaches the etch stop layer. Etch stop
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`layers are thus used to protect components (e.g., a gate electrode or S/D region) by
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`stopping the etchant before it reaches the protected component. Decl. ¶ 39.
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`The following figures, created by Dr. Bravman, illustrate the process. The
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`figure below (step 1) shows a diffusion region with an etch stop layer above it and
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`further covered by an insulating material:
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`Decl. ¶ 40.
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`As shown in the figure below (step 2), to make a contact opening down to the
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`Petition for Inter Partes Review
`diffusion region, an etchant is applied to the insulating material. The etchant
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`effectively etches away the insulating material but not the etch stop layer. As a
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`result, when the etchant reaches the etch stop layer, etching is stopped. In this way,
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`the etch stop layer prevents the etchant from etching into and damaging the
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`diffusion region:
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`Decl. ¶ 41.
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`As shown in the figure below (step 3), the etch stop layer can then be
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`removed by using a different (and usually more precise) etching process to
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`complete the contact opening down to the diffusion region:
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`Decl. ¶ 42.
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`VI. OVERVIEW OF THE ’552 PATENT
`A. The Alleged Problem in the Art
`The ’552 patent purports to describe an improved technique for forming
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`contact openings in transistors. The patent asserts that prior art techniques for
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`forming contact openings resulted in an unacceptably high risk of creating
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`unintentional connections (and thus a short-circuit) between the contacts and
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`nearby components. Specifically, according to the patent, the use of highly
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`selective etchants to create contact openings caused the sidewall spacers between a
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`contact opening and a nearby component (such as a gate electrode) to become
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`sloped. ’552 at 5:6-14 (“The properties of the highly selective etch of the
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`overlying etch stop layer 240 will transform a substantially rectangular spacer
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`into a sloped spacer.”); id. at 2:4-6, 2:39-41. This is shown in Fig. 2(B):
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`The figure, described as “Prior Art,” shows a contact opening 270, a sidewall
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`spacer 235, and a gate electrode 220 that needs to remain isolated from the contact
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`opening. As shown, the sidewall spacer has become “sloped.” ’552 at 5:6-14; see
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`also id. at 5:51-55; Decl. ¶ 43.
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`The patent then explains that, in subsequent fabrication steps, a sloped
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`sidewall is particularly susceptible to erosion such that it can be worn down to the
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`point that the contact opening and a nearby component (e.g., the gate electrode)
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`can come into unintentional contact. Specifically, the patent explains that, after the
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`U.S. Patent No. 6,784,552 Claims 1-7
`Petition for Inter Partes Review
`contact opening is formed, an additional etching step is usually performed to clean
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`the contact opening. ’552 at 5:55-56 (explaining that “RF sputter etch” is
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`performed). This final etching step—which is a dry etch performed using vertical
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`bombardment—can erode the remaining insulating material separating the gate
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`electrode from the contact opening. The patent explains that because the sidewall
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`spacer has become sloped, it is more directly exposed to the vertical bombardment
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`and thus more susceptible to erosion. ’552 at 5:59-6:1 (“The dynamics of the
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`sputter etch 380 are that it proceeds vertically, directing high-energy particles at
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`the contact region. . . . Because the spacer portion 370 is sloping or diagonal, a
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`significant surface area portion of the spacer portion 370 is directly exposed to
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`the high-energy particles from the RF sputter etch 380.”). This is shown in Fig.
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`3B:
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`As shown, as a result of this process, the sloped sidewall spacer has become further
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`eroded from the dotted line (370) to the solid line such that the gate electrode 320
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`is now exposed to the contact opening. ’552 at 6:14-19 (“[T]he result of the
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`sputter etch 380 is that the sputter etch 380 laterally erodes the diagonal portion of
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`U.S. Patent No. 6,784,552 Claims 1-7
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`the TEOS spacer portion 370 adjacent to the contact region to a point where the
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`polysilicon layer 320 [i.e., the gate electrode] is no longer isolated from the contact
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`region 360 by an insulating layer.”). According to the patent, such contact results
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`in a short-circuit and thus a non-functioning transistor. ’552 at 6:19-21; Decl. ¶ 44.
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`B. The Alleged ’552 Patent Invention
`The patent purports to solve this problem by using a process that prevents
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`the formation of a sloped spacer and instead retains the “substantially rectangular”
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`shape of the lateral spacer. ’552 at 11:48-49 (“[C]are is taken to etch the spacers
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`435 such that the spacers 435 have a substantially rectangular profile.”), 13:9-16
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`(“Of primary significance, the spacer portion 435 of the TEOS layer retains its
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`substantially rectangular profile. . . . The invention relates to these process
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`conditions as well as others that result in the retention of a boxy spacer.” (TEOS
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`is a common type of insulator used in integrated circuits)). Decl. ¶ 45.
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`The patent does not purport to have invented the use of sidewall spacers, the
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`use of anisotropic etchants to etch in a vertical direction, or the use of such
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`etchants to form contact openings. All of this was indisputably well-known. ’552
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`at 1:10-7:13 (Background). Instead, the patent claims as its novel concept the use
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`of a known etchant in such a way that retains the “substantially rectangular” shape
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`of the sidewall s