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`Unit 2815, at the United States Patent and Trademark cm
`on:
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`Date of anal
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`312 321 4 54¢ Jzggaflx
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`Paul E. Rauch. Ph.D. — Re .Nn. 38.591
`Name of applicant. assignee or
`Registered Rep
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`9
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` Signature
`Date of Signatu
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`9/
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`J1-‘T
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Our Case No, 10200112
`Cypress Ref. No. PM95012D
`
`In re Application of:
`
`James E. Nulty et al.
`Serial No. 09/540,610
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`Filing Date: March 31,2000
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`For
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`Structure Having Reduced Lateral
`Spacer Erosion
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`AMENDMENT AND RESPONSE AFTER FINAL
`
`Commissioner for Patents
`Washington, D.C. 20231
`
`Dear Madam:
`
`Responsive to the Final Office Action mailed January 9, 2002, Applicants
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`respectfully request reconsideration in light of the following amendments and remarks.
`
`IN THE CLAIMS
`Please amend claims 25-27' and 34 as follows.
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`‘Q3’
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`‘\§\» ®®
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`Received lrom < 312 321 4299 > at 5l20l02 3:25:23 PM [Easlem Daylight Time]
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`25. ('i' be Amended) The semiconductor apparatus of claim 27 wherein said etch stop
` 26. (Twice mended) The semiconductor apparatus of claim 27 wherein said etch stop
`01;? 27.(Axtended)Astructure,comprising:
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`(
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`(b)
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`a conductive layer disposed over a substrate;
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`first insulating layer on the conductive layer;
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`(0)
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`contact region in said first insulating layer;
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`(cl) at east one insulating spacer in the contact region adjacent to the first insulating
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`layer; and
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`(e) an
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`tch stop material over said first
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`insulating layer and adjacent to the
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`the etch stop material being a different material from the insulating
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`Insulating space
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`34. (Twice mended) A stmcture, comprising:
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`.
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`(a) a rst electncaliy conductive material formed in and/or on a surface of a
`substrate;
`ct opening in a region adjacentto a second electrically conductive
`_
`(b) a co
`material fonried o the substrate;
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`
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`conductive material.
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`453*
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`C/\
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`material omprises silicon nitride.
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`material com rises silicon dioxide.
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`FAQS
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`SUPPORT FOR AMENDMENT
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`The amendments of claims 27 and 34 are supported on page 23. In. 11-12. Claims
`25-26 have been amended for clarity. Appendix A, attached herewith.,ls a marked-up
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`version of the changes made to the claims. No new matter has been added. Claims 25-
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`39 are pending.
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`REMARKS
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`Applicants thank the Examiner for the helpful telephone discussion‘ on March 14,
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`2002. During this discussion. Applicants noted that the claimed invention specifies that the
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`etch stop material is a different material than the insulating spacer.
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`The present invention relates to a semiconductor device with well defined contact
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`openings. The current practice with respect to forrnlng contact openings during the
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`fabrication of semiconductor devices. particularly self aligned contact openings, is to use
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`etchants with high selectivity to protect underlying regions. However. the properties of a
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`highly selective etch of the overlying etch stop layer can transform a substantially
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`rectangular spacer adjacent to the contact region into a sloped spacer. Before the
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`conductive material is added to the contact opening. the opening is cleaned with a sputter
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`etch whlchcan erode a portion ofthe sloped insulating spacer. Thus. in conventional self-
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`aligned contact structures. the diagonal thickness of the spacer. rather than the vertical
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`thickness of the insulating layer. determines the minimum insulating layer thickness for the
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`gate. Sloping spacers limit the number of structures that can be Included on a device.
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`The present invention avoids this problem by retaining the substantially rectangular
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`profile of the insulating spacers. The present invention includes at least one insulating
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`spacer in the contact region and an etch stop material over the first insulating layer and
`adjacent to the insulating spacer. the etch stop material being different from the insulating
`spacen
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`Reiectiogs under 35; U.S.C. § ]Q2 and 10;
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`The rejection of the claims under 35 U.S.C. § 102 and 103 over Dennison et al.
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`(US. Pat. No. 5.338.700). either alone or in combination with Gonzalez (U.S. Pat. No.
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`5.234,856),Vis respectfully traversed. Qennlson at at, describes a barrier layer rather
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`Recelvedirom<3123214299>at 5i2nill2 3:26:23 PM [Eastern Daylight Time]
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`MRY-28-2882
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`than an etch stop material, and does not suggest that it is a different material from the
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`insulating spacer.
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`Dennison et ai, describes a method of forming a bit line over a capacitor array of
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`memory cells. The semiconductor wafer ofQ has an array of electrically
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`isolated word lines 12, 14 and 16 having insulating spacers and caps 18 (Fiure 1).
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`The spacers and caps 18 preferably comprise an lnsulative nitride, such as Si3N.«, (col.
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`3, in. 33-34). The reference further states "a thin layer 20 of Si3N.;, is provided atop the
`wafer to function as a diffusion barrier" (col. 3, in. 34-36). Dennisgn et al. does not
`teach or suggest that the spacers and caps 18 and diffusion barrier 20 are different
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`materials. On the contrary, the reference specifically teaches that 18 and 20 are the
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`same material. Furthermore. since 20 is a diffusion barrier. not an etch stop, there
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`would be no reason to use a material distinct from the spacer 18.
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`_
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`Gonzalez describes a dynamic random access memory cell having a stacked-
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`trench capacitor that is "resistant to alpha particle generated soft errors. Gonzalez only
`describes silicon dioxide in spacers 31 (col. 5, in. 10-12).
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`The claimed invention includes an etch stop material that is different from the
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`insulating spacer. The barrier layer of Dennison et ai. is described as Si;,N4. the same
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`material as the spacers. Furthermore, there is no suggestion that they be formed from
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`different materials since the barrier layer is not intended to function as an etch stop
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`layer. The combination with Qongalez does not correct this deficiency.
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`Therefore. Applicants submit that Dennison et al., either alone or in combination
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`with Ggnzalez. does not anticipate nor make obvious the claimed invention. Withdrawal
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`of the rejection of the claims on these grounds is respectfully requested.
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`
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`Paul E. Rauch. Ph.D.
`Registration No. 38.591
`Attorney for Applicants
`
`BRlNKS HOFER GILSON & Ll0NE
`P.O. BOX 10395
`CHICAGO, ILLINOIS 80610
`(312) 321-4200
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`Received from < 312 321 4299 > at 5l2nlii2 3:25:23 PM [Eastern Dayliglit Time]
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`4
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`May-23-22];
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`FREE
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`APPENDIX A
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`25. (Twice Amended) The semiconductor apparatus of claim 27 wherein said etch stop
`' [layer] material comprises silicon nitride.
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`26. (Twice Amended) The semiconductor apparatus of claim 27 wherein said etch stop
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`[layer] material comprises silicon dioxide.
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`2?. (Amended) A structure, comprising:
`
`(a) a conductive layer disposed over a substrate;
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`(b) a first insulating layer on the conductive layer;
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`(c) a contact region in said first insulating layer;
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`b
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`(d) at least one insulating spacer in the contact region adjacent to the first insulating
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`layer; and
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`7
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`(e) an etch stop material over said first
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`insulating layer and adjacent to the
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`insulating spacer.
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`the etch stop material being 3 [distinct] giflerent material from the
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`insulating spacer.
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`34. (Twice amended) A structure. comprising:
`
`(a) a first electrically conductive mterial formed in and/or on a surface of a
`substrate;
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`(b) a contact opening in
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`region adjacent to a second electrically conductive
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`material formed on the substrate;
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`(c) an electrically insulative spacer in the contact opening adjacent to the second
`electrically conductive material;
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`(d) an etch stop material over the electrically insulative spacer and the first and
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`second electrically conductive materials, the etch stop material being _a [distinct] different
`matefil from the insuiative spacer.
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`(e) a blanket layer over the etch stop material; and
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`(f) an opening through a firet part of the etch stop material to the first electrically
`conductive material.
`'
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`Received from < 312 321 4299 > at 5i20i02 3:26:23 PM [Eastern Daylight lime]