UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`INTEL CORPORATION
`Petitioner
`
`v.
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`DSS Technology Management, Inc.
`Patent Owner
`
`U.S. Patent No. 6,784,552
`Claims 1-7
`____________________________________________
`
`Case IPR2016-00287
`____________________________________________
`
`DECLARATION OF JOHN C. BRAVMAN, PH.D.
`ON BEHALF OF PETITIONER
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`
`
`INTEL 1002
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`I. 
`
`TABLE OF CONTENTS
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`Relevant Law ................................................................................................... 8 
`A. 
`Claim Construction ............................................................................... 8 
`B. 
`Anticipation ........................................................................................... 9 
`C. 
`Obviousness ........................................................................................... 9 
`Summary of Opinions .................................................................................... 11 
`II. 
`III.  Brief Description of the Technology ............................................................. 11 
`A. 
`Basic Structure of Transistors ............................................................. 11 
`B. 
`Overview of Transistor Fabrication .................................................... 13 
`1.  Formation of Transistor Components ................................................. 13 
`2.  Etching to Create Contact Openings ................................................... 14 
`IV.  Overview of The ’552 Patent ......................................................................... 19 
`A. 
`The Alleged Problem in the Art .......................................................... 19 
`B. 
`The Alleged ’552 Patent Invention ..................................................... 21 
`C. 
`Prosecution History ............................................................................. 24 
`V.  Overview of the Primary Prior Art References ............................................. 27 
`A. 
`Summary of the Prior Art .................................................................... 27 
`B. 
`Overview of Heath (Ex. 1003) ............................................................ 28 
`C. 
`Overview of Supporting References ................................................... 30 
`1.  Hawley (Ex. 1004) .............................................................................. 30 
`2.  Overview of Chappell (Ex. 1005) ....................................................... 30 
`3.  Overview of Dennison (Ex. 1006) ...................................................... 31 
`VI.  Claim Construction ........................................................................................ 33 
`VII.  Level of Ordinary Skill In The Art ................................................................ 39 
`VIII.  Specific Grounds for Petition ........................................................................ 40 
`A.  Ground 1: Claims 1-2, 4-7 are Anticipated by Heath ........................ 40 
`1.  Independent Claim 1 ........................................................................... 40 
`2.  Claim 2: “The semiconductor apparatus of claim 1 wherein said etch
`stop material comprises silicon nitride” ................................................... 48 
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`3.  Claim 4: “The structure of claim 1, wherein the insulating spacer has
`a surface portion in the contact region without overlaying etch stop
`material” ................................................................................................... 49 
`4.  Claim 5: “The structure of claim 4, wherein the insulating spacer
`surface portion without overlying etch stop material comprises an
`insulating spacer surface portion most distant from said substrate” ........ 50 
`5.  Claim 6: “The structure of claim 1, further comprising a second
`insulating layer on the etch stop layer and over the conductive layer” .... 51 
`6.  Claim 7: “The structure of claim 6, further comprising a second
`conductive material in the contact region” ............................................... 51 
`Ground 2: Claim 3 Would Have Been Obvious Over Heath in View
`of Hawley and Chappell ...................................................................... 52 
`1.  Claim 3: “The semiconductor apparatus of claim 1 wherein said etch
`stop material comprises silicon dioxide”.................................................. 52 
`Ground 3: Claims 1-2, 4-7 Would Have Been Obvious Over Heath in
`View of Dennison ................................................................................ 55 
`1.  Heath, in combination with Dennison, renders the claims obvious
`under an overly narrow construction of the “angle” limitation—e.g.,
`limiting it to a particular portion of the “side” of the insulating spacer—
`recited in claim 1 (element 1(f)) ............................................................... 56 
`D.  Ground 4: Claim 3 Would Have Been Obvious Over Heath in View
`of Dennison, Hawley and Chappell .................................................... 67 
`IX.  Availability for Cross-Examination .............................................................. 67 
`X. 
`Right to Supplement ...................................................................................... 68 
`
`B. 
`
`C. 
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`I, John C. Bravman, declare as follows:
`
`1. My name is John C. Bravman.
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`2. My academic training was at Stanford University, where I received
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`my Bachelor of Science degree in Materials Science and Engineering in 1979, and
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`a Master of Science degree in 1981, also in Materials Science and Engineering. I
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`completed my Doctor of Philosophy degree in 1984, with a dissertation that
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`focused on the nature of silicon – silicon dioxide interfaces as found in integrated
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`circuit devices.
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`3.
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`From 1979 to 1984, while a graduate student at Stanford, I was
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`employed part-time by Fairchild Semiconductor in their Palo Alto Advanced
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`Research Laboratory. I worked in the Materials Characterization group. In 1985,
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`upon completion of my doctorate, I joined the faculty at Stanford as Assistant
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`Professor of Materials Science and Engineering. I was promoted to Associate
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`Professor with tenure in 1991, and achieved the rank of Professor in 1995. In 1997
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`I was named to the Bing Professorship.
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`4.
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`At Stanford I was Chairman of the Department of Materials Science
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`and Engineering from 1996 to 1999, and Director of the Center for Materials
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`Research from 1998 to 1999. I served as Senior Associate Dean of the School of
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`Engineering from 1992 to 2001 and the Vice Provost for Undergraduate Education
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`from 1999 to 2010. On July 1, 2010, I retired from Stanford University and
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`assumed the Presidency of Bucknell University, where I also became a Professor
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`of Electrical Engineering.
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`5.
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`I have worked for more than 25 years in the areas of thin film
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`materials processing and analysis. Much of my work has involved materials for
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`use in microelectronic interconnects and packaging, and in superconducting
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`structures and systems. With regard to integrated circuits, I led investigations
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`involving aluminum, copper and tungsten metallizations, polycrystalline silicon,
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`metal silicides, a variety of oxide and nitride dielectrics, and barrier layers such as
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`titanium and tantalum-based nitrides. Further, my groups blended fundamental
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`aspects of the behavior of microelectromechanical systems—specifically,
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`compliant multilayer cantilever beams—for possible test probe and package
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`implementations. In this work my group investigated the mechanical behavior of
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`package underfill systems, focusing on the relationship between microstructures,
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`processing, and adhesion. I have also led multiple development efforts of
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`specialized equipment and methods for determining the microstructural and
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`mechanical properties of materials and structures. My groups designed and built
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`the first high voltage SEM for in-situ studies of electromigration, the first high
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`temperature wafer curvature system, and the first microtensile tester for micron-
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`scale structures, amongst many others. As a graduate student I developed one of
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`the earliest methodologies for obtaining high resolution cross section transmission
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`electron micrographs of integrated circuit structures.
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`6.
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`I have taught a wide variety of courses at the undergraduate and
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`graduate level in materials science and engineering, emphasizing both basic
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`science and applied technology, including coursework in the areas of integrated
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`circuit materials and processing. Some of these courses focused on processes (e.g.,
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`cleaning, etching, deposition, doping, oxidation, etc.) used in the production of
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`integrated circuits. More than two thousand students have taken my classes, and I
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`have trained 24 doctoral students, most of whom now work in the microelectronics
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`industry.
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`7.
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`In the course of my research, my group made extensive use of sputter
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`etching technologies for the creation of the films and patterned structures
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`appropriate to our testing protocols. We worked both within Stanford’s
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`laboratories and with many industrial partners.
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`8.
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`I am a member of many professional societies, including the Materials
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`Research Society, the Institute of Electrical and Electronic Engineers, the
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`American Society of Metals, and the American Physical Society. I served as
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`President of the Materials Research Society in 1994.
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`9.
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`A copy of my curriculum vitae (including a list of all publications
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`authored in the previous 10 years) is attached as Appendix A.
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`I have reviewed the specification, claims and file history of U.S.
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`10.
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`Patent No. 6,784,552. I understand that the ’552 patent was filed on March 31,
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`2000 and claims priority to U.S. Patent Appl. No. 08/577,751 (now U.S. Patent No.
`
`6,066,555) filed on December 22, 1995. I understand that, for purposes of
`
`determining whether a publication will qualify as prior art, the earliest date that
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`the ’552 patent could be entitled to is December 22, 1995. However, I further
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`understand that the prior assignee claimed a priority date prior to April 21, 1995
`
`during prosecution of the ’555 parent application. ’555 Declaration Under 37
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`C.F.R. 1.131, Feb. 25, 1999 (Ex. 1011) at 3. In any case, the cited references are
`
`prior art and invalidate the ’552 patent.
`
`11.
`
`I have reviewed the following patents and publications in preparing
`
`this declaration:
`
` U.S. Patent No. 4,686,000 (“Heath”) (Ex. 1003).
`
` European Patent Publ. No. 0592078 (“Hawley”) (Ex. 1004).
`
` U.S. Patent No. 5,541,427 (“Chappell”) (Ex. 1005).
`
` U.S. Patent No. 5,338,700 (“Dennison”) (Ex. 1006).
`
` U.S. Patent No. 5,374,836 (“Vinal”) (Ex. 1009).
`
` U.S. Patent No. 5,053,351 (“Fazan”) (Ex. 1012).
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` J. Dulak et al., Etch mechanism in the reactive ion etching of silicon
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`nitride, Journal of Vacuum Science & Technology A 9, 775 (1991)
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`(“Dulak”) (Ex. 1010).
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`12.
`
`I have reviewed the above patents and publications and any other
`
`publication cited in this declaration.
`
`13.
`
`I have considered certain issues from the perspective of a person of
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`ordinary skill in the art as described below at the time the ’552 patent application
`
`was filed. In my opinion, a person of ordinary skill in the art for the ’552 patent
`
`would have found the ’552 patent invalid.
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`14.
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`I have been retained by the Petitioner as an expert in the field of
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`semiconductor device fabrication and design. I am working as an independent
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`consultant in this matter and am being compensated at my normal consulting rate
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`of $450 per hour for my time. My compensation is not dependent on and in no
`
`way affects the substance of my statements in this Declaration.
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`15.
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`I have no financial interest in the Petitioner. I similarly have no
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`financial interest in the ’552 patent, and have had no contact with the named
`
`inventor of the ’552 patent.
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`I. RELEVANT LAW
`16.
`I am not an attorney. For the purposes of this declaration, I have been
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`informed about certain aspects of the law that are relevant to my opinions. My
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`understanding of the law is as follows:
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`A. Claim Construction
`17.
`I have been informed that claim construction is a matter of law and
`
`that the final claim construction will ultimately be determined by the Board. For
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`the purposes of my analysis in this proceeding and with respect to the prior art, I
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`have been informed that I should apply what is known as “the Phillips standard,”
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`rather than the broadest reasonable interpretation standard.
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`18.
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` Specifically, I have been informed and understand that since the ’552
`
`patent will expire prior to any Final Decision (and likely even before the date of
`
`the Decision on Institution) of this inter partes review, the Phillips standard applies
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`for the purposes of claim construction. I further understand that the Phillips
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`standard means that claim terms are given their plain and ordinary meaning as
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`understood by a person of ordinary skill in the art at the time of the invention in
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`light of the claim language and the patent specification.
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`19.
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`I have also been informed and understand that any claim term that
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`lacks a definition in the specification is therefore given its plain and ordinary
`
`meaning as understood by one of ordinary skill in the art.
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`B. Anticipation
`20.
`I have been informed and understand that a patent claim may be
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`“anticipated” if each element of that claim is present either explicitly, implicitly, or
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`inherently in a single prior art reference. I have also been informed that, to be an
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`inherent disclosure, the prior art reference must necessarily disclose the limitation,
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`and the fact that the reference might possibly practice or contain a claimed
`
`limitation is insufficient to establish that the reference inherently teaches the
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`limitation.
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`C. Obviousness
`21.
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a person of ordinary skill in the art at the time
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`the application was filed. This means that, even if all of the requirements of a
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`claim are not found in a single prior art reference, the claim is not patentable if the
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`differences between the subject matter in the prior art and the subject matter in the
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`claim would have been obvious to a person of ordinary skill in the art at the time
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`the application was filed.
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`22.
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`I have been informed and understand that a determination of whether
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`a claim would have been obvious should be based upon several factors, including,
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`among others:
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` the level of ordinary skill in the art at the time the application was filed;
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`U.S. Patent No. 6,784,552
`Claims 1-7
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` the scope and content of the prior art; and
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` what differences, if any, existed between the claimed invention and the
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`prior art.
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`23.
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`I have been informed and understand that the teachings of two or
`
`more references may be combined in the same way as disclosed in the claims, if
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`such a combination would have been obvious to one having ordinary skill in the
`
`art. In determining whether a combination based on either a single reference or
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`multiple references would have been obvious, it is appropriate to consider, among
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`other factors:
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` whether the teachings of the prior art references disclose known concepts
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`combined in familiar ways, which, when combined, would yield
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`predictable results;
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` whether a person of ordinary skill in the art could implement a
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`predictable variation, and would see the benefit of doing so;
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` whether the claimed elements represent one of a limited number of
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`known design choices, and would have a reasonable expectation of
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`success by those skilled in the art;
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` whether a person of ordinary skill would have recognized a reason to
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`combine known elements in the manner described in the claim;
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` whether there is some teaching or suggestion in the prior art to make the
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`modification or combination of elements claimed in the patent; and
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` whether the innovation applies a known technique that had been used to
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`improve a similar device or method in a similar way.
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`24.
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`I understand that one of ordinary skill in the art has ordinary
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`creativity, and is not an automaton.
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`25.
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`I understand that in considering obviousness, it is important not to
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`determine obviousness using the benefit of hindsight derived from the patent being
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`considered.
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`II. SUMMARY OF OPINIONS
`26.
`It is my opinion that every limitation of the structures described in
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`claims 1 through 7 of the ’552 patent are disclosed by the prior art, and are
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`anticipated and/or rendered obvious by the prior art.
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`III. BRIEF DESCRIPTION OF THE TECHNOLOGY
`A. Basic Structure of Transistors
`27. The ’552 patent relates to the field of semiconductor integrated circuit
`
`manufacturing. Semiconductor integrated circuits, such as microprocessors and
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`computer memory, are typically made up of hundreds of millions (and in some
`
`cases billions) of microscopic structures called transistors. Transistors act as
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`microscopic switches that turn on and off at extraordinarily high rates to enable
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`aggregations of transistors (and other components) to process data.
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`28. As shown in the figure below, transistors typically include three
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`primary “electrodes” or “terminals”—a gate, a source, and a drain—embedded in
`
`or on a dielectric substrate and surrounded by other dielectric materials:
`
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`29. The source and drain regions (also referred to as “diffusion regions”)
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`are transistor components that emit (source) and receive (drain) current when the
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`transistor is “on.” The gate typically sits between the source and drain and is a
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`terminal that can have a voltage applied to it that in turn causes a current to flow
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`between the source and drain.
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`30. The gate, source and drain of a transistor typically need to be
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`connected to other components to form an electrical circuit. The ’552 patent refers
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`to the components used to make these connections as “contacts.” Contacts consist
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`of one or more conducting materials (e.g., a metal) that allow current to flow
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`between transistor components. In many cases, it is important to maintain
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`electrical isolation between contacts and other nearby components (such as a gate
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`electrode) so that current that is supposed to flow to other parts of the circuit does
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`not instead flow to these nearby components (e.g., the gate). As described in more
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`detail below, devices called sidewall spacers can be formed between the contact
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`and the nearby components to maintain this electrical isolation.
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`B. Overview of Transistor Fabrication
`1. Formation of Transistor Components
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`31. Transistor fabrication typically starts with a silicon substrate. In
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`typical planar transistors, source and drain regions (“diffusion regions”) are created
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`by implanting regions of the substrate with ions (charged atomic particles) of
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`different materials—called “dopants” or “impurities”—to make those regions
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`conductive. (Once implanted the ions become neutral atoms.) This process—
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`referred to as “doping” because it dopes the silicon substrate with atomic particles
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`that have additional charge carriers—is shown below:
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`32. Structures can then be formed above the substrate by depositing layers
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`of other materials onto the substrate. A gate electrode, for example, is formed by
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`first growing or depositing a “gate oxide” (an insulator) on the substrate followed
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`by depositing a conductive material (metal or polysilicon) on top of the gate oxide.
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`The conductive material acts as the gate and the gate oxide creates a layer of
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`isolation between the gate and the source/drain regions (“S/D regions” or
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`“diffusion regions”).
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`33.
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`Insulating materials may then be deposited around and over the gate
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`and the S/D regions to maintain electrical isolation where desired. Sidewall
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`spacers, for instance, can be formed on each side of the gate electrode as shown
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`below:
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`As was known as of the time of the alleged ’552 invention, such sidewall spacers
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`help to prevent direct electrical contact between the gate electrode and nearby
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`components and thus help to prevent short-circuits.
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`2. Etching to Create Contact Openings
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`34. Gate electrodes and S/D regions of transistors must typically be
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`connected to other components in the semiconductor device. These connections
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`are made using “contacts”—connections between components that allow electrical
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`signals to pass between the components. Contacts are formed by creating openings
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`through the layers of a semiconductor device (i.e. “contact openings”) and then
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`filling the openings with a conductive material. Fig. 4(J) of the ’552 patent shows
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`a fully-formed contact opening 460, while Fig. 4(L) shows the contact opening
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`after it has been filled with a conductive material 480 (pink) to form the contact1:
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`The process of removing material to create contact openings is known as
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`“etching.” To perform etching, semiconductor manufacturers use “etchants.” As
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`was known at the time of the alleged ’552 invention, etchants have various known
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`properties that can be chosen depending on the type of etching desired.
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`35. Etching can be performed “isotropically” or “anisotropically.” An
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`isotropic etch will etch material in all directions (e.g., both vertically and
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`horizontally with respect to the substrate surface). An anisotropic etch will etch
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`material more effectively in a particular direction (e.g., vertically but not
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`horizontally relative to the substrate surface).
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`36. Etching can also be “wet” or “dry.” Wet etching refers to etching in
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`which the etchant is a liquid, which will dissolve through a particular material to
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`1 All emphasis and annotations added unless otherwise indicated.
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`create a contact opening. Dry etching—sometimes based on the physical process
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`known as “sputtering”—is etching away material by using a gas or plasma to
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`bombard the material to be etched with ions. Generally, wet etching is used to
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`perform isotropic etching (i.e., all directions) and dry etching is used to perform
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`anisotropic etching (i.e., one direction).
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`37. Etchants can also be “selective” or “non-selective.” The “selectivity”
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`of an etchant refers to its effectiveness at etching away one type of material versus
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`another type of material. A highly-selective etchant relative to a particular material
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`will etch away that material at a much faster rate than a different type of material.
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`A non-selective etchant will etch away both types of materials at approximately the
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`same rate. See, e.g., ’552 at 2:12-21; see also id. at 4:66-5:2. The same etchant
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`can behave as either a selective or non-selective etchant depending on the material
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`being etched, the processing conditions, and other parameters of the etching
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`process. For example, an etchant that is selective as to one material can be non-
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`selective as to another.
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`38. As was well-known at the time of the ’552 patent, contact openings of
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`various shapes and sizes can be created depending on the etching method chosen.
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`As shown in Figs. 4(H) and 4(I) of the ’552 patent, the etchant removes material to
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`create an “opening” in the layers of a semiconductor device. Fig. 4(H) shows a
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`transistor structure with insulating material 450 (green) covering the diffusion
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`regions 445 (orange). Fig. 4(I) shows the same structure after the insulating
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`material has been etched to create contact openings 460 and 465 which extend
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`down towards the diffusion regions:
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`39. As was also well known, “etch stop layers” (material 440 in Figs.
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`4(H) and 4(I)) can be used to avoid etching areas not intended to be removed. An
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`etch stop layer, as its name suggests, effectively stops an etchant from further
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`eroding or removing material once the etching process reaches the etch stop layer.
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`Etch stop layers are thus used to protect components (e.g., a gate electrode or S/D
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`region) by stopping the etchant before it reaches the protected component.
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`40. The following figures illustrate the process. The figure below (step 1)
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`shows a diffusion region with an etch stop layer above it and further covered by an
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`insulating material:
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`41. As shown in the figure below (step 2), to make a contact opening
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`down to the diffusion region, an etchant is applied to the insulating material. The
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`etchant effectively etches away the insulating material but not the etch stop layer.
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`As a result, when the etchant reaches the etch stop layer, etching is stopped. In this
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`way, the etch stop layer prevents the etchant from etching into and damaging the
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`diffusion region:
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`42. As shown in the figure below (step 3), the etch stop layer can then be
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`removed by using a different (and usually more precise) etching process to
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`complete the contact opening down to the diffusion region:
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`IV. OVERVIEW OF THE ’552 PATENT
`A. The Alleged Problem in the Art
`43. The ’552 patent purports to describe an improved technique for
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`forming contact openings in transistors. The patent asserts that prior art techniques
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`for forming contact openings resulted in an unacceptably high risk of creating
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`unintentional connections (and thus a short-circuit) between the contacts and
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`nearby components. Specifically, according to the patent, the use of highly
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`selective etchants to create contact openings caused the sidewall spacers between a
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`contact opening and a nearby component (such as a gate electrode) to become
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`sloped. ’552 at 5:6-14 (“The properties of the highly selective etch of the
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`overlying etch stop layer 240 will transform a substantially rectangular spacer
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`into a sloped spacer.”); id. at 2:4-6, 2:39-41. This is shown in Fig. 2(B):
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`The figure, described as “Prior Art,” shows a contact opening 270, a sidewall
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`spacer 235, and a gate electrode 220 that needs to remain isolated from the contact
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`19
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`opening. As shown, the sidewall spacer has become “sloped.” ’552 at 5:6-14; see
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`also id. at 5:51-55.
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`44. The patent then explains that, in subsequent fabrication steps, a sloped
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`sidewall is particularly susceptible to erosion such that it can be worn down to the
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`point that the contact opening and a nearby component (e.g., the gate electrode)
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`can come into unintentional contact. Specifically, the patent explains that, after the
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`contact opening is formed, an additional etching step is usually performed to clean
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`the contact opening. ’552 at 5:55-56 (explaining that “RF sputter etch” is
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`performed). This final etching step—which is a dry etch performed using vertical
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`bombardment—can erode the remaining insulating material separating the gate
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`electrode from the contact opening. The patent explains that because the sidewall
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`spacer has become sloped, it is more directly exposed to the vertical bombardment
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`and thus more susceptible to erosion. ’552 at 5:59-6:1 (“The dynamics of the
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`sputter etch 380 are that it proceeds vertically, directing high-energy particles at
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`the contact region. . . . Because the spacer portion 370 is sloping or diagonal, a
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`significant surface area portion of the spacer portion 370 is directly exposed to
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`the high-energy particles from the RF sputter etch 380.”). This is shown in Fig.
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`3:
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`20
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`As shown, as a result of this process, the sloped sidewall spacer has become further
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`eroded from the dotted line (370) to the solid line such that the gate electrode 320
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`is now exposed to the contact opening. ’552 at 6:14-19 (“[T]he result of the
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`sputter etch 380 is that the sputter etch 380 laterally erodes the diagonal portion of
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`the TEOS spacer portion 370 adjacent to the contact region to a point where the
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`polysilicon layer 320 [i.e., the gate electrode] is no longer isolated from the contact
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`region 360 by an insulating layer.”). According to the patent, such contact results
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`in a short-circuit and thus a non-functioning transistor. ’552 at 6:19-21.
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`B. The Alleged ’552 Patent Invention
`45. The patent purports to solve this problem by using a process that
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`prevents the formation of a sloped spacer and instead retains the “substantially
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`rectangular” shape of the lateral spacer. ’552 at 11:48-49 (“[C]are is taken to etch
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`the spacers 435 such that the spacers 435 have a substantially rectangular
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`21
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`profile.”), 13:9-16 (“Of primary significance, the spacer portion 435 of the TEOS
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`layer retains its substantially rectangular profile. . . . The invention relates to these
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`process conditions as well as others that result in the retention of a boxy spacer.”
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`(TEOS is a common type of insulator used in integrated circuits)).
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`46. The patent does not purport to have invented the use of sidewall
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`spacers, the use of anisotropic etchants to etch in a vertical direction, or the use of
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`such etchants to form contact openings. All of this was indisputably well-
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`known. ’552 at 1:10-7:13 (Background). Instead, the patent claims as its novel
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`concept the use of a known etchant in such a way that retains the “substantially
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`rectangular” shape of the sidewall spacer. Specifically, the patent describes using
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`an anisotropic etchant that etches only vertically relative to the substrate surface to
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`form a contact opening. According to the patent, the use of such an etchant avoids
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`the problem of creating a sloped spacer and instead “retains the substantially
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`rectangular lateral spacer portion” of the lateral spacer. ’552 at 7:45-51 (“The
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`etch-stop is also almost completely anisotropic, meaning that the etchant etches in
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`one direction-in this case, vertically (or perpendicular relative to the substrate
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`surface) rather than horizontally. The etch removes the etch stop insulating layer
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`and retains the substantially rectangular lateral spacer portion of the first
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`insulating layer.”).
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`22
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`47. Figs. 4(J) and 4(K) (which is a blow up of 4(J)) show the contact
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`opening after etching is complete:
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`’552 at 12:54-13:10. As shown by the red lines in the figures, after the contact
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`opening 460 has been etched, the sidewalls (420) have vertical sides thus retaining
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`their “substantially rectangular” shape.
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`48. As a result, according to the patent, the lateral spacer is less
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`susceptible to erosion in the subsequent sputter etch step—which involves the
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`vertical bombardment of the contact region with high energy particles—and thus
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`the risk of unintentional contact (and short-circuit) with nearby components is
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`reduced. ’552 at 7:62-8:3 (“Unlike prior art processes whereby the sputter etch
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`erodes the underlying sloping lateral spacer portion of the first insulating layer
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`adjacent to the conducting layer, the sputter etch does not significantly erode the
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`substantially rectangular lateral spacer of the first insulating layer, thus allowing
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`the conductive layer of the device structure to remain completely isolated. . . .”).
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`Claim 1 is the sole challenged independent claim. The dependent claims add only
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`implementation details such as: the specific materials for certain components
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`23
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`(claims 2-3); additional specificity regarding the materials around the insulating
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`U.S. Patent No. 6,784,552
`Claims 1-7
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`spacer (claims 4-5); additional insulating layers on the structure (claim 6); and
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`c