Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`Paper No. ________
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
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`Sony Corporation
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`Petitioner
`v.
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`Raytheon Company
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`(record) Patent Owner
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`Patent No. 5,591,678
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`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET. SEQ
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`Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`TABLE OF CONTENTS
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`TABLE OF CONTENTS ........................................................................................ i
`TABLE OF EXHIBITS ....................................................................................... iii
`NOTICE OF LEAD AND BACKUP COUNSEL ................................................. 1
`NOTICE OF THE REAL-PARTIES-IN-INTEREST ........................................... 1
`NOTICE OF RELATED MATTERS .................................................................... 1
`NOTICE OF SERVICE INFORMATION ............................................................ 2
`GROUNDS FOR STANDING .............................................................................. 2
`STATEMENT OF PRECISE RELIEF REQUESTED .......................................... 2
`THRESHOLD REQUIREMENT FOR INTER PARTES REVIEW .................... 3
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`I. INTRODUCTION TO THE SUBJECT MATTER ............................................. 3
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`II. INTRODUCTION TO THE PRIOR ART ............................................................ 9
`A. Overview of Liu ....................................................................................... 10
`B. Overview of Wen ..................................................................................... 13
`C. Overview of Black ................................................................................... 16
`D. Summary of the Prior Art ........................................................................ 17
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`III. CLAIM CONSTRUCTION & LEVEL OF SKILL IN THE ART ................... 18
`A. Claims 1, 3, 6-7, 11, 13, 15 — “Microelectronic Circuit Element” ........ 18
`B. Claims 1, 11, 13 — “Etching,” “Etchable Layer” and
`“Etch-Stop Layer” .................................................................................... 19
`C. Claims 1, 3-5, 11-13, 15-18 — “Wafer” ................................................. 20
`D. Level of Skill in the Art ........................................................................... 20
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`IV. DETAILED EXPLANATION OF THE REASONS FOR
`UNPATENTABILITY............................................................................................. 20
` Claims 1-4, 6, 7, 10 and 11 are anticipated by Liu. ......................... 20 Ground 1.
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` Claims 2-4 and 11 are obvious over Liu in view of Black. ............. 33 Ground 2.
`Ground 3.
` Claims 5 and 12-16 are obvious over Liu in view of Riseman. ...... 36
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` Claim 8 is obvious over Liu in view of Oldham. ............................ 49 Ground 4.
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` Claim 10 is obvious over Liu in view of Wen. ................................ 50 Ground 5.
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` Claim 9 is obvious over Liu in view of Wen, in further view of Ground 6.
`Ying. ................................................................................................. 52
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`Kusunoki. ......................................................................................... 54
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` Claim 17 is obvious over Liu in view of Riseman, in further view of Ground 7.
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`Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`Ground 8.
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`Claim 18 is obvious over Liu in view of Riseman, in further view of
`Oldham. ............................................................................................ 57
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`V. CONCLUSION ................................................................................................... 59
`CERTIFICATE OF SERVICE ............................................................................ 60
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`Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`TABLE OF EXHIBITS
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`Exhibit No.
`1001
`1002
`1003
`1004
`1005
`1006
`1007
`1008
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`1009
`1010
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`1011
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`1012
`1013
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`1014
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`Description
`U.S. Patent No. 5,591,678 (“the ’678 patent”).
`Declaration of Dr. Blanchard.
`U.S. Pat. No. 4,422,091 (“Liu”).
`U.S. Pat. No. 3,846,198 (“Wen”)
`U.S. Pat. No. 4,681,718 (“Oldham”).
`U.S. Pat. No. 3,864,819 (“Ying”).
`U.S. Pat. No. 4,426,768 (“Black”).
`Certified translation of Japanese Unexamined Patent Application
`Publication No. 03-108776 (“Kusunoki”).
`U.S. Patent No. 4,106,050 (“Riseman”).
`Excerpt from Dictionary of Electronics, Harper-Collins, 2004 (p.
`152).
`U.S. Pat. App. Ser. No. 08/006,120, Amendment of June 16,
`1994.
`U.S. Pat. App. Ser. No. 08/006,120 (application with claims).
`Independent claim comparison for the ’678 patent.
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`Japanese Unexamined Patent Application Publication No. 03-
`108776, published May 8, 1991.
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`Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`NOTICE OF LEAD AND BACKUP COUNSEL
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`Lead Counsel: Matthew A. Smith (Reg. No. 49,003); Tel: 650.265.6109
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`Backup Counsel: Zhuanjia Gu (Reg. No. 51,758); Tel: 650.529.4752
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`Backup Counsel: Robert Hails (Reg. No. 39,702); Tel. 202.220.4235
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`Address of lead counsel: Turner Boyd LLP, 702 Marshall St., Ste. 640
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`Redwood City, CA 94063. FAX: 650.521.5931.
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`NOTICE OF THE REAL-PARTIES-IN-INTEREST
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`The real-parties-in-interest for this petition are Sony Corporation, Sony
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`Corporation of America, Sony Semiconductor Corporation, Sony EMCS
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`Corporation, Sony Electronics, Inc., Sony Mobile Communications, Inc., Sony
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`Mobile Communications AB and Sony Mobile Communications (USA), Inc.
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`NOTICE OF RELATED MATTERS
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`U.S. Patent No. 5,591,678 (“the ’678 patent”) has been asserted in Raytheon
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`Company v. Sony Corporation, et al., C.A. No. 2:15-cv-342 (E.D. Tex.) and
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`Raytheon Company v. Samsung Electronics Co., Ltd., et al., C.A. No. 2-15-cv-
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`00341 (E.D. Tex.). Both cases were filed March 6, 2015 and remain pending.
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`Petitioner has filed a Petition for inter partes review of the ’678 patent, and
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`Patent Owner has filed its preliminary response, in IPR2015-01201. A decision on
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`whether to institute review has not yet been issued therein. The validity challenges
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`presented in this Petition are not redundant of those in IPR2015-01201: Petitioner
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`does not rely on the principal references from the earlier Petition herein; the
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`Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`principal reference in this Petition qualifies as prior art under 35 U.S.C. § 102(b),
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`whereas the principal reference in Ground 1 of the earlier Petition was prior art
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`under 35 U.S.C. § 102(e); and the principal reference relied on in this Petition was
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`not known to Petitioner when the Petition in IPR2015-01201 was filed.
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`NOTICE OF SERVICE INFORMATION
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`Please address all correspondence to the lead counsel at the addresses shown
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`above. Petitioners consent to electronic service by email at:
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`smith@turnerboyd.com, docketing@turnerboyd.com, gu@turnerboyd.com,
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`seraphine@turnerboyd.com and rhails@kenyon.com.
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`GROUNDS FOR STANDING
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`Petitioner hereby certifies that the patent for which review is sought is available
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`for inter partes review, and that the Petitioner is not barred or estopped from
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`requesting an inter partes review on the grounds identified in the petition.
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`STATEMENT OF PRECISE RELIEF REQUESTED
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`Petitioner respectfully requests that claims 1-18 of U.S. Patent No. 5,591,678
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`(“the ’678 patent”)(Ex. 1001) be canceled based on the below listed grounds. The
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`primary reference in each ground is U.S. Patent No. 4,422,091 (“Liu”). Several
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`additional grounds are presented for dependent claims, which recite only common
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`features of microelectronic circuits within the relevant timeframe.
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`Ground 1: Claims 1-4, 6-7, and 10-11 are anticipated by Liu.
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`Ground 2: Claims 2-4 and 11 are obvious over Liu in view of Black.
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`Ground 3: Claims 5 and 12-16 are obvious over Liu in view of Riseman.
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`Ground 4: Claim 8 is obvious over Liu in view of Oldham.
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`Ground 5: Claim 10 is obvious over Liu in view of Wen.
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`Ground 6: Claim 9 is obvious over Liu in view of Wen, in further view of Ying.
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`Ground 7: Claim 17 is obvious over Liu in view of Riseman, in further view of
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`Kusunoki.
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`Ground 8: Claim 18 is obvious over Liu in view of Riseman, in further view of
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`Oldham.
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`THRESHOLD REQUIREMENT FOR INTER PARTES REVIEW
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`This petition presents “a reasonable likelihood that the Petitioners would prevail
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`with respect to at least one of the claims challenged in the petition”, 35 U.S.C.
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`§ 314(a), as shown in the Grounds explained below.
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`I. INTRODUCTION TO THE SUBJECT MATTER
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`The following introduction is essentially the same as that presented in IPR2015-
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`01201. New discussion begins at Section II, p. 9.
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`At a high level, the ’678 patent involves the manufacture of stacked integrated
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`circuits, or “chips”. (Ex. 1001, 1:65 – 2:2; 7:60-65). When chips are used in a
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`system, they are often mounted adjacent to each other on a
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`circuit board, as shown in the drawing at right (looking down
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`onto a flat board). Circuit boards may have to fit into a
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`computer or other device having a compact housing. Because
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`of the spatial limits of the housing, circuit boards often have a
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`limited area. This limited area can constrain the number and
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`size of chips that can be wired to the board. (Ex. 1002, ¶38).
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`One way to increase the number of chips on a circuit board is to stack the chips,
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`as shown in the drawing, left. Two stacked chips
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`take up approximately the same circuit board area
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`as a single chip. (Ex. 1002, ¶38). When stacked,
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`the electrical contacts on each chip need to be wired
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`to the circuit board. (Ex. 1001, 1:51-57). In the relevant timeframe there was an
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`active industry designing stacked chips. (Ex. 1002, ¶38).
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`In the disclosure of the ’678 patent, stacks are made by manipulating and
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`stacking semiconductor-based building blocks
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`called “substrates”. Each substrate begins as
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`three layers: an “etchable layer”, an “etch-
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`stop” layer and a “wafer”. Substrate 40 has a
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`top “wafer” 46 (highlighted yellow in the relevant portion of Fig. 1), a bottom
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`etchable layer 42 (blue), and a middle etch-stop layer 44 (green). (Ex. 1001, 3:64 –
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`4:2)(Ex. 1002, ¶40). The top wafer 46 contains integrated circuit elements, such as
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`transistors. (Ex. 1002, ¶40). The bottom “etchable layer” 42 is a layer that
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`dissolves readily when exposed to an etchant. In contrast, the middle “etch-stop”
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`layer 44 does not dissolve readily when exposed to the etchant. Because of this, an
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`etching process stops when the etchant reaches the “etch-stop” layer, after having
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`dissolved the etchable layer 42. (Ex. 1002, ¶¶43, 47).
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`The thick etchable layer 42 on each substrate provides mechanical stability.
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`Without such an etchable layer, according to the ’678 patent, the overall substrate
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`might be too thin, and therefore too fragile to handle. (Ex. 1001, 1:58-65)(Ex.
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`1002, ¶48). The ’678 patent states:
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`“The circuit element usually is fabricated with a relatively thick first
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`substrate that provides support during initial fabrication and
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`handling.” (Ex. 1001, 2:61-64)(Emph. add.)(Ex. 1002, ¶49).
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`To form a stack of chips, one could stack several of the three-layer substrates,
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`each of which contains its own integrated circuit in layer 46. Once a stack of chips
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`is formed, the chips need to be electrically connected. Connections to the chips are
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`made at the contacts on each chip. These contacts can be connected using wires
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`that run from the contacts down the sides of the chip stack to the circuit board, and
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`then back up to another chip. (Ex. 1002, ¶50). According to the ’678 patent,
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`however, this method is “clumsy, space consuming, and impossible to do for the
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`case of highly complex circuitry”. (Ex. 1001, 1:51-57)(Ex. 1002, ¶50).
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`Another way to connect the contacts of chips in a stack would be through the
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`etchable layer 42 and the etch-stop layer 44. The ’678 patent describes, for
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`example, through-holes (or “vias”) through which such a connection can be made.
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`(Ex. 1001, 6:10-42). This would allow a chip that is lower in the stack to connect
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`to the underside of a chip higher in the stack. The ’678 patent states, however, that
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`it is difficult to form electrical connections that go all the way through the thick
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`etchable layer 42:
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`“It is difficult to achieve electrical connections through such a thick
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`substrate, because of the difficulty in locating deep, through-support
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`vias precisely at the required point, the difficulty in insulating the
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`walls of deep vias, and the difficulty in filling a deep via with
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`conducting material.” (Ex. 1001, 2:64-3:2)(Ex. 1002, ¶51).
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`One could remove the thick etchable layer to make the formation of vias easier.
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`However, the ’678 patent states that the etchable layer “cannot simply be removed
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`to permit access to the bottom side of the electrical circuit element, as the assembly
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`could not be handled in that very thin form”. (Ex. 1001, 3:2-5)(Ex. 1002, ¶52).
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`Therefore, the ’678 patent discloses another method: attaching the three-
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`layer substrate shown in Fig. 1 to a different, “support” structure. The ’678 patent
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`states: “[i]n the present approach, after initial circuit element fabrication on a first
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`substrate structure, the electrical circuit element is transferred to a second substrate
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`structure.” (Ex. 1001, 3:7-8)(Ex. 1002, ¶53). Once the substrate is supported by
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`the new support structure, the ’678 patent discloses removing the etchable layer 42.
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`For example, claim 1 of the ’678 patent recites:
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` “1. A method of fabricating a microelectronic device, comprising the
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`steps of:
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`furnishing a first substrate having an etchable layer, an etch-stop
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`layer overlying the etchable layer, and a wafer overlying the etch-stop
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`layer;
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`forming a microelectronic circuit element in the exposed side of the
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`wafer of the first substrate opposite to the side overlying the etch-stop
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`layer;
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`attaching the wafer of the first substrate to a second substrate; and
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`etching away the etchable layer of the first substrate down to the etch-
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`stop layer.” (Ex. 1001, 8:5-16).
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`The process of the ’678 patent is explained in more detail in reference to Fig. 1
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`of the ’678 patent, which shows a series of steps. The first step 20 involves
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`providing the substrate with three layers. (Ex. 1001, 3:66 – 4:2)(Ex. 1002, ¶40).
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`The ’678 patent admits that this three-layer substrate is not novel, stating “[s]uch
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`substrates can be purchased commercially.” (Ex. 1001, 4:2)(Ex. 1002, ¶40).
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`The second step 22 in the ’678 patent is the formation of a “microelectronic
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`circuit”. (Ex. 1002, ¶41). This step is recited in independent claims 1, 11 and 13
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`as “forming a microelectronic circuit element”. A “microelectronic circuit
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`element” is defined broadly in the specification. (Ex. 1001, 4:43-52); see § III.A,
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`below.
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`The next step 24 (shown in the relevant portion of Fig. 1, with highlighting
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`added) involves attaching to the top of the first
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`microelectronic element to a second substrate
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`58 (orange). (Ex. 1002, ¶42). The second
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`substrate 58 can include its own microelectronic
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`circuit element. (Ex. 1001, 5:20-21)(Ex. 1002, ¶42). The second substrate and
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`wafer are bonded using (e.g.) epoxy. (Ex. 1001, 5:15-44)(Ex. 1002, ¶42).
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`The second substrate is then itself mounted
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`to a sapphire support 62 by a layer of wax 64.
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`(Ex. 1001, 5:47-49)(Ex. 1002, ¶43). The
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`support 62 (brown) is shown in the excerpt from Fig. 1, above right. In the figure,
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`an etching step has also been applied after the mounting step to remove etchable
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`layer 42. The etching step involves exposing the layer 42 to a liquid etchant. The
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`’678 patent notes that:
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`“The etchant is chosen so that it attacks the etchable layer 42 relatively
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`rapidly, but the etch-stop layer 44 relatively slowly or not at all. The
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`terms ‘etchable’ and ‘etch-stop’ indicate a relative relation to each
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`other in a particular etchant, as used herein.” (Ex. 1001, 5:52-56)(Ex.
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`1002, ¶43).
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`The ’678 patent also describes using “well known pattering techniques” to
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`perform back-side etching to the etch-stop layer, to form electrical connections to
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`the microelectronic circuit elements:
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`“Back-side electrical connections are formed through the etch-stop
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`layer 44 (for direct back-side interconnects 56) and through the etch
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`stop layer 44 and the wafer layer 45 to the microelectronic circuit
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`element 50 (for indirect front side interconnects 96), as shown at
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`numeral 28. To form such connections, the etch-stop layer 44 is
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`patterned by well known patterning techniques to precisely identify
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`the location to be penetrated. Material is removed from these locations
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`of the etch-stop layer 44 by any appropriate method. (Ex. 1001, 6:10-
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`19)(Ex. 1002, ¶44).
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`II. INTRODUCTION TO THE PRIOR ART
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`The principal reference in this Petition is U.S. Patent No. 4,422,091 (“Liu”)(Ex.
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`1003). Liu demonstrates that what the inventors of the ’678 patent represented was
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`inventive was well-known long before the ’678 patent parent application was filed
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`in 1993. (Ex. 1011, pp. 5-6). Secondary references U.S. Patent No. 3,846,198
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`(“Wen”)(Ex. 1004) and U.S. Patent No. 4,426,768 (“Black”) also disclose the
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`fundamental steps claimed in the ’678 patent, confirming that the claimed
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`invention was not new. Liu issued in 1983, Wen issued in 1974, and Black issued
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`in 1984, making all prior art under pre-AIA 35 U.S.C. § 102(b).
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`A. Overview of Liu
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`Liu describes a method for making a charge-coupled device (“CCD”), which
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`facilitates the movement of electrical charge, usually from within the device to an
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`area where the charge can be manipulated. (Ex. 1003, 1:11-13)(Ex. 1002, ¶72).
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`Like the ’678 patent, Liu starts with a three-part substrate, shown in Fig. 2B of
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`the patent, shown highlighted right. The
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`substrate includes a first etchable layer, which
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`Liu also calls a “substrate” 18 (blue). The
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`layer above the etchable layer is an etch-stop
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`layer, called the “window layer” 4 (green). The top layer is the wafer, made up of
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`“absorber” and “channel layers” 6 and 8 (yellow). (Ex. 1003, 3:63 – 4:19)(Ex.
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`1002, ¶73). Liu describes the process of furnishing the above-described substrate
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`by growing layers 4, 6 and 8 onto a GaAs substrate 18. These layers are liquid
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`phase epitaxial (LPE) layers. (Ex. 1003, 3:61-65)(Ex. 1002, ¶74).
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`Liu explains that once the epitaxial layers are in place, microelectronic circuits
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`are formed on the wafer, channel layer 8:
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`“As shown in step C of FIG. 2, a CCD
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`circuit 10 is fabricated on channel layer 8
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`using standard photolithographic
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`techniques. In general, this requires: (1)
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`formation of ohmic contacts 20, (2)
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`channel isolation 22 by proton
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`bombardment, (3) deposition of Schottky barrier gates 24, (4)
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`deposition of vias 28, and (5) deposition of interconnects 30.” (Ex.
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`1003, 4:21-27)(Ex. 1002, ¶75).
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`These circuits are formed on the wafer (channel layer 8), and also extend to the
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`wafer, for example, the ohmic contact 20 shown highlighted red in Fig. 2C above.
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`(Ex. 1002, ¶76).
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`The next step disclosed in Liu is attachment of a
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`support 12 (highlighted orange in Fig. 2F, here), or
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`“second substrate” as it is called in the ’678 patent.
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`(Ex. 1002, ¶77). Liu explains that the second substrate
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`12 can also have a microelectronic circuit element, and
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`that electrical contact can be made between the
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`microelectronic circuit elements in the first and second substrates:
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`“In a third embodiment of the invention, support 12 is a GaAs or Si
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`chip, having its own circuit for signal conditioning and
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`amplification already fabricated and with appropriate connecting
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`pads aligned to the corresponding pads on circuit layer 10. This will
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`provide a compact, high signal-to-noise ratio two-chip combination
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`with considerable saving in weight and space for external electronics.”
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`(Ex. 1003, 3:43-50)(Emph. add.)(Ex. 1002, ¶78).
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`Once the second substrate, support 12, has been attached, Liu’s etchable layer is
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`no longer needed and can be removed. The etch-stop layer (window layer 4)
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`serves as a stop to the etching process, as Liu explains:
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`“After the support 12 has been bonded to the
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`device GaAs substrate 18 is no longer needed
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`for support and it is etched completely away
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`down to window layer 4 as shown in step G of
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`FIG. 2.” (Ex. 1003, 4:53-56)(Ex. 1002, ¶79).
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`Liu etches the substrate 18 using a selective etchant
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`that removes the GaAs substrate 18 without removing the (GaAl)As window layer
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`4. (Ex. 1003, 4:56-58)(Ex. 1002, ¶¶130-131).
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`Liu thus describes the same process as claimed in the ’678 patent, using a
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`substrate that will later be removed, for the same reasons articulated in the ’678
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`patent, including stability during the manufacturing process:
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`“Although the finished device does not have a substrate, the growth of
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`the epitaxial layers during fabrication requires that a substrate be used.
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`A window layer, an absorber layer, and a CCD channel layer (in this
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`order) are grown epitaxially on a substrate. A CCD circuit is then
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`fabricated on the channel layer and a support is mounted on the
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`channel layer. The substrate layer is no longer needed either to grow
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`the epitaxial layers or to support the device, and it is etched off.” (Ex.
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`1003, 2:26-34)(Ex. 1002, ¶80).
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`Liu further teaches that once the substrate 18 is
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`removed, the etch-stop layer 4 can also be etched,
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`“patterned”, to allow for connections to the
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`circuit. (Ex. 1003, 4:59-67)(Ex. 1002, ¶81). This
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`also commonly referred to as “back-side etching”.
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`or
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`is
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`(Ex. 1002, ¶81). Fig. 1 of Liu, right, shows this patterning around the border of the
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`microelectronic device (inverted from Fig. 2). This back-side etching allows for
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`electrical connections to the CCD circuit through exposed interconnect pads 16,
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`highlighted red here. (Ex. 1003, 4:59-66) (Ex. 1002, ¶82).
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`B. Overview of Wen
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`Wen discloses a method for making semiconductor devices with thin active
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`regions of semiconductor material. (Ex. 1004, 1:36-38)(Ex. 1002, ¶227). “More
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`particularly, the present invention relates to a method of selectively etching away a
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`semiconductor substrate to leave a thin region of semiconductor material on a
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`support.” (Ex. 1004, 1:38-42)(Ex. 1002, ¶227).
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`Wen’s stated intention is to overcome the same problems involved in
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`manufacturing microelectronic circuit elements articulated in the ’678 patent:
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`“High frequency semiconductor devices and integrated circuits
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`require high quality, ultra-thin, uniformly thick bodies of a
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`semiconductor material on a metallic or electrically insulating
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`support. A problem in making such devices is to achieve the ultra-
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`thin, less than about 10 microns, bodies of the semiconductor
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`material. To handle a large wafer of the semiconductor material
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`which is this thin is very difficult since such a thin wafer is very
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`brittle and subject to be easily broken.” (Ex. 1004, 1:43-51)(Emph.
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`add.)(Ex. 1002, ¶228).
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`To solve this problem, Wen teaches the same process as described in Liu and
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`claimed in the ’678 patent, summarized in Wen’s specification and Fig. 1:
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`“Semiconductor devices of the type having a thin
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`active region of the semiconductor material on the
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`support body are made by depositing the active
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`region on a silicon substrate with a thin barrier
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`layer of highly doped p-type silicon being
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`provided between the active region and the
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`substrate. The support body is applied to the
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`active region and the substrate is removed by
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`etching in a solution of potassium hydroxide and
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`1-propanol. The etching solution removes the
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`substrate but stops at the barrier layer leaving a
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`smooth, flat surface. The barrier layer can either used as part of the
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`semiconductor device being made or easily removed with a suitable
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`etchant.” (Ex. 1004, 1:15-27)(Ex. 1002, ¶229).
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`Like Liu and the ’678 patent, Wen starts with a three-layer substrate, shown in
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`Fig. 2, here. Wen calls its etchable layer a
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`“substrate” 12 (highlighted blue); its etch-stop
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`layer a “barrier” layer 14 (green); and its wafer a
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`“region” or “active region” 16 (yellow). (Ex.
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`1004, 2:54-71)(Ex. 1002, ¶230). The wafer is “a region 16 of single crystalline
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`silicon which forms the active portion of the semiconductor devices being made.”
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`(Ex. 1004, 2:69-71)(Ex. 1002, ¶230). Wen also discloses the formation of a
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`microelectronic circuit elements on the wafer (active region) 16, including
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`transferred electron effect devices, integrated circuits, and high frequency
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`semiconductor devices. (Ex. 1003, 3:2-11)(Ex. 1002, ¶231).
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` Wen teaches that, like in the ’678 patent, “a support body 18 of an electrical
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`insulating or semi-insulating material, such as glass, quartz or a high resistance
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`semiconductor material” (highlighted orange in Fig. 2 above) is added to the wafer
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`side of the substrate. (Ex. 1004, 3:12-14, 3:41-46). This is the same as the
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`“second substrate” in the ’678 patent. (Ex. 1002, ¶232). Following attachment of
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`the second substrate (support 18), substrate 12 is etched down to etch-stop (barrier)
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`layer 14. (Ex. 1004, 3:47-50)(Ex. 1002, ¶233). Wen explains:
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`“Thus, by having the barrier layer 14 between the substrate 12 and the
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`active region 16, the substrate 12 will be etched away relatively fast
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`but the etching will substantially stop when all of the substrate 12 is
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`removed and the barrier layer 14 is reached.” (Ex. 1004, 4:36-40)(Ex.
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`1002, ¶233).
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`Wen further explains that, “[a]fter the substrate [etchable layer] 12 is removed,
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`the device 10 comprises the support body 18 having the active silicon region 16 on
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`a surface thereof and the barrier layer 14 over the active region 16.” (Ex. 1003,
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`4:52-55). And once the etchable layer is removed, an electrical connection can be
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`formed through the etch-stop layer:
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`“if the barrier layer 14 is not desired, it can be easily removed by
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`etching in a nitric and hydrofluoric acid mixture. Since the barrier
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`layer 14 is very thin it can be etched away quickly leaving the active
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`region 16 with a flat, smooth surface. The device 10 can then be
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`processed to complete the semiconductor device being made. For
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`example, metal contacts can be applied, to form an integrated circuit
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`the active region 16 may be provided with areas of different
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`conductivity types by diffusion or ion implantation to form the desired
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`circuit...” (Ex. 1003, 4:63-72)(Ex. 1002, ¶234).
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`C. Overview of Black
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`Black describes a method for making “Ultra-Thin Microelectronic Pressure
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`Sensors”. (Ex. 1007, Title)(Ex. 1002, ¶142). Black discloses starting with the
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`same three-layer substrate as disclosed in Liu and claimed in the ’678 patent. This
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`U.S. Pat. No. 5,591,678
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`substrate is shown highlighted in Fig. 1,
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`right. Black calls the overall substrate a
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`“wafer” 20; its etchable layer a silicon carrier “substrate” 21; its etch-stop layer an
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`“epitaxial layer” 22; and its wafer the “upper epitaxial layer” 23. (Ex. 1007, 2:39-
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`2:60)(Ex. 1002, ¶¶143-144). Black also refers to its etch-stop layer simply as
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`“etch-stop 22”. (Ex. 1007, 6:16-25)(Ex. 1002, ¶143). The microelectronic circuit
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`elements in Black are “resistor array forms,” shown at 28 in Fig. 9 below. (Ex.
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`1007, 3:1-7)(Ex. 1002, ¶143).
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`As also shown in Fig. 9, right, Black attaches its first substrate (inverted here)
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`to a second substrate (highlighted orange), and
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`removes the etchable layer 21 to the etch-stop
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`layer 22. (Ex. 1007, 5:22-28, 6:15-17)(Ex.
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`1002, ¶¶145-146). Fig. 9 shows both the
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`patterning of the etch-stop layer 22 and forming electrical connections through the
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`etch-stop layer 22 to the aluminum bonding pad 32, through windows 51. (Ex.
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`1007, 6:17-28)(Ex. 1002, ¶147).
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`D. Summary of the Prior Art
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`Liu, Wen and Black thus each describe the fundamental steps claimed in the
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`’678 patent: starting with a three-layer substrate with an etchable layer, an etch-
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`stop layer and a wafer; forming a microelectronic circuit element in and on the
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`U.S. Pat. No. 5,591,678
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`exposed side of the wafer; attaching a second support substrate to the exposed side;
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`removing the etchable layer down to the etch-stop layer; and forming electrical
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`connections through the etch-stop layer to the microelectronic circuit elements.
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`The ’678 patent claims also include limitations relating to basic teachings
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`known in the art for the making of microelectronic circuit elements, such as
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`identifying known chemical materials and thicknesses to be used for the three
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`layers of the substrate (claims 5, 12-18); specifying the degassing and curing of the
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`epoxy used to bond the second substrate to the first (claims 8 and 18); and
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`identifying a separate structure used to hold the first during processing (claim 9).
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`As set forth herein, these limitations were also well-known by those of skill in the
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`art long before the claimed invention of the ’678 patent.
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`III. CLAIM CONSTRUCTION & LEVEL OF SKILL IN THE ART
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`The ’678 patent is expired. For an expired patent, the PTAB gives claims “their
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`ordinary and customary meaning, as would be understood by a person of ordinary
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`skill in the art, at the time of the invention, in light of the language of the claims,
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`the specification, and the prosecution history of record”. Cisco Systems, Inc. v.
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`AIP Acquisition, LLC, Case No. IPR2014-00247, Paper 20 (Order on Conduct of
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`Proceedings) at pp. 2-3 (PTAB July 10, 2014).
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`A. Claims 1, 3, 6-7, 11, 13, 15 — “Microelectronic Circuit Element”
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`Claims 1, 3, 6-7, 11, 13 and 15 use the term “microelectronic circuit element”.
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`U.S. Pat. No. 5,591,678
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`The ’678 patent describes this term as follows:
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`“As used herein, the term ‘microelectronic circuit element’ is to be
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`interpreted broadly, and can include active devices and passive
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`structure. For example, the microelectronic circuit element can
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`include many active devices such as transistors. Alternatively, it may
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`be simply a patterned electrical conductor layer that is used as an
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`interconnect between other layers of structure in a stacked three-
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`dimensional device, or may be a sensor element.” (Ex. 1001, 4:43-52).
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`The term “microelectronic circuit element” therefore should mean “active devices
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`or passive structures useful for circuits”. (Ex. 1002, ¶67).
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`B. Claims 1, 11, 13 — “Etching,” “Etchable Layer” and “Etch-Stop
`Layer”
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`Independent claims 1, 11 and 13 use the terms “etching,” “etchable layer” and
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`“etch-stop layer.” The Collins Dictionary of Electronics defines “etching” as “the
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`dissolving of material by a chemical process”. (Ex. 1010, p. 152). This is
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`consistent with the ’678 patent’s use of the term. (Ex. 1001, 5:52-6:3)(Ex. 1002,
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`¶68).
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`The ’678 patent explains the terms “etchable layer” and “etch-stop