UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_______________
`
`
`
`SONY CORPORATION,
`Petitioner
`
`v.
`
`RAYTHEON COMPANY,
`Patent Owner
`_______________
`
`Case: IPR2015-01201
`
`Patent 5,591,678
`_______________
`
`DECLARATION OF EUGENE A. FITZGERALD
`
`
`
`
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`Raytheon2032-0001
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`Sony Corp. v. Raytheon Co.
`IPR2016-00209
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`

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`
`
`TABLE OF CONTENTS
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`
`
`I.
`
`II.
`
`Introduction ................................................................................................. 1
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`Qualifications and Compensation ................................................................ 1
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`III. Materials Considered ................................................................................... 5
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`IV. Level of Ordinary Skill in the Art ................................................................ 5
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`V. My Understanding of Patent Law ................................................................ 6
`A.
`Burden of Proof ................................................................................. 7
`B.
`Anticipation ....................................................................................... 7
`C.
`Obviousness ....................................................................................... 7
`D.
`Claim Construction ............................................................................ 9
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`1.
`
`2.
`
`3.
`
`“Etching” .................................................................................... 9
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`“Etchable Layer” and “Etch-Stop Layer” ...................................10
`
`“Etching Away the Etchable Layer of the First Substrate
`Down to the Etch-Stop Layer” ..................................................11
`
`VI. Relevant Time Frame ..................................................................................12
`
`VII. Technical Background ................................................................................13
`A.
`Integrated Circuit Manufacturing ......................................................13
`
`1. Moore’s Law .............................................................................13
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`2. Advanced Packaging .................................................................16
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`3. Microelectronic Processes .........................................................18
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`4. Material Removal Processes ......................................................19
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`VIII. Predictability in the Art ...............................................................................31
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`
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`i
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`Raytheon2032-0002
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`IX. The ’678 Patent ...........................................................................................34
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`X.
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`Prosecution History of the ’678 Patent ........................................................34
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`XI. The ’678 Patent Requires Etching to Remove a Portion of its
`Substrate, and Does Not Disclose CMP for This Purpose ...........................35
`
`XII. CMP is Not Etching, Does Not Include Etching and Therefore, CMP
`is Not “Similar” to Etching .........................................................................38
`A.
`CMP and Etching Have Different Selectivity ....................................40
`B.
`CMP and Etching Result in Different Roughness of Substrates ........43
`C.
`CMP and Etching Result in Different Degrees of
`Contamination ..................................................................................45
`CMP and Etching Speeds Are Different ............................................46
`CMP and Etching Involve Different Uniformity of Removal
`Across the Wafer ..............................................................................48
`
`D.
`E.
`
`XIII. Prior Art Analysis .......................................................................................49
`A.
`Bertin Does Not Anticipate Claims 1, 6, 7, 10 and 11
`(Ground 1) ........................................................................................50
`
`B.
`
`1. Bertin is Not Prior Art ...............................................................50
`The Combination of Bertin and Morimoto Would Not Render
`Claims 5 and 12-13 Obvious (Ground 2) ..........................................51
`
`1. Bertin is Not Prior Art ...............................................................51
`
`2. Morimoto Does Not Disclose Etching .......................................51
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`3. Morimoto Does Not Disclose an Etch-Stop Layer .....................53
`
`C.
`
`4. Claim-by-Claim Analysis (Claims 5, 12 and 13)........................59
`The Combination of Morimoto With Any of the So-Called
`“CMP / Etching References” Would Not Render Claims 1-2, 4-
`5, 10, 13-14, and 16-17 Obvious (Ground 4) .....................................61
`
`
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`ii
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`Raytheon2032-0003
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`1. Several of the So-Called “CMP / Etching References” are
`Not Prior Art .............................................................................61
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`2. The “CMP / Etching References” Would Not be Combined
`With Morimoto .........................................................................62
`
`3. Claim Analysis ..........................................................................78
`D. Morimoto With Any of the “CMP / Etching References” in
`Combination With Oldham Would Not Render Claims 8 and 18
`Obvious (Ground 5) ..........................................................................81
`E. Morimoto With Any of the “CMP / Etching References” in
`Combination With Bertin Would Not Render Claims 3 and 15
`Obvious (Ground 6) ..........................................................................83
`
`1. Bertin is Not Prior Art ...............................................................83
`
`XIV. Conclusion ..................................................................................................83
`
`
`Appendix 1 – Curriculum Vitae
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`Appendix 2 – List of Documents Considered
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`iii
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`Raytheon2032-0004
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`I.
`1.
`
`Introduction
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`The facts set forth below are known to me personally, and I have firsthand
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`knowledge of them.
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`2.
`
`I make this Declaration in support of the Patent Owner’s response to the
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`Petition for inter partes review (“IPR”) of U.S. Patent No. 5,591,678 (“the ’678
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`Patent”).
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`3.
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`I have been retained by Steptoe & Johnson LLP on behalf of the Patent
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`Owner, Raytheon Company.
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`4.
`
`I have been asked to provide my technical review, analysis, insights, and
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`opinions on the materials I have reviewed in this case related to the ’678 Patent,
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`including the references cited in Petitioner’s grounds of rejection set forth in
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`Petition No. IPR2015-01201 for Inter Partes Review of the ’678 Patent
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`(“Petition”), and the scientific and technical knowledge regarding the same subject
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`matter at the time of the inventions disclosed in the ’678 Patent.
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`II. Qualifications and Compensation
`I am over the age of eighteen and I am a citizen of the United States.
`5.
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`6.
`
`I have summarized in this section my educational background, career
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`history, and other relevant qualifications. My curriculum vitae, including my
`
`qualifications, a list of the publications that I have authored during my technical
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`
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`1
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`Raytheon2032-0005
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`career, and a list of the cases in which, during the previous four years, I have
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`testified as an expert at trial or by deposition, is attached to this declaration as
`
`Appendix 1.
`
`7.
`
`I received a B.S.
`
`in Materials Science and Engineering from the
`
`Massachusetts Institute of Technology in 1985, a M.S. in Materials Science and
`
`Engineering from Cornell University in 1987 and a Ph.D. in Materials Science and
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`Engineering from Cornell University in 1989.
`
`8.
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`From 1988 to 1994, I worked as a research scientist at AT&T Bell
`
`Laboratories in Murray Hill, N.J., in the Materials Science and Engineering
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`Department. While at AT&T Bell Laboratories, I conducted fundamental research
`
`in semiconductor materials and devices.
`
`9.
`
`From 1994 to 2000, I was an Associate Professor at MIT. From 2000 to the
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`present, I have been a Professor of Materials Science at MIT, in the Materials
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`Science and Engineering Department. I am currently the Merton C. Flemings-
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`Singapore-MIT-Alliance Professor of Materials Science and Engineering and
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`currently the Lead Principal Investigator of MIT SMART LEES (Singapore-MIT
`
`Alliance for Research and Technology, MIT’s Research Center in Singapore, Low
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`Energy Electronics Systems), where I manage the fifty-million-dollar research
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`program.
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`2
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`Raytheon2032-0006
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`10. My specialization is electronic materials, devices, and circuits, and I have
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`operated as a researcher, scientist, and entrepreneur in this area since the mid-
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`1980s. I researched and innovated in the areas related to the critical aspects of the
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`claimed inventions in question, such as semiconductor manufacturing and
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`processing techniques, including use of various etching methods as well as use of
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`chemo-mechanical polishing (CMP). The vast majority of my own inventions
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`involve such processing of materials and electronic devices, including the novel
`
`use of CMP (as only a portion of examples, United States Patent Nos. 6,171,936;
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`6,291,321; and 7,081,410).
`
`11.
`
`I have received numerous honors and awards for my work. For example, I
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`was a co-recipient of the Institute of Electrical and Electronics Engineers (“IEEE”)
`
`2011 Andrew S. Grove Award for outstanding contributions to solid state devices
`
`and technology including “seminal contributions to the demonstration of Si/Ge
`
`lattice mismatch strain engineering for enhanced carrier transport properties in
`
`MOSFET devices,” the IEEE 2004 EDS George Smith Award for Best Paper for a
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`paper I co-authored entitled “Fully Depleted Strained-SOI n- and p- MOSFETs on
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`Bonded SGOI Substrates and Study of the SiGe/BOX Interface,” and the TMS
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`1994 Robert Lansing Hardy Medal Award for exceptional promise of a successful
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`career in the field of metallurgy and materials science.
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`3
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`Raytheon2032-0007
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`12.
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`I am the founder, co-founder or a founding team member of the following
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`companies and organizations: AmberWave Systems Corporation (a company
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`focused on strained silicon semiconductor technology); Contour Semiconductor (a
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`company focused on a unique semiconductor fabrication process for non-volatile
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`memory); 4Power LLC (manufacturer of high efficiency, low cost solar cells using
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`III-V thin films on silicon substrates); Paradigm Research LLC (commercializing
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`true monolithic III-V/Si CMOS integrated circuits); The Innovation Interface (a
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`not-for-profit organization that trains future innovators through university-
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`corporate innovation projects); and The Water Initiative (creating customized
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`point-of-drinking water solutions and scaling those solutions through micro-
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`entrepreneurs, developers and government entities).
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`13.
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`I have authored or co-authored more than 200 scientific publications. I am
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`named as an inventor or co-inventor on over 90 issued patents. Most of these
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`publications and patents relate to the growth of semiconductor materials. I have
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`supervised at least 30 doctoral candidates submitting thesis papers relating to
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`semiconductor materials and device processing.
`
`14.
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`I am being compensated for my time at the rate of $500 per hour for my
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`work in connection with this matter. The compensation is not dependent in any
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`4
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`Raytheon2032-0008
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`way on the contents of this Declaration, the substance of any further opinions or
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`testimony that I may provide, or the ultimate outcome of this matter.
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`III. Materials Considered
`I have carefully reviewed the ’678 Patent and its file history. I have also
`15.
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`reviewed the references cited in the Petition (Paper No. 2) and the supporting
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`declaration of Dr. Blanchard (Ex. 1002). I have also reviewed the parties’ claim
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`construction positions from the related district court proceedings in Raytheon v.
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`Samsung Elecs. Co., Ltd. et al., Case No. 2:15-cv-00341 (E.D. Tex.) (Dkt. Nos. 90,
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`and 116-1) (Ex. 2042) and the Declaration of Dr. A. Bruce Buckman submitted by
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`Patent Owner as part of that briefing (Dkt. No. 100-2) (attached to Ex. 2037).
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`16. For convenience, all of the sources that I considered in preparing this
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`declaration are listed in Appendix 2.
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`IV. Level of Ordinary Skill in the Art
`I have been informed that my analysis of the interpretation of the claims of
`17.
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`the ’678 Patent must be undertaken from the perspective of a person possessing
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`ordinary skill in the art of the ’678 Patent. I have reviewed Dr. Buckman’s
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`declaration submitted as part of the district court claim construction briefing, as
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`noted above, and Dr. Buckman opines therein that a person of hypothetical
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`ordinary skill in the art (PHOSITA) at the time of the ’678 Patent would have been
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`5
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`Raytheon2032-0009
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`an individual with a Bachelor’s degree in electrical engineering, materials science,
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`or the like, with advanced classwork or industry experience in fabrication of
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`microelectronic devices. (Ex. 2037 at ¶14.) I agree with this opinion and hereby
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`adopt it herein. I possess these qualifications, and I have considered the issues
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`herein from the perspective of a person of ordinary skill in the art.
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`18.
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`I have also reviewed Dr. Blanchard’s proposal as to the level of ordinary
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`skill, which does not materially differ from Dr. Buckman’s opinion noted above.
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`(See Ex. 1002 at ¶ 49.) Thus, my opinions and assertions contained herein would
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`not differ if the Board adopted Dr. Blanchard’s proposal or Dr. Buckman’s.
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`However, I disagree with Dr. Blanchard’s statement that a PHOSITA “would have
`
`considered CMP and etching to be similar techniques.” (Id. at ¶ 52.) This
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`statement is incorrect for the reasons set forth herein.
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`V. My Understanding of Patent Law
`I am not an attorney but I have had the concept of patentability explained to
`19.
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`me. I understand that a patent claim can be unpatentable under the United States
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`patent laws for various reasons, including, for example, anticipation or obviousness
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`in light of the prior art. In arriving at my opinions, I have applied the following
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`legal standards and analyses regarding patentability.
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`6
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`Raytheon2032-0010
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`A. Burden of Proof
`I understand that Petitioner has the burden to prove a proposition of
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`20.
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`unpatentability by a preponderance of the evidence. I also understand that this is a
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`lower standard than the clear and convincing evidence standard that is required to
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`prove unpatentability in patent litigation before a district court.
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`B. Anticipation
`I understand that a claim is anticipated by a prior art reference if the prior art
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`21.
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`reference discloses every element in the claim. Such a disclosure can be express (it
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`says or shows it), or it can be inherent (the element must necessarily be there even
`
`if the prior art does not say it or show it). If the claim is anticipated, the claim is
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`unpatentable.
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`22.
`
`I understand that the first step in an anticipation analysis is to construe the
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`claim, and the second step is to compare the construed claim to the prior art
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`reference.
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`C. Obviousness
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`23.
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`I understand that a patent claim may be unpatentable for obviousness even if
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`it is not anticipated by the prior art. I understand that a patent claim is obvious if
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`the differences between the claimed intervention and the prior art are such that the
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`subject matter of the claimed invention, as a whole, would have been obvious to
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`7
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`Raytheon2032-0011
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`one of ordinary skill in the art at the time the invention was made. If the claim is
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`obvious, the claim is unpatentable.
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`24.
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`I understand that before an obviousness determination is made, the level of
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`ordinary skill in the art must be considered, and the scope and content of the prior
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`art must be considered, as well. I understand that to determine the scope and
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`content of prior art, one must determine what prior art is reasonably pertinent to the
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`particular problem the inventor faced. I understand that prior art is reasonably
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`pertinent if it is in the same field as the claimed invention, or is from another field
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`that a person of ordinary skill in the art would look to in trying to solve the
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`problem.
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`25.
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`I understand that a patent claim maybe be obvious if the prior art would have
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`suggested, motivated, or provided a reason to one of ordinary skill in the art to
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`combine certain prior art references to arrive at the elements of the claim. I also
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`understand that one can look at interrelated teachings of multiple patents, the
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`effects of demands known to the design community or present in the marketplace,
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`and the background knowledge possessed by a person having ordinary skill in the
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`art—all in order to determine whether there was an apparent reason to combine the
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`known elements in the fashion claimed by the patent at issue. I further understand
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`that a person of ordinary skill is a person of ordinary creativity, not an automaton.
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`8
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`Raytheon2032-0012
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`This person of ordinary creativity works in the contexts of a community of
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`inventors and of the marketplace. The obviousness inquiry needs to reflect these
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`realities within which inventions and patents function. In order to arrive at a
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`conclusion that an invention is obvious, it can be helpful to identify a reason that
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`would have prompted a person of ordinary skill in the relevant field to combine the
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`elements in the way the claimed invention does.
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`D. Claim Construction
`26. For the purposes of my opinions related to the issue of patentability of the
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`’678 Patent, I have been informed that, because the ’678 Patent is now expired and
`
`its claims cannot be amended in this proceeding, the claims of the ’678 Patent are
`
`to be interpreted using the same claim construction standards as are applied in a
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`district court proceeding, which I understand are generally their ordinary and
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`customary meaning as understood by a person of ordinary skill in the art at the
`
`time of invention. Below I summarize the claim constructions relevant to my
`
`analysis herein.
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`“Etching”
`
`1.
`I note that in the parties’ Joint Claim Construction Chart, Petitioner agreed
`
`27.
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`with the Patent Owner that the definition of “etching” is “removing material with
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`9
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`Raytheon2032-0013
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`an etchant.” (Ex. 2042 at p. 31.) I agree with this construction and will adopt and
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`apply it herein.
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`28. Dr. Blanchard concludes that the term “etching” should be construed to
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`mean “the dissolving of material by a chemical process.” (Ex. 1002 at ¶ 61.) Dr.
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`Blanchard’s definition is at least partially consistent with the parties’ agreed-upon
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`definition, insofar as “removing material with an etchant” (the agreed-upon
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`construction) necessarily implicates using a chemical (e.g. a liquid in wet-etching
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`or a plasma in dry etching) to dissolve and remove material. I also note that Patent
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`Owner submitted a proposed definition for etching in its preliminary statement:
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`“chemically removing a portion of a substrate.” Thus, though I adopt the parties’
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`agreed-upon construction, my analysis herein would not differ if the Board adopted
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`either Dr. Blanchard’s or the Patent Owner’s earlier construction of “etching.”
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`“Etchable Layer” and “Etch-Stop Layer”
`
`2.
`In the district court proceedings, Patent Owner proposes a construction of
`
`29.
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`“etchable layer” as “a portion of the first substrate that is readily etched, relative to
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`the etch stop layer.” (Ex. 2042 at p. 31.) Patent Owner proposes a construction of
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`“etch-stop layer” as “a portion of the first substrate that is etched less readily,
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`relative to the etchable layer.” (Id.) I have reviewed Patent Owner’s arguments in
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`10
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`Raytheon2032-0014
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`support of these constructions and I agree with these constructions and the
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`arguments made in support thereof. Thus, I adopt these constructions herein.
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`30. Dr. Blanchard asserts that the terms “etchable layer” and “etch-stop layer”
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`“stand in relation to a particular etchant” and that an “etch-stop layer must be more
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`resistant to an etchant than a corresponding etchable layer.” (Ex. 1002 at ¶ 61.)
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`Thus, Dr. Blanchard concludes that “[i]n other words, an ‘etchable layer’ is
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`dissolved rapidly by an etchant, while an ‘etch[-]stop layer’ is dissolved slowly (or
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`not at all by the same etchant).” (Id.) Dr. Blanchard’s definitions appear to be
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`consistent with the Patent Owner’s constructions. Thus, though I adopt the Patent
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`Owner’s constructions, my analysis herein would not differ if the Board adopted
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`Dr. Blanchard’s constructions of “etchable layer” and/or “etch-stop layer.”
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`“Etching Away the Etchable Layer of the First Substrate Down
`3.
`to the Etch-Stop Layer”
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`31.
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`In the district court proceedings, Patent Owner proposes a construction of
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`“etching away the etchable layer of the first substrate down to the etch-stop layer”
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`as “etching the etchable layer to at least the etch-stop layer.” (Ex. 2042 at p. 31.) I
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`have reviewed Patent Owner’s arguments in support of this construction and I
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`agree with this construction and the arguments made in support thereof. Thus, I
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`adopt this construction herein. Neither Dr. Blanchard nor Petitioner proposes a
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`construction of this claim phrase.
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`11
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`Raytheon2032-0015
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`VI. Relevant Time Frame
`I understand that anticipation and obviousness must be evaluated at the time
`32.
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`the invention was made. I understand that the declarations of the inventors of the
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`’678 Patent are being submitted. (Exs. 2015, 2016 and 2017.) I further understand
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`that they have declared that Claims 1-5, 8-10, and 13-18 were conceived and
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`reduced to practice by August 9, 1990 (Exs. 2015, ¶¶ 5-9, 23-26; 2016, ¶¶ 4, 12-13,
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`16-17, 21-22) and that Claims 6-7 and 11-12 were conceived and reduced to
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`practice by June 1991 (Exs. 2016, ¶¶ 5-7, 19-21, 25-32; 2017, ¶¶ 4-6, 14-22.). I
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`will assume for the purpose of this declaration that August, 1990 was the date the
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`inventions in Claims 1-5, 8-10, and 13-18 were made, and that June 1991 was the
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`date the inventions in Claims 6-7 and 11-12 were made, with the understanding
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`that my testimony will also be applicable to some time prior to those dates,
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`approximately the early 1990s. I may refer to this time period as the “relevant time
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`frame,” and my testimony concerning obviousness is directed to this time frame,
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`even if I occasionally do not explicitly use a past tense.
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`33.
`
`I also understand that the front page of the ’678 Patent (left column, field
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`“[63] Continuation of Ser. No. 6,120”) indicates the first application related to the
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`’678 Patent was filed on January 19, 1993. (Ex. 1001.) For purposes of my
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`declaration and analysis, whether the Board decides to accept the August 1990 and
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`12
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`Raytheon2032-0016
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`June 1991 invention dates or the January 19, 1993 filing date of the earlier-filed
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`application is inconsequential. The analysis presented herein also applies if the
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`Board decides that the ’678 Patent has a later date of invention and therefore the
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`relevant time frame is in 1993 rather than in 1990.
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`VII. Technical Background
`A.
`Integrated Circuit Manufacturing
`1. Moore’s Law
`34. To understand the invention of the ’678 Patent, it is important to consider
`
`the status of the miniaturization of integrated circuits at the time of the invention in
`
`the early 1990s. The progress in miniaturization is central to the context of the
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`invention since the ’678 Patent describes a method for closely integrating silicon
`
`integrated circuits into a more complex and compact integrated system, i.e.
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`miniaturization of integrated electronic systems.
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`35.
`
`In the 1950s when transistors (also called “solid state amplifiers”, an
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`evolutionary
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`jump from existing vacuum
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`tube
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`technology) first became
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`commercially practical, designers of electronic products composed of such
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`13
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`Raytheon2032-0017
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`components realized the “tyranny of numbers” would limit that miniaturization.1
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`The phrase refers to the fact that the components would need many electrical
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`connections to other components and, as the components got smaller, such
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`interconnection in the desired systems could not be practically accomplished by
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`hand. The ability to place many transistors next to each other simultaneously in
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`the same piece of semiconducting silicon allowed for these transistors to be
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`connected to each other in one step by depositing metal films across the piece of
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`semiconductor and etching the film such that metal line traces connected
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`transistors to each other in desired patterns. This processing was known as “planar
`
`processing” 2 and it formed modern “integrated circuits.” Over time, layers of
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`metal line traces separated by dielectric insulation were applied, building a planar
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`network of metal lines interconnecting the various transistors to each other. Many
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`processes across silicon wafers were developed to manufacture many such
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`integrated circuits in a silicon wafer, and in batches of silicon wafers in
`
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`1 “The Technological Impact of Transistors”, J.A. Morton and W.J. Pietenpol,
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`Proceedings of Institute the of Radio Engineers (1958) 955. (Ex. 2020.)
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`2 U.S. Patent No. 2,981,877. (Ex. 2021.)
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`14
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`Raytheon2032-0018
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`production.3 Thus, planar processing produces transistors in a plane, that is, the
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`plane of the starting silicon wafer blank.
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`36. These methods of producing integrated circuits resulted in an economic
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`feedback loop, in which investment in equipment and processes to produce
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`evermore increased transistor densities, and therefore, integrated circuit density,
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`resulted in an exponential rise in manufactured transistor density. In other words,
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`more and more transistors were being rapidly squeezed into smaller areas in the
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`plane of the wafer. This two-dimensional (2-D) techno-economic law, in which
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`transistor density in integrated circuits exponentially increases with time in the
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`silicon wafer-plane, is referred to as Moore’s Law, named after an Intel founder
`
`that recognized the trend in 19654 and updated it in 1975.5 Since Moore’s Law is
`
`exponential, it dominated the design of integrated systems from the 1960s and into
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`
`3 “VLSI Technology,” S.M. Sze, McGraw-Hill, New York (1983). (Ex. 2022.)
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`4 “Cramming more components onto integrated circuits”, G.E. Moore, Electronics
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`38 (1965). (Ex. 2023.)
`
`5 “Progress in Digital Integrated Electronics”, G.E. Moore, International Electron
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`Devices Meeting, IEEE, 1975, pp. 11-13. (Ex. 2024.)
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`the new millennium. Thus, at the time of the invention, the central driving force
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`for miniaturization was this 2-D integration. Integrating pieces of silicon in three
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`dimensions, for the majority of those creating integrated systems, was unnecessary
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`at the time of invention, since at that time Moore’s Law reliably allowed a much
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`higher degree of integration in-plane at very low cost, year after year.
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`Advanced Packaging
`2.
`37. Moore’s Law resulted in a standardized packaging industry in which the
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`integrated circuit could be mounted, and connections from the integrated circuit to
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`the pins of the package could be accomplished inexpensively. The package
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`requirements are minimized by the progress of Moore’s Law: increased transistor
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`density also decreased power use per function, resulting in thermal requirements
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`that could be managed with evolutionary package development.
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`38. The ’678 Patent describes methods of three-dimensional (3-D) integration,
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`in which integrated circuits processed from methods used in microelectronic
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`processing3 can be stacked in the dimension perpendicular to the 2-D plane of
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`Moore’s Law microelectronic fabrication.6 At the time of invention, these methods
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`6 “3-D Integration for VLSI Systems”, C.S. Tan, K.N. Chen, S.J. Koester, Pan
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`Stanford Publishing (2012). (Ex. 2025.)
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`were ahead of their time and forward-looking since chip design and Moore’s Law
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`were making such rapid progress that conventional low-cost silicon packaging (in
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`2-D) was sufficient. 3-D would become most significant when Moore’s Law no
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`longer delivered progress in 2-D that scaled with the goals of integrated systems.
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`Indeed, 3-D has gained importance as Moore’s Law has slowed and now does not
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`deliver the required increases demanded by integrated systems, and hence the
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`importance of the ’678 Patent has increased as manufacturers have increasingly
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`applied such methods of 3-D integration.
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`39. The defense industries were leaders in much of the advanced packaging
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`industry and 3-D integration due to their need to miniaturize ahead of the
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`commercial capability, but their defense customers could support the costs. The
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`’678 Patent was born from such early investigations into increasing component and
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`circuit density. As Moore’s Law has slowed today, advanced 3-D packaging is
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`deployed more commonly underscoring the significance and early timing of
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`the’678 Patent.
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`40. The groundbreaking methods disclosed in the ’678 Patent were driven by
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`possible new configurations of semiconductors that would transform the field of
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`image processing, important in early defense applications. Specifically, exposing
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`the backside of a chip (through the transfer, flip and etch methods described in the
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`’678 Patent) would allow electronics to be placed behind an image sensor. This
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`would allow for higher pixel density (i.e., higher megapixel rating) in a smaller
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`footprint. Such a configuration also allows better low-light performance (because
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`the light photons don’t have to navigate through a mesh of wires in a back-
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`illuminated sensor (BSI) arrangement) and less image signal noise (again, because
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`the electronics are behind the image sensor). Such advanced cameras were a very
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`early example of what we call “3-D” integration today.
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`3. Microelectronic Processes
`41. Many processes were developed to allow modern microelectronics to
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`become a reality.7 General materials deposition and material removal processes
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`are the key to microelectronic fabrication. By combining with photolithography,
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`patterns can be created in multiple layers that form the microelectronic circuit.
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`Layers of a material are deposited across a silicon wafer, and
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`then
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`photolithography is used to pattern that material with a mask, followed by methods
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`to remove areas of the deposited material. This process sequence is repeated
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`7 “Silicon VLSI Technology”, J.D. Plummer, M.D. Deal, P.B. Griffin, Prentice-
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`Hall, NJ (2000); “Silicon Processing”, D.C. Gupta, ASTM Special Technical
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`Publication 804, Philadelphia (1983). (Ex. 2026.)
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`multiple times to create transistors and their interconnections in the plane of the
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`silicon wafer.
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` The deposition and removal processes developed
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`in
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`the
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`microelectronic industry includes:
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` Material Deposition, Modification or Creation
` Evaporation
` Sputtering
` Epitaxy
` Plasma Enhanced Chemical Vapor Deposition (PECVD)
` Oxidation
` Ion Implantation
` Material Removal
` Ion Milling/Sputter
` Dry Etching (Reactive Ion Etching)
` Wet Etching
` Grinding
` Polishing (Lapping)
` Chemo-Mechanical Polishing (CMP)
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`42. These processes are used in creating the initial silicon wafers, the formation
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`of the transistors in the silicon wafer (referred to as the “front-end” of processing),
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`as well as in the interconnection of the transistors to each other (referred to as the
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`“back-end” of processing). Material removal processes are key in all stages of
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`processing.
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`4. Material Removal Processes
`43. Silicon processing can involve many different types of material removal
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`processes. Each process has different performance goals, that is, some processes
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`specialize in quickly removing material, other processes selectively remove a
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`desired material while preserving other materials, reduce the roughness of final
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`surface, and/or may be useful for cleaning a material’s surface. For example, dry
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`etching (reactive ion etching) was developed for some processing steps due to
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`higher reproducibility across the wafer (resulting in higher yi