Failure Mechanisms and Fault Classes for
`CMOS-Compatible Microelectromechanical Systems
`
`A. Castillejo, D. Veychard, S. Mir, J.M. Karam and B. Courtois
`TIMA Laboratory, 46 AV. Fdix Viallet
`38031 Grenoble FRANCE
`
`Abstract
`
`Silicon-compatible micromachining provides a low
`cost monolithic solution for the integration of micro-
`electromechanical systems (MEMS). In the last years,
`C M P (the French MultiProject Wafer Service) has
`made available technological solutions f o r the fabrica-
`tion of CMOS-compatible MEMS. Numerous mono-
`lithic devices have been fabricated using this service.
`The inspection of failed devices has allowed the iden-
`tification of the most typical failure mechanisms and
`design errors f o r this type of MEMS. This valuable in-
`formation, together with a detailed analysis of the fabri-
`cation processes, is used in this paper to provide a clas-
`sification of faults in silicon-compatible MEMS which
`can later be used for fault simulation and testing.
`
`1 Introduction
`
`The constant trend towards higher integration lev-
`els has been a key factor for the success of micro-
`electronic technologies for many years. This trend is
`nowadays being considered for emerging technologies
`producing miniaturized mixed-domain devices called
`MEMS. These devices (sensors, actuators or mechani-
`cal structures) are raising a great deal of interest. They
`touch us in every day applications, such as airbag ac-
`celerometers, blood pressure sensors and thermal ink-
`jet printheads. This is a high-growth market for which
`much research, development and manufacturing activi-
`ties are under development [I]. By incorporating an in-
`creasing number of features and moving towards mono-
`lithic integration, MEM devices are evolving from sim-
`ple components to actual systems. The realization of
`these systems requires, in turn, significant advances in
`computer-aided design, test and manufacturing [2].
`Miniaturization, in conjunction with an ability for
`mixed integration with electronic circuits, are key fac-
`tors for the success of microelectromechanical technolo-
`gies. Monolithic systems which combine in a single chip
`signal processing circuitry with sensors or actuators
`result in lower manufacturing costs and, most often,
`in enhanced performance by improving, for example,
`
`on signal-to-noise ratio. However, higher integration
`levels always raise major test concerns which hamper
`the progress towards developing low cost highly inte-
`grated products. In fact, testing and packaging costs
`for MEMS can already amount for as much as 75% of
`the total cost [l]. As a consequence, research into ad-
`equate ways of testing these mixed-domain monolithic
`systems is now starting [3].
`A functional test approach is cuirrently used for
`small size MEMS [4]. But the development of cost-
`effective tests for larger systems mqy well require a
`move towards test stimuli targeting actual faults. In
`addition, design techniques which take test into ac-
`count as part of the design flow are always important,
`and this requires consideration and simulation of a list
`of faults which represent potential defects. This was
`done for the case of testing microelectronic circuits,
`first with digital circuits, and later with analog and
`mixed-signal devices. For testing ME'MS, similar ap-
`proaches are expected in the coming years. But some
`basic questions for non-electrical parts must first be
`addressed. These include: (a) which are the failure
`mechanisms for non-electrical parts? (1)) in which ways
`do failure mechanisms affect system behavior? and (c)
`can these faulty behaviors be adequaitely represented
`for behavioral simulation?
`In this work, these questions art? addressed for
`MEMS realized using CMOS-compatible technologies.
`These technologies are chosen since they are mature
`and stable, and most pressure sensors and accelerom-
`eters in the market relied on them. They use silicon
`to implement both electronic and mechanical compo-
`nents by means of a CMOS process followed by a mi-
`cromachining postprocess which allows creation and
`thermal isolation of suspended micromechanical parts.
`This postprocess, most normally bulk or surface mi-
`cromachining, is compatible with CMOS fabrication
`processes, and results in microstructures such as mem-
`branes, cavities, masses and bridges which are basic de-
`sign cells for MEMS. Silicon-compatible micromachin-
`ing provides a low cost monolithic solution for the in-
`tegration of MEMS. For this reason, ClVIP (the French
`
`0-7803-5092-8/98 $1 0.00 0 1998 IEEE
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`INTERNATIONAL TEST CONFERENCE
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`Multiproject Wafer Service) adapted a commercial tool
`for the design of MEMS [5] and provided access to these
`technologies. A large number of devices have been cre-
`ated using this service in the last years.
`The aim of this paper is to provide a classification of
`faults which can be useful for developing fault simula-
`tion and test techniques for CMOS-compatible MEMS.
`With this aim, this paper has been organized as follows.
`Previous works in the field of MEMS testing are first
`briefly discussed. A description of material and struc-
`tural properties and actual models which are used for
`behavioral simulation of silicon-compatible MEMS is
`next presented. A detailed discussion of failure mecha-
`nisms which can occur both during the CMOS process
`and during the micromachining postprocess is next pro-
`vided. The study of failed devices has allowed the iden-
`tification of the most typical failure mechanisms and
`design errors for this type of MEMS. Failure mecha-
`nisms can be classified according to the physical prop-
`erties or parameters which are affected, and this gives
`rise to the classification of faults presented [6]. Faults
`are classified, according to their effect on microstruc-
`ture behavior, in two classes which resemble those con-
`sidered for testing analog circuits: catastrophic faults,
`for which electrical, mechanical or thermal misfunction
`prevents any system utilization, and parametric faults,
`for which changes on geometrical or material parame-
`ters alter system performance.
`
`2 Previous Work
`
`The need for high safety applications triggered an
`early interest for built-in self-test and diagnosis of
`MEMS. In [7], the importance of using reliability in-
`dicators for on-chip test monitoring and diagnosis of
`MEMS is shown. Although different approaches are
`presented, there is no evaluation of the most suitable
`techniques. Fault simulation is the most common way
`of evaluating and optimizing a test approach, and this
`is always subject to the use of a fault list. However,
`fault models and fault simulation techniques for MEMs
`are yet to be developed.
`All MEMS work partially in the electronic domain,
`and thus efforts towards transferring test generation
`and verification techniques from the domain of mixed-
`signal integrated circuits to the domain of MEMS are
`under way. In [8], on-line testing for bridge-type mi-
`cromachined pressure and accelerometer sensors is dis-
`cussed. Considering an electrical model of the system,
`fault simulation is applied for selecting test parameters.
`The fault models used are those commonly applied
`for analyzing catastrophic faults in mixed-signal elec-
`tronic circuits, including open, short, bridge and stuck-
`at faults. Generally, reusing some existing algorithms
`
`and techniques from analog and mixed-signal testing
`seems feasible. For example, the algorithm presented
`in [9] for test generation for microelectronic analog fil-
`ters may be useful for micromechanical filters, provided
`that adequate faults are considered. The search for
`valid fault models for non-electrical parts requires a
`detailed study, quantitative and qualitative, of failure
`mechanisms.
`Inductive Fault Analysis (IFA) was largely success-
`ful for identifying realistic failure mechanisms or de-
`fects in VLSI digital circuits [lo]. IFA analysis for ana-
`log and mixed-signal circuits has also attracted many
`research efforts in the last years [ll]. Recently, an IFA-
`like analysis has been considered for surface microma-
`chined sensors [3]. A process simulation tool that maps
`spot contaminations to layout defects is used. These
`contaminations, or unwanted particles in the fabrica-
`tion process, cause defects in the material and struc-
`tural properties of the intended device and result in a
`wide spectrum of faulty behaviors. But a main problem
`with this approach is that, most often, many elements
`which are required for an exact characterization of fab-
`rication processes are unavailable. Alternatively, qual-
`itative studies based on analysis of failed microstruc-
`tures provide a reliable source of information for the
`identification of realistic defects.
`Since electrical simulators are well developed, it is
`common practice to model a microelectromechanical
`device as an equivalent electrical circuit with an un-
`derlying behavior described by means of the same dif-
`ferential equations. Difficulties for using a similar ap-
`proach for fault simulation are shown in [4], in par-
`ticular due to the inadequacy of injecting faults in a
`lumped parameter model which is suitable for repre-
`senting fault-free behavior, but which no longer ac-
`curately represents a faulty behavior. These difficul-
`ties may be encompassed by constructing simulation
`models which ensure fault injectability, and high-level
`hardware description languages such as HDL-A seem
`suitable for modeling mixed-domain devices [12]. In
`addition, [4] shows that some fault types which can
`easily be injected at behavioral level have little or no
`correspondence to realistic defects, strengthening the
`interest for studying realistic failure mechanisms.
`
`3 Physical Modeling
`
`In this section, we summarize material and struc-
`tural properties and parameters which are used to
`build actual models for behavioral simulation and im-
`plementation of CMOS-compatible MEMS. This has
`the twofold aim of providing a brief discussion of this
`kind of devices and their applications, and of describ-
`ing those physical properties and parameters which are
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`involved in the modeling of their behaviour.
`Since the principles governing the manufacturing
`of these systems are an evolution of microelectron-
`ics, superposition of different material layers is used
`for implementation. Mechanical, thermal and electri-
`cal phenomena occurring in these layers are generally
`exploited. An implementation of this type of MEMs
`often consists of two sub-systems: an actual gauge and
`a microstructure which suspends the gauge. Figure 1
`shows the most typical gauges which interface with the
`electrical domain.
`A
`
`W
`L
`R = P m
`p = po(l+ TCR(T - To))
`(a) Resistance
`
`(b) Piezoresistivity
`
`L
`
`(c) Capacitance
`
`mittivity E,, and Seebeck coefficient a.
`Figure l(a) shows how resistivity is affected by tem-
`perature. The temperature coefficient TCR is sig-
`nificantly constant, for metal and polysilicon conduc-
`tors, in large temperature regions. Process parame-
`ters, such as oven temperature, condition the average
`size of silicon grains which greatly impacts resistivity
`values for polysilicon. Typically, thermoresistive prop-
`erties are used for temperature transducers. In Fig-
`ure 1 (b), piezoresistive gauges exploit resistivity varia-
`tions as a result of material deformation under a stress
` Polysilicon is mostly used for these gauges due to .
`~
`1
`
`a good ratio of resistance variation to material strain.
`Being a phenomenon related to resistivity, the piezore-
`sistive coefficient
`for longitudinal deformation is in-
`fluenced by the same process parameters affecting re-
`sistivity, including doping, average size of silicon grains
`and oven temperatures. This phenomenon is mostly
`used for pressure and acceleration sensors. Measures
`of capacitance variation as shown in Figure l(c) are
`often used in accelerometers, pressure sensors and mi-
`croresonators. Finally, Figure l (d) illustrates Seebeck
`phenomenon in which an electrical voltage is generated
`between both ends of a material which are subject to
`a temperature difference. By joining together two dif-
`ferential materials, a thermocouple is obtained for use
`notably in infrared sensors. The Seebeck coefficient a
`is independent of geometrical parameters and linked
`to resistivity. Thus both material properties are af-
`fected by similar process parameters and physical fail-
`ures. Table 1 summarizes design and implementation
`parameters for these gauges.
`desion parameters 11
`
`implementation, parameters
`
`V, = a,(Thot - Tcold) = Q, AT
`Vb = a b AT
`V = (aa - ab)AT = aab AT
`(d) Seebeck effect
`
`Figure 1: Typical gauge principles used for CMOS-
`compatible MEMS.
`Gauges can be either passive, when they experi-
`ence an impedance change under the effect of a phys-
`ical magnitude under measurement (e.g. temperature,
`stress or movement), or active when they generate an
`output electrical voltage or current(e.g. Seebeck phe-
`nomenon). These physical effects are modeled as a
`function of gauge geometry (parameters L, W, t, and
`d) and material properties such as resistivity PO, per-
`
`Table 1: Design and implementation parameters for
`typical gauges.
`
`For the type of MEMS concerned in this work, we
`are interested in mechanical and thermal parameters
`which characterize the microstructures that support
`the gauges. Example parameters are described in Fig-
`ure 2. Seismic masses, which can be formed as superpo-
`sition of several layers, are employed for piezoresistive
`microaccelerometers and micromechanical filters, and
`they are characterized by their ge0metr.y (L, W and t)
`and mass density pm. A damping factor is calculated,
`for example, as a function of air viscosity Y and geomet-
`rical parameters involving the size of the seismic mass
`(with length L, and width Wm), a coefficient a which
`depends on the ratio 2, and the distance do between
`
`mass and encapsulation. The stiffness constant IC of
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`design parameters
`m
`b
`
`implementation parameters
`L m 1
`t m I wm I
`Pm
`I Wm I dn
`I
`L,
`
`Table 2: Design and implementation parameters for
`CMOS-compatible microstructures.
`
`4 Failure Mechanisms
`
`Failure mechanisms or defects which can occur dur-
`ing fabrication are next described. Defects occurring
`during the CMOS process are distinguished from de-
`fects occurring during micromachining.
`
`4.1 During CMOS process
`
`For this description, the AMS CMOS 1.2 pm process
`is considered. This process allows for two polysilicon
`levels (one doped N-type and another doped P-type)
`and two levels of metal.
`Microelectronic and micromechanical components
`are created on the wafer during the CMOS process by
`creating a set of semiconductor, conductor and dielec-
`tric layers. These layers are obtained by means of tech-
`nological operations which include, for the CMOS tech-
`nology considered, oxidation, deposition, photolithog-
`raphy, etching, ion implantation and annealing. Each
`operation is a potential source of defects. The most
`typical failure mechanisms are listed in Table 3 for each
`technological step (groups from A . l to A.6). As a re-
`sult of a technological step, contaminants (unwanted
`particles) or residuals may remain in the environment
`and be harmful in a succeeding step (group A.7).
`During wet oxidation used for growing Si02 over a
`silicon surface, hydrogen molecules can escape through,
`breaking oxide bonds and creating hydroxides which
`weaken the oxide. A microsystem beam, for example,
`may then be too fragile. Deviations on oven tempera-
`ture or oxidation time may result in inadequate oxide
`thickness, while an unexpected thickness of SiN may af-
`
`(b) damping factor
`
`(c) stiffness constant
`
`GT = 4Q,0wpLpTe3
`(f) thermal radiation
`
`(e) thermal convection
`
`Figure 2: Mechanical and thermal parameters for mod-
`eling CMOS-compatible microstructures.
`
`the joined beam, usually composed of several layers, is
`calculated from its length L,, Young modulus E, and
`its moment of inertia I obtained as a function of beam
`geometry.
`Silicon micromachining allows releasing the mi-
`crostructure from the bulk, becoming then thermally
`isolated. Thermal properties are exploited for systems
`such as infrared sensors and electrothermal converters.
`Heat transfer can occur via the mechanisms of conduc-
`tion, convection and radiation, each characterized by
`means of a conductance value as shown in Figure 2.
`For thermal conduction, conductance GC! depends on
`geometry of the conducting layers and their conductiv-
`ity factors kci. For thermal convection, conductance
`Gcv depends on geometric features and properties of
`the cooling fluid (mostly, air natural convection). Con-
`vection coefficients are taken into account for both top
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`A. During CMOS Drocess
`
`1. During wet oxidation
`a. breaks of Si02 bonds
`b. inadequate Si02
`thickness
`c. inadeauate Si07 size
`2. During deposition
`a1 .voids in dielectric
`a2.voids in metal
`b. hillocks
`c. deposit thickness
`d. microcracks
`e. impurities
`f. annealing temperatue
`3. During photolithography
`a. photoresist residuals
`b. dust particles in masks
`C* Photoresist
`d. notching
`e. acute angles
`f. alignment
`g. photoresist pouring
`
`~~
`
`4.During etching
`a. aluminium residuals
`b. detachment of
`conductors
`C. presence of particles
`d. insufficient etching
`e. etching step
`5,During ion implantation
`6.During annealing
`a. contact quality A1-Si
`b. insulator break
`between conductors
`c. change of polysilicon
`electrical properties
`and
`
`7.
`residuals
`a. O2 and oxide residuals
`b. nitrogen
`c. phosphorus
`d. chlorine
`e. potassium
`
`B. Durine: micromachining
`
`1. protuberances in the cavity
`2. undesired reaction products
`3. insufficient etching
`4. break of passivation or Si02 layers
`5. re-deposition
`
`Table 3: Failure mechanisms for CMOS-compatible
`MEMS.
`
`fect the size of the oxide surface. For example, Figure 3
`shows a break of a fragile bridge-type microstructure.
`Deposition is used for creating dielectric (insulator,
`passivation) and conducting (polysilicon, metal) lay-
`ers. Voids can appear in both types of layers modi-
`fying structural parameters. In dielectric layers, voids
`can give rise to short circuits between insulated layers,
`while in metal layers they can produce opens of the con-
`ductor. Because of the large thermal expansion of alu-
`minium with respect to silicon, hillocks in aluminium
`layers may result in metal-metal shorts. A deviation of
`temperature or deposition time will affect the thickness
`of the deposited layer. Non-uniform depositions may
`result in asymmetric structures. Microcraks can also
`occur since the technology used is non-planar, giving
`higher resistance values in metal layers. Impurities in
`the crystalline structure of a metal alter the movement
`
`Figure 3: Photograph of a break in a fragile 180 pm
`wide bridge-type microstructure (optical microscope).
`
`of electrons and thus increase resistivity.
`For photolithography, the technology considered
`uses contact printing followed by illumination with ul-
`traviolet light. Photoresist residuals, dust in masks
`or photoresist shadowing can cause circuit opens and
`shorts. Notching due to parasitic light reflections or
`photoresist pouring after development may result in
`narrower photoresist layouts and thutj larger and less
`resistive conductors. Acute projection angles which
`are tolerated for microsystem fabricattion may result
`in open circuits. Incorrect mask alignment may result
`in inadequate contacts or opens, or important asym-
`metries during micromachining.
`Wet and plasma-assisted dry etching are used in
`the technology considered. Aluminium residuals, the
`presence of particles during etching, and over-etching,
`which results in detachment of conducting layers, may
`result in different types of shorts. Under-etching
`caused by insufficient etching time may leave shorts in
`conducting layers or a closed contact causing an open
`circuit. Etching steps affect also the quality of the con-
`tacts.
`Variations on density of dopant atoms during ion
`implantation in polysilicon affect material properties
`such as resistivity, temperature and Seebeck coeffi-
`cients, piezoresistivity and thermal conductivity. Since
`the impact of the ion beam causes some damage to the
`single-crystal silicon structure, a subsequent annealing
`step is applied to restore the regularity of the lattice
`and to obtain good contact quality. During annealing,
`high heating temperatures and different material ex-
`pansion coefficients may result in insulator breaks (thus
`short circuits) or even microstructure breaks. The an-
`nealing temperature may affect the overall polysilicon
`electrical properties.
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`Contaminant particles remaining in the environ-
`ment may be harmful in succeeding CMOS technolog-
`ical operations or during micromachining. Most often,
`contaminants exist in the atmospheric environment.
`Oxygen contaminants forming silica can disrupt con-
`tact quality and etching. Nitrogen favours mechanical
`breaks, phosphorus can result in open circuits by react-
`ing within a void, and chlorine in a photoresist favours
`metal corrosion resulting in circuit opens.
`In particular, one of the most common problems
`encountered for the fabrication of CMOS-compatible
`MEMS is the presence of oxide residuals from the
`CMOS process in areas of naked silicon exposed for
`micromachining. These areas are created by stacking
`a contact, a via and an open in the passivation. Oxide
`residuals are formed from thermal silica and from dif-
`ferent layers of oxides which are not properly cleaned
`during fabrication. As an example, Figure 4 shows a
`microstructure after the CMOS process flow and be-
`fore micromachining. Several superposed oxide layers
`(darker regions) can be distinguished on top of the ex-
`posed silicon (lighter region). In this case, one oxide
`layer (CVD2) was not properly cleaned. This residual
`oxide can prevent the formation of an adequate cavity
`during micromachining of the exposed silicon.
`
`Oxide Layers Residual CVD2 Expos$ Silicon
`
`must be used for realizing the microstructures sup-
`porting the gauges and can be combined with metal
`and polysilicon layers. Anisotropical etching is con-
`sidered which results in a cavity with the shape of an
`inverted pyramid. For surface micromachining, a sac-
`rificial layer of a material such as silicon oxide, polysil-
`icon, porous silicon or aluminium is deposited. The
`postprocessing operation removes this sacrifitial layer
`to suspend the microstructure.
`CMP has mostly used silicon-compatible front-side
`bulk micromachining. Low cost maskless etching can
`be achieved using typical etchants such as EDP, KOH
`or TMAH. EDP has the advantage that it does not
`significantly attack aluminium, and it does not attack
`passivation layers. KOH allows very clean surfaces and
`etching plans, but has the disadvantage that it attacks
`aluminium. TMAH has an excellent etching rate, and
`it does not attack aluminium pads if the solution con-
`tains adequate proportions of dissolved silicon or silicic
`acid.
`The bottom of the cavities obtained using typical
`TMAH solutions may not be flat as shown in Figure 5
`due to pyramidal protuberances or hillocks which can
`appear. These reduce the etching rate of the bottom of
`the cavity which can be a problem for thermal sensors,
`due to thermal leakage, or alter damping factors for
`accelerometers. Hillocks may be avoided adding to the
`solution adequate quantities of peroxide.
`
`Figure 4: SEM picture of a microstructure showing the
`presence of oxide residual after the CMOS process.
`
`Protukirance
`
`4.2 During micromachining
`
`After a CMOS process on a conventional production
`line (such as AMS or Atmel-ES2), anisotropic etching
`outside the foundry is used to suspend the structures.
`Several micromachining processes are possible which
`include front-side and back-side silicon bulk microma-
`chining, and surface micromachining. For silicon bulk
`micromachining using these technologies, silicon oxide
`
`Figure 5: SEM picture showing pyramidal protuber-
`ances at the bottom of a microcavity etched with
`TMAH 2.5%. The 100 pm wide bridge is not released
`in its central part.
`
`In general, a microstructure may not be fully sus-
`pended, or the cavity produced may be inadequate,
`as a consequence of insufficient etching time, slow
`etching rate because of an inadequate solution, or re-
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`depositions which may occur after etching. For exam-
`ple, the microbridge in Figure 5 is not fully suspended
`because of insufficient etching time. In addition, com-
`plex substances can be formed as a result of chemi-
`cal reactions which take place during silicon etching.
`These substances may affect the quality of the solu-
`tion, reducing etching rate (or appear stuck on the mi-
`crostructure at the end of the process).
`An example of these failure modes is shown in the
`MEMS device of Figure 6 . This thermal pixel con-
`sists of a suspended polysilicon resistor. The membrane
`that suspends the resistor has large thermal resistance,
`which originates a temperature increase in the center
`of the structure and a visible heat radiation. It can
`be observed that part of the membrane in the central
`part was not suspended (lighter region), and most of
`the heat generated by the polysilicon resistor in that
`part is evacuated through thermal conduction to the
`bulk. On the other hand, the first part of the polysil-
`icon resistor is suspended, and the heat radiation can
`be observed.
`
`Figure 6: Photograph of a thermal pixel not fully sus-
`pended (optical microscope).
`
`For bulk micromachining , the dimensions of the ex-
`posed silicon areas must be large enough to avoid prob-
`lems with oxide residuals which resist to the etchant
`attack. These residuals can be most important in re-
`gions with acute angles or cross-like structures. Fig-
`ure 7 shows an example of a microstructure which is
`not adequately formed because of these defects. Silicon
`is not adequately exposed in the areas covered by the
`oxides.
`In general, if oxide residuals are not too thick, they
`may be eliminated by immersion of the microstructure
`in an acid solution such as HF. However, cleaning with
`HF can cause breaks in oxide and passivation layers.
`Breaks or microcraks in passivation layers can allow
`
`Oxide Residual
`
`Figure 7: SEM picture showing presensce of oxide resid-
`ual in exposed areas of small dimensions.
`
`the etchant to penetrate and cause opens in polysili-
`con conductors and attack aluminium lines (only KOH
`etching). An example of this is shown in Figure 8 where
`an inadequate passivation layer allowed KOH to pene-
`trate and attack aluminium lines. This can cause open
`circuit catastrophic faults or parametric faults due to
`important deviations in circuit resistivity. An exam-
`ple of failure mechanism for this is the following. Most
`metal layers used for IC fabrication are composed of
`aluminium and other types of metals which are not at-
`tacked by KOH. In some cases, KOH can etch away an
`aluminium layer and leave the metal barriers of these
`layer! which can contain, for example, a thin layer of
`lOOOA of TiW. As a result, conduction can only occur
`in this thin metal barrier layer which results in a large
`increase in resistivity.
`
`KOH attack to aluminium lines
`
`Figure 8: SEM picture showing the attack of EDP to
`aluminium lines due to inadequate pa,ssivation layer.
`
`A common defect is also the attack of aluminium
`
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`I. Gauge faults
`
`11. Microstructure faults
`
`Break
`............ Fr
`break outside gauge
`............
`Fr/G
`break around gauge
`. . Fr/FrG
`break including gauge fracture
`.......................
`Stiction
`Sti
`Non-released microstructure Nr
`Asymmetrical microstructure
`............. Ath
`thermal asymmetry
`......... Amech
`mechanical asymmetry
`
`Short faults
`........
`c c P-P
`in one polysilicon level
`Cc pl-p2
`between both polysilicon levels
`between poly and metal ...... Cc p-m
`in one metal level ............. Cc m-m
`between both metal levels .... Cc ml-m2
`Open faults
`............
`CO P
`in polysilicon level
`in metal level ................. CO m
`in poly-metal contact ......... CO c
`B. Parametric faults
`Structural
`.......................... W
`width
`..........................
`L
`length
`.......................
`t
`thickness
`Mechanical
`...................
`mass density
`Pm
`.... d
`distance microstructure-bulk
`................ E
`Young modulus
`Thermal
`........... kc
`thermal conductivity
`.......... d
`encapsulation distance
`................
`beam emittance
`eb
`
`Structural
`width ........................ W
`length ........................
`L
`thickness .....................
`t
`Material
`......... PPOlY
`polysilicon resistivity
`..............
`Pmet
`metal resistivity
`............
`Pcon
`contact resistivity
`.........
`TCRpoly
`TCR coefficient poly
`........
`TCRmet
`TCR coefficient metal
`piezoresistive coefficient ...... n
`.......
`a
`Seebeck coefficient poly
`Poly
`.....
`amet
`Seebeck coefficient metal
`..................
`permittivity
`Er
`
`Table 4: Fault classes for CMOS-compatible microelectromechanical systems.
`
`pads. To avoid this, CMP has been proposing the use
`of a thin layer of oxide to cover them which prevents the
`attack [13]. During bonding, this thin layer is broken
`using ultrasonic bonding.
`
`5 Fault Classes
`
`Failure mechanisms can be classified according to
`the physical properties or parameters of the MEMS
`which are affected, and this allows a classification of
`faults for CMOS-compatible MEMS as shown in Ta-
`ble 4. This classification has taken into account known
`fault models for analog electrical parts (such as open
`and shorts, considering fabrication processes which can
`have two levels of metal and two levels of polysilicon),
`known failure modes including those observed in fabri-
`cated MEMS and described in Section 4, and the im-
`plementation parameters described in Section 3 for the
`modeling of these devices.
`
`In Table 4, two main groups of faults are consid-
`ered, those affecting the microsystem gauge and those
`affecting the microstructure that supports the gauge.
`Each group of faults is in turn classified in two classes:
`catastrophic faults, which prevent any system utiliza-
`tion, and parametric faults, for which changes on geo-
`metrical or material parameters alter microsystem per-
`formance.
`A gauge provides the actual electrical interface, and
`therefore it is subject to analog faults which typically
`include catastrophic short faults (two layers of metal
`and two layers of polysilicon can be used as conduc-
`tors), catastrophic open faults (in polysilicon or metal
`conductor, and in polysilicon-metal contacts) and para-
`metric deviations in the geometry of the elements (W,
`.
`L and t) or their material properties (e.g. p
`Poly)
`For catastrophic faults in the microstructure, several
`sub-classes of mechanical and thermal faults are consid-
`ered. A beam supporting a gauge can break in several
`
`Paper 22.1
`548
`
`Raytheon2025-0008
`
`

`
`Failure mechanism (see Table 4)
`A. CMOS pr
`cess
`3
`4
`2
`~ b c d e 11 a2 b c d e ~ b c d e f g
`
`x x x x
`X
`X
`
`x x
`
`x x x x
`
`X
`
`B. Micro-
`7 m
`machining
`1 2 3 4 5
`
`Fault
`(see
`Table 3)
`- -
`A
`1
`1
`-
`
`G
`a
`U
`g
`e
`
`L
`t
`W
`PPOlY
`Pmet
`pcon
`TCRpoly
`TCRmet
`TPolY
`ffPolY
`ffmet
`-
`E,
`P
`Pm.
`E
`S
`t
`kci
`r
`Eb
`d
`U. - -
`c c P-P
`c c pl-p2
`G
`Cc p-m
`a
`Cc m-m
`U
`Cc ml-m2
`g
`e
`C O P
`CO m
`C O c
`Fr
`R I G
`l?r/FrG
`Sti
`Nr
`Ath
`mech
`
`-
`P
`S
`t
`r
`U
`C
`t. -
`
`- -
`
`P
`a
`r
`a
`m
`e
`t
`r
`i
`C
`
`- -
`
`C
`a
`t
`a
`S
`t
`r
`0
`P
`h
`i
`C
`-
`
`X
`
`X
`X
`X
`x
`x
`
`X
`X
`
`X
`
`X
`X
`X
`X
`
`c x x
`c x x
`c x x
`c x x
`c x x
`c x x x x
`c x x x x
`c x x x x
`
`x x x
`
`K X X X
`
`X
`
`x
`x
`
`
`
`
`X
`
`X
`
`X
`X
`X
`
`l c x x
`
`X
`x x
`X
`
`
`X
`X
`X
`
`K
`R X X
`
`x
`x
`
`- -
`
`X
`X
`X
`X
`X
`
`Y
`
`X
`X
`X
`
`X
`X
`X
`
`K
`K
`-
`K
`
`Table 5: Failure mechanisms and fault classes.
`
`ways, including or not a break of the gauge. Stiction
`of a suspended structure to the bulk can mostly oc-
`cur for surface micromachining. For bulk micromachin-
`ing the microstructure may not be adequately released
`due to incomple