Sony Corp. v. Raytheon Co.
`IPR2016-00209
`
`Raytheon2018-0001
`
`

`
`dates follow. Operatorskilsl rc:,11paeidn;aandq-.::n°°k'“‘” P"°°¢'
`
`.
`
`on
`
`es: open.
`
`“W91! '4N'C). the seed ' di
`
`-
`
`.9305
`
`Raytheon2018-0002
`
`Raytheon2018-0002
`
`

`
`OONORA ON QYSTAL GROWTH AND PlIO0E$lNO TECIIIOLOGY
`
`7
`
`tions. Once the crystal teaches the diameter desired. the autotnatic-diatneter-
`control (ADC) system is turned on and closed-loop controls regulate the
`diatnaer.
`
`'l'he process continues through body growth. As the crystal is pulled. the
`melt level in the crucible drops relative to other hot-zone components. Be-
`cause this changing melt level creates undesirable changes in thermal profiles
`at the growth interface. an electromechanical crucible-lifl system is normally
`provided to elevate the crucible continuously during the growth procus. The
`rate of lifl. in turn. affects other growth parameters. so the furnace operator
`must monitor visual indiations of structure on the growing crystal to assure
`that crystal pull speed and crucible lift rate are appropriate.
`Body growth proceeds at pull speeds ranging from 50 to |00 tum/It. until
`only a small volume of melt remains in the cntcible: at this point the round-
`off procedure begits. Structure must be maintained tnetieulously during
`round-off. because crystal defects such as “slip" can propagate up through
`the still-plastic crystal body. After round-off‘. power to the furnace is turned
`offand the crystal is allowed to cool. The crystal may later be heat treated to
`stabilize electrially active oxygen.
`
`Crystal Evaluation
`
`The completed crystal is imrnetsed in an etchant designed to highlight de-
`fects such as slip. When the shoulder and round-off portions lave been
`cropped with a diamond saw. resistivity and type measurements are made
`and recorded for the crystal ends. The cropped ingot is ground to the desired
`dillnctcr. and may be rechecked for atrial profile by taking resistivity read-
`ings along the length of its cylindrical surface.
`At a location determined by atomic orientation. a flat is ground along the
`length of the ingot: th's will serve as a reference plane for later operations.
`The crystal may now be sliced into wafers or cropped into segments for spe-
`cific end users.
`
`CZ Materiel Cltcmerertk-rt‘a
`
`Muchofthccurtent tesearchonsiliconisfocusedontheexccedingy
`complex relationships among certain impurities and defects in silicon crys-
`tals. benuse point defects in wafersubstratcs exert an increasingly strong in-
`lluence on final die yields. This surge of interest in crystal defect formation
`arises from the shrinking die and circuit-element size used in ver'y-large-ocale-
`integration (VLSI) technology. ‘nae complexities lie partially in the fact that
`impurity concentration alone does not constitute defect formation: other de-
`termining factors include thermal gradients at the time of solidification. lo-
`calized melt convection. instantaneous growth rates. melt—temelt phe-
`nomena. and thermal conditions after solidification.
`
`Raytheon2018-0003
`
`
`
`Raytheon2018-0003
`
`

`
`
`, l§o
`
`
`8
`
`SILICON PROCESING
`
`Current technial literature on the subject of crystal defects is plentiful.
`but its utilintion in production practices presents many challenges. To de-
`termine accurately the influence of process changes in crystal growth upon
`device yields in a particular fabrication line may involve an elapsed time of
`three to six months. and requires detailed communication between water
`supplier and user.
`
`Oxygen and Carbon
`
`Control of oxygen and carbon in the growing crystal is an active area of
`research. Oxygen is prwent in C2 silicon as a result ofdissolution of the sil-
`ica crucible wall. and generally is higher in concentration at the top end ofan
`ingot. Reported concentrations-range from <10 to >40 ppm. Oxygen influ-
`ences wafer strength. resistance to thermal warping. minority-carrier life-
`time. and intrinsic impurity gettering. There is evidence that the level of oxy-
`gen content influences die yields. and that appropriate levels for maximum
`yield depend upon the particular device production technology.
`Carbon is present in C2 silicon as a result ofcontributions from the origi-
`nal polycrystalline material and from graphite components of the hot zone.
`Reported concentrations range front 0.1 to 7 ppm. with levels usually rising
`throughout the length of the ingot. Carbon is strongly implicated in the gen-
`eration of point defects: its role appears to be interrelated to the presence cl‘
`oxygen.
`
`Carbon and Oxygen Aleastrrentenl/Control
`
`Control of carbon and oxygen must be achieved primarily by the materials
`producer. and substantial efiort is being expended in related applied re-
`searehoxygeneanbepartiallycontrolledbytneansofgrowth techniques
`that minimize the rate of crucible-wall dissolution and reduce the incorpora-
`tion of dissolved oxygen into the growing crystal. Control of carbon is re-
`lated to gas now patterns. hot zone materials. furnace leak integrity. and
`starting material.
`The primary technique for measuring oxygen and carbon concentrations
`employs a transmission/absorption-type infrared spectrophotometer.
`Lengthyandcareful samplcprocessingisnecessary toobtain usableresttlts.
`although the recent introduction of Fourier transform infused equipment
`facilitates rapid rneasuretnent of oxygen and urban on polished slices.
`A subjective indication ofthe influence ofearbon and oxygen on C2 mate-
`rial is provided by a variety of
`tests. This technique employs high-
`temperature oxidation of a polished sample. followed by decoration etching
`and visual examination. Swirl is evidenced as a cloudy appearance. often
`havingastvirled l'orm.that iseatuedbythehigh-densityformationot‘nti-
`croscopic etch pits at sites where concentrated mierodefects occur. Because
`
`Raytheon2018-0004
`
`Raytheon2018-0004
`
`

`
`BONORA ON CRYSTAL GROWTH ADI) PflOCE%lN6 TECFNOLOGY
`
`9
`
`swirl has been correlated to areas of high device-yield loss. CZ growth tech-
`nologies that provide low or zero swirl may improve die yields.
`
`New Developments in Crystal Growing
`
`The field of (‘Z growth is experiencing the emergence of several new tech-
`nologies in such diverse areas as control of oxygen by magnetic lields. liquid-
`silicon recharging. high resistivity. and furnace automation. An overview of
`these areas will provide a general idea of work currently tmder way.
`
`Magnetic (‘Z
`
`In ordinary CZ growth. thermal gradients set up convection currents that.
`when combined with crucible and crystal rotation. give rise to a general flow
`pattern such as that in Fig. 2. This convection-induced flow transports oxy-
`gen through the melt into the liquid-crystal interface via dissolution of the
`quartz crucible.
`The convection currents also give rise to regularly occurring temperature
`transients at the melt-crystal interface. creating what is termed the melt-
`remclt phenomenon. This repetition of incremental solidification and melt-
`ing is implicated in the development of mierodefects.
`Standard CZ pullers afford limited capability for oxygen control through
`such processes as changing rotation and pull speeds and hot-zone geometry.
`Recently it has been found that oxygen content and crystal striations may be
`reduced significantly by applying a transverse magnetic field to the silicon
`melt area in order to damp the liquid convection currents.‘ Several silicon
`
`
`
`FIG. 2—.\'rAn-mlie reprerenuuon ofnrrll/low pamnu induced by thermal mvrrrt-rim and cru-
`athlr nualion.
`
`'Suruki. 'l‘.. lsawa. N.. Otubo. Y..and Hashi. K. in Seauroadurmr Silicon 1981. II. R. Hall’
`at al. Eds . Proceedings of Fourth International Symposium on Silicon Materials Science and
`Technology. The Electroelueutieal Society. Pennington. N. J.. l98l.
`
`Raythe0n2018-0005
`-F
`
`
`Raytheon2018-0005
`
`

`
`10
`
`SILICON Pnocsssme
`
`
`
`FIG. 3—Di4i;raiir ofiluumerk flair mini and
`
`rbenld eolmeerloiu.
`
`producers are investigating the effects of this technique. known as magnetic
`CZ (MCZ).
`
`The MC2 effect offers a direct means of regulating oxygen transport and
`temperature transients. In principle. any motion of the highly conductive
`molten silicon is impeded when it crosses the magnetic flux field (Fig. 3).
`This provides a thick. stable boundary layer between the crucible wall and
`the bulk silicon melt. so that oxygen transport is limited to diffusion through
`a stable liquid medium. At the same time. the temperature transients at the
`growth interface are suppressed: the result is a relatively steady instantane-
`ous growth rate.
`
`Courlnuous Liquid-filieon Feed
`
`The concept of continuous liquid-silicon feed (CLF) has been under de-
`velopment for several years. CLF employs a heated qtnrt7 tube to transfer
`liquid silicon from a meltdown chamber to a growth chamber. allowing for
`control of dopant concentration in the feed material. and for semicontinuous
`replenishment of polycrystalline material and crystal solidification. Advan-
`tages include axially uniform crystal properties. improved productivity. and
`decreased crucible and power costs. Individual crystal sizes up to 65 kg have
`been achieved. and the process has shown capability for growing zJero-defect-
`quality material. Operation of the C Li’ system is tedinically complex. how-
`ever. and additional furnace automation is required for production feasibil-
`ity. A schematic representation of a CLF system is shown in Fig. 4.
`
`High-Resistivity cz
`
`Historically. most requirements for resistivities greater than 25 0-cm
`have been filled with material grown by the float-zone
`which uses no
`crucible. Increasing demands for resistivities as high as 70 0-em have re-
`
`Raytheon2018-0006
`
`
`
`..9.Jouuff
`
`Raytheon2018-0006
`
`

`
`BONOBA ON CRYSTAL GROWTH AND PROCESSING TECHNOLOGY
`
`11
`
`
`
`FIG. 4—(‘rm.s srrunn o/future inwrpomtntg ronrtmravs Ir‘¢rn'dfrd of.rt'!aimn olvring groi--tit.
`
`ocntly been satisfied with C2 material. Production experience to date indi-
`cates that extra care in doping and charge preparation can lteep yields close
`to levels expected for standard product. provided that high-purity polycrys-
`talline rnatenal is used. General availability of the product may afford addi-
`tional flexibility in the design of high-speed memory devices.
`
`Furnace Automation
`
`To free the crystal growth process from operator judgment. it is desirable
`to have a computer monitor the process status and effect necessary changes.
`Improved furnace mechanical design. coupled with the uniform consistency
`of digital control and new process transducers. will lead to substantial auto-
`mation. and preprogrammed process changes will give better run-to-run
`uniformity.
`Present activities emphasize effective use of linked automation and devel-
`opment of “recipe“ loading systems that will facilitate end-user process de-
`velopment without the need for software and computer system skills. Figure
`5 shows a state-of-the-art computer-controlled furnace.
`
`Crystal Processing
`
`Slicing
`
`Conversion of ground ingots into slices (wafers) is accomplished primarily
`by inside-diameter (ID) diamond sawing. Machine technology has changed
`to accommodate larger ingots as well as new accuracy requirements. Typical
`
`Raytheon2018-0007
`
`Raytheon2018-0007
`
`

`
`-'12
`
`SIUOON PROCESSING
`
`new machines incorporate hydraulitztlly or mechanically tensioned blade
`heads in the 685.6— to 762-mm-diameter range. using blades with 12- and IS-
`mil lterf widths and 203.2- to 254-mm bores. Machine types currently avail-
`able include horizontal and vertical spindles with rollingclement and air-
`bearing construction. All types are successfully in use by leading silicon
`producers. and automatic control-feedback features are becoming available.
`All saws allow adjustment of the ingot axis to permit cutting on the desired
`crystal orientation. Typical productivity figures for I00-mm wafers are 150
`to 23) wafers per 8-h shift. and blade life is in the range of 3500 to 7000 cuts.
`Control of planarity during the slicing process has become critical in the
`last three years. since repeated thermal processing of wafers has been found
`to exaggerate the distortions of wafer bow. Flatness of the polished wafer
`product also is influenced by bow. because the subsequent grinding/lapping
`
`Raytheon2018-0008
`
`Raytheon2018-0008
`
`

`
`eouonn on CRYSTAL Gnown-t mo mocessme TECHNOLOGY
`
`13
`
`
`
`I-16. b—('kur-up View ofll) nrw. skewing atnonnuit Male drnnrgfunve.
`
`processes remove material from bowed wafers in an unpredictable manner.
`Most saws incorporate a means to facilitate bow control by measuring the
`deflection of the blade during each wafer cut.
`Generally. a blade that cuts without lateral deflection will deliver slices
`with minimal “cut-in“ how. but how induced by nonsymmetrical surface
`stresses on opposing laces may still exist. The saw operator normally moni-
`tors both blade deflection and general wafer bow trends. and will correct the
`cutting action by a combination of blade-dressing techniques and blade
`tensioning.
`Figure 6 shows a prototype saw that allows the cut ingot face to be auto-
`matically raised during slicing. This semiautomatic device also allows the
`measurement for cut-in bow. and for initiation of a programmed blade-
`dressing sequence indicated by the direction and magnitude of the bow.
`Another feature that is becoming prevalent is “single-slice recovery".
`wherein a retrieval mechanism recovers each wafer and loads it into a con-
`
`ventional cassette. This feature eliminates drag of the blade on the return
`stroke. with improved safety and ease of operation.
`Wafer slicing and cleaning remain critical first fabrication steps. and a
`wafer with excessive bow. lack of planarity. or work damage crates prob-
`Iems in further processing,
`
`l i I
`
`Raytheon2018-0009
`
`bwin:
`
`Typically. the as-cut slice from an ID saw is not flat enough to meet pol-
`ished slice requirements. and a free-abrasive double-sided machining process
`(lapping) is used to planar-ire both slice surfaces and provide uniform finish.
`
`Raytheon2018-0009
`
`

`
`
`
`.....—......n.r_—.'.:___'51
`
`Some difficttlties associated with edge contouring have included:
`
`1. Loss of diatnetral accuracy.
`2. Rounding of the fill cusps.
`3. Angular shining of the wafer an.
`4. Random sulloping of the wafer edge.
`5. lnsullicient control or top and bottom contours.
`
`grinding. and higlvspeed grinding with a preformed wheel. A common meth-
`od ttsesagrooved wheel rotating at high speed. which isheldauinst thepe-
`riphery of a slowly rotating wafer by a constant-force mechanism. An alter-
`native method (Fig. 7) uses a multistep sequence to wind the outside
`diameter. top edge. and bottom edge on a am-controlled profile grinder.
`Advantages include (I) aecunte final diameter. independent or wafer-statt-
`in; dimensions; (2) accurate primary-flat and secondary-flat generation: and
`(3) independent selection of top and bottom edge contours.
`
`Raytheon2018-0010
`
`Raytheon2018-0010
`
`

`
`15
`
`. . removal rates an 30
`. and more moderate cy-
`- Diflieulties with acid etch-
`xides of nitrogen evolved. operator hazards.
`uniform etch removal which leads to a non-
`
`and a Iendency towards non
`planar wafer surface.
`For these and other reasons. caustic etching in high-lempenlure (70 lo
`
`Raytheon2018-0011
`
`Raytheon2018-0011
`
`

`
`.16
`
`SILIOON FDOCESING
`
`130°C) potassium or sodium hydroxide has become commonplace in the last
`two years. Although time cycles are considerably longer than with acid.
`material removal tends to be more uniform. and the etched wafer flatter.
`Process characteristics are more uniform throughout bath life. and both et-
`chant costs and air pollution are reduced.
`Rinsing is particularly important after caustic etching. and several stages
`of deionized (DI) water rinse may be necessary. 1'he wafer surface tends to
`be grainier or rougher after caustic etch. which leads to occasional problems
`with backside contamination. Residual sodium-potassium contamination
`has not presented problems.
`
`Gerredug
`
`Controlled residual work damage on the backside or at strain sites in the
`silicon lattice acts to “getter" various impurities during thermal processing.
`prevailing their migration upward into active device regions. Common meth-
`ods of introducing controlled backside residual damage include:
`
`1. Abmsiw blesn'ng—-Controlled-diameter particles of alumina or other
`hard material are directed at high velocity against the wafer backside in a
`process similar to sandblasting.
`2. laser beam—A small-diameter focused laser pulse of appropriate
`wavelength and energy strikes the surface and creates localized melting or
`material removal. A matrix of damage sites in the desired pattern is achieved
`by repeated pulsing.
`3. Direct surface abrtm'on—‘l1te wafer is rotated on a vacuum chuclt and
`an abrasive-coated cloth or paper is moved radially in point or line contact
`with the wafer. leaving a series of concentric damage sites.
`4. Liquid ltontrtg—A high-velocity stream of liquid containing abrasive
`particles is traversed across the wafer backside.
`
`In all systems of this type. major considerations are uniformity of damage
`depth and freedom from residual contamination. In addition. certain dam-
`age processes leave deep fissures which tend to pick up contaminants that
`cannot be easily detected or cleaned. and which dilfuse through the wafer at
`subsequent steps. These processes all have different characteristics in terms
`of damage intensity and ease with which damage sites anneal out and lose
`effectiveness.
`
`A variety of thermal and chemical means are also available to improve
`gettering. One technique involves processing a wafer in a manner so as to
`achieve a sharp gradient of oxygen concentration at the polished surface.
`thus creating a “denuded zone“ which contrasts with relatively high oxygen
`content in the bulk of the wafer. Other techniques to achieve oxygen gra-
`dients are being explored experimentally. The concept of the silicon wafer
`
`Raytheon2018-0012
`
`
`
`Raytheon2018-0012
`
`

`
`BONORA ON CRYSTAL GROWTH AND PROCESSING TECHNOLOGY
`
`17
`
`substrate as a homogeneous entity. polished on one side. is rapidly giving
`way to the recognition that many desirable properties can be deliberately
`and methodically created.
`Introduction of bacltsurfaoe gcttering is normally done following the etch-
`ing operation. and rigorous cleaning is necessary prior to polishing.
`
`Intermediate Wafer Inspection
`
`After the slice/lap/etch operations. integrated automatic equipment (Fig.
`8) is used to inspect and sort the wafers for resistivity. thiclcna. how. flat-
`ness. and surface appearance. Visual inspection of as-etched wafer surfaces is
`performed to check for etch stains. residual saw marks. flakes and chips.
`edge contour. and uniformity of appearance- Although this operation relies
`heavily on human visual skill and judgment. automatic wafer-handling
`equipment can assure consistency of wafer inspection time and viewing con-
`ditions. Automatic handling also eliminates wafer breakage and chipping
`which occur with coin stacking and with tweezer or vacuum pencil pickup.
`
`Laser Marking
`
`The concept of using a focused laser beam to create alphanumeric or bar
`code identifiation marks on wafers has been in the embryonic stage since
`I975. Commercial equipment with good production capability is awtilable
`from several manufacturers. and some silicon producers are shipping pilot
`quantities of marked wafers. Despite adoption of the Semiconductor
`
`
`
`FIG. 8—l’¢rnw view of rr.st’rn‘vi’I_v/chicken: mm-r. rnzwpomung 24 rrreflrr notions.
`
`_—-—:—jj ‘
`
`Raytheon2018-0013
`
`
`
`Raytheon2018-0013
`
`

`
`Equipment and Materials Institute (SEMI) standard and universal recogni-
`tion that an identification code is desirable. the transition to widespmd use
`is slow because of the many challenges involved in effectively utilizing code
`information.
`
`The marking performed by the silicon manufacturer is normally done as
`pan of. or after. slice sorting. because the correct resistivity will be known at
`that point. Laser marking may raise a entered edge and leave slag on the
`slice surface. and the producer may prefer to mark prior to etching. particu-
`larlyifthemarltistobeon the waterbackside. lntllis¢v¢IIl.Ihesortingsteps
`are repeated prior to polishing.
`During the next several years. it can be expected that equipment manufac-
`turers and device line planners will integrate the use of marked information
`into an overall concept to aid process control and material flow. This ambi-
`tious undertaking will involve the availability of highly reliable code readers
`and wafer-bulfering systems. Truly hands-oil’ material flow in both silicon
`and device plants will require production control systems with computer-
`controllcd feedback to regulate processes and to allow for equipment down-
`time and nonuniform production rates in some operations. Multipurpose
`cassette-type wafer handlers (Fig. 9) probably will be utilized for transient
`inventory (bttffering) as well as for machine loading.
`
`Polirlrlng
`
`For almost two decades. one-sided water polishing has been accomplished
`by caustic colloidal-silica slurry and a rotating pad for stock removal (10 to
`
`
`
`-‘E
`
`l I
`
`i
`
`s.
`
`Raytheon2018-0014
`
` :
`
`Raytheon2018-0014
`
`

`
`aoucmt on CRYSTAL cnawm mo mocessmc recmotoev
`
`19
`
`N um) followed by finishirtg—a two-step chemical-mechaniral syseem de-
`sip:edIoprodnoeahidIlyreflectiveplanarsnrl'aoe.I'reefrom subsurface
`work damage. haze. and microscrarches. Traditional wax-mounting or rain-
`mounting techniques are prone to leave dimples. wave, or surface contami-
`nation, and are being replaced by templates. surface tension. friction, and
`solidlilm bonding. ‘fhesetvaxlesrnountingprocesseshave irnprovedyielfi
`andreducod prooessingeostabutindustry-wideflatnesspoalstornonlinear
`thickness variation remain a clnllenge.
`Flatness requirements are the major driving force and the figure of merit
`for developing polishing technology. Improvements in flatns continue. and
`wafers currently can be produced to is than 3-gun TIR (peak-to-pak total
`indicated reading).'lhecomp|etespectrnmofrequirementsl'orpolished
`wafer quality dictates a highlyengineered system lodeliversatisfactory re»
`sults. Important polished-wafer parameters such as flatness, taper.and qual-
`ity of surface finish are primarily affected by:
`
`l. Composition. flow rate. radial distribution. and temperature of the
`slurry.
`2. Surface speed. temperature distribution. relative diameters. filidity.
`and geometrical contours of the main platen and carriers.
`3. Materials and procedures for wafer mounting.
`4. Comprmsibility and slurry retention of polish pads.
`5. Unit content pressure. cycle times. rinse sequence. and ambient conditions.
`
`The majority of equipment sold today (whether wax or waxlm) uses mul-
`tiple mounting of wafers on acarrier. with variations between manufacturers
`based on the number. type.and size ofcarriers. A commonly used polishing
`machine (Fig. 10) uses four motor-driven carriers. each of which Inndlcs
`seven I00-mm wafers. The main platen for the polishing pad is driven by a
`M-hp motor. and a typical stock removal cycle is ID to 20 min. A similar ma-
`chine. with dilferent pad and run conditions. would be used for finish polish-
`ing in a l- to 5-rnin cycle.
`Automation of nmltiwafer polishing currently focuses on handling and
`loading of wafers onto the carrier. and on demounting. 11:: machine shown
`in Fig. I0 uses a medium-pressure pulsed jet of DI water to demount waters
`at the rate of 2 s per wafer.
`
`Wder Cleaning
`
`The demounted wafers go through precleaning and final cleaning steps.
`The preclean proees is matched to the characteristics of the polishing system
`(wax or tvaxless). When the wafer is removed from preclean. its surface is
`either entirely hydrophilic or hydrophobic. depending on the presence or ab-
`sence of an oxide film on the polished silicon surface. Since the prccleaning is
`
`Raytheon2018-0015
`
`
`
`Raytheon2018-0015
`
`

`
`generally the last‘ cleaning step for the wafer backside. it is important to use
`no chemicals having nonvolatile residues and to control water purity for
`rinsing.
`Final cleaning generally is accomplished on automated wafer scrubbers in
`a clean-room atmosphere. It entails sequential chemical scrubs. rinsing. and
`spin drying.
`
`Finn! Inspection
`
`A rigorous final inspection. in many cases at a lw% level. is performed
`following final cleaning. Parameters to be checked visually include particu-
`lates. haze. stains, waves. and backside cleanliness. In addition. a sample-
`level check is run on measurable parameters. including how. flatness. resis-
`tivity/thiclmess/type. flat length and position. oxygen and carbon content.
`swirl level. and gcttering effect.
`
`Raytheon2018-0016
`
`Raytheon2018-0016
`
`

`
`BONOHA ON CRYSTAL GROW?!-l AND PROCESSING TECHNOLOGY
`
`21
`
`
`
`FIG. ll-Gmertrl-pwruu insprrlfon rlaviowfar inisutl Jdcflion of Ivqfiv-lltrfow qtinh'I_i'.
`
`‘Die visual inspection requires experienced production personnel and is
`generally subjective. To diminish subjectivity. etforts are being made to auto-
`mate portions of the process by the use of an incident-angle laser beam scan
`for detecting particulates. haze. and stains.
`Mechanized handling (Fig. ll) is being introduced in a variety of inspec-
`tion operations to ensure consistency of inspection conditions and to reduce
`contamination and breakage.
`Flatness measurement is of special interest because it has a major influ-
`ence on the practical limits for shrinking line widths and increasing circuit
`complexity. The depth of field of optimum yield/pattem definition in protec-
`tion alignment is small. and therefore the degree of precision in predicting
`the surface plane of the wafer directly affects the entire photolitliographic
`process.
`
`In the area of flatness inspection. several different types of equipment are
`in use. each with substantially different principles of measurement:
`
`l. Grazing-angle laser inter'ferometr)' with fixed wafer and chuck.
`2. Ultrasonic probe with spiral scan and mechanical wafer rotation.
`3. Multipoint capacitance probe with fixed wafer.
`4. Single-axis laser scan with mechanical wafer rotation.
`5. Multipoint optical probes with mechanical wafer traverse.
`
`An additional measurement system has been introduced recently that ex-
`pands flatness mcasuremen: to include a new paraineter—loca! slope. ‘Ibis
`
`Raytheon2018-0017
`
`
`
`Raytheon2018-0017
`
`

`
`22
`
`SILICON PROCESSING
`
`FIG. l2-—Su;(«r are-ustrrrtmat system that employ: tr laser-been seat. ¢'i.rple,t-r tr mundan-
`rxuwl Iopogrqpltird readout. andedcttlaaa percentage ofu no/er rlur near 0 rperitielflamest
`rutttdanf.
`
`system (Fig. I2) uses a two-dimensional laser scan with a solid-state sensor
`to determine the angular deviation of the reflected beam. In effect. slope is
`measured directly. with conventional flatness data obtained by the digital in-
`tegration of slope data over distance traversed. In this manner. complete sur-
`face topology is obtained. Tests indiatte reliable operation with both pol-
`ished and patterned wafers.
`The issue of slope-flatness measurement on wafers after several thermal
`processing steps may be of interest. since thermally induced distortion can
`become severe enough to prevent total wafer pulldown on a vacuum chuck.
`Thus a wafer may be perfectly flat at incoming inspection and fail in subse~
`quent lithography steps owing to laelt of flatness.
`A tendency towards thermal distortion is a material variable influenced by
`intrinsic oxygen. grown-in stresses. and backside treatment. as well as by
`oxidation/diffusion temperatures and push/pull rates.
`The interactive effects between silicon wafer manufacturing proctsses and
`device line performance typify the complex issues facing wafer manufacturers
`and users. It is apparent that technology etforts are expanding in the devel-
`opment of silicon materials. New material parameters likely to be studied for
`possible effects on device yield and performance include:
`
`I. Interstitial oxygen (including thickness gradient effects).
`
`Raytheon2018-0018
`
`
`
`Raytheon2018-0018
`
`

`
`aoNoaA on cnvsm. Gaovm-t mo mocessmo 1'EcotNot.ocv
`
`23
`
`2. Nondoplnt tnoo-metal content.
`,3. Nonvistnl surface-state conditions.
`.4. Residual lattice stress.
`
`5. Qrbon. precipitate formation, and point defect distribution.
`6. State of oxygen in the lattice.
`'
`
`Control or that factors may in tum contribute to the dcvolopmeot of nevi-
`.paeration semiconductor end-products.
`
`Raytheon2018-0019
`
`Raytheon2018-0019