UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_______________
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`SONY CORPORATION
`Petitioner
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`v.
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`RAYTHEON COMPANY,
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`Patent Owner
`_______________
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`Case: IPR2016-00209
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`Patent 5,591,678
`_______________
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`DECLARATION OF EUGENE A. FITZGERALD
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`Raytheon2001-0001
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`Sony Corp. v. Raytheon Co.
`IPR2016-00209
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`TABLE OF CONTENTS
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`I.
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`Introduction ...................................................................................................... 3
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`II. Qualifications and Compensation .................................................................... 3
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`III. Materials Considered ....................................................................................... 4
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`IV. Level of Ordinary Skill in the Art ................................................................... 4
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`V. My Understanding of Patent Law .................................................................... 6
`A.
`Burden of Proof ..................................................................................... 6
`B. Anticipation ........................................................................................... 6
`C. Obviousness ........................................................................................... 7
`D.
`Claim Construction ............................................................................... 8
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`VI. Relevant Time Frame ...................................................................................... 9
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`VII. Technical Background ................................................................................... 10
`A.
`Integrated Circuit Manufacturing ........................................................ 10
`1.
`Moore’s Law ....................................................................................... 10
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`2.
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`3.
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`Advanced Packaging ........................................................................... 13
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`Microelectronic Processes ................................................................... 15
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`VIII. Predictability in the Art ................................................................................. 15
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`IX. The ’678 Patent .............................................................................................. 17
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`X.
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`Prosecution History of the ’678 Patent .......................................................... 18
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`XI. Prior Art Analysis .......................................................................................... 19
`A.
`Liu Does Not Anticipate Claims 1-4, 6, 7, 10 and 11 (Ground 1) ...... 20
`1.
`Liu Does Not Disclose a Substrate with Three Different Layers ....... 20
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`Raytheon2001-0002
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`2.
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`3.
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`4.
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`Liu Does Not Furnish a Three-Part Substrate ..................................... 35
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`Liu’s Layers Do Not Overlie As Required By the Claims ................. 39
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`Liu Does Not Disclose Forming a Microelectronic Circuit Element in
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`the Exposed Side of the Wafer......................................................................... 40
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`5.
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`Liu Does Not Disclose Patterning and Back-side Processing ............ 41
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`B.
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`1.
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`2.
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`C.
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`D.
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`E.
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`F.
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`G.
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`a.
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`The Combination of Liu and Black Would Not Render Claims
`2-4 and 11 Obvious (Ground 2) .......................................................... 47
`There is No Motivation to Combine Liu and Black ............................ 47
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`Black Does Not Disclose Patterning ................................................... 51
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`The Combination of Liu With Riseman Would Not Render
`Claims 5 and 12-16 Obvious (Ground 3) ............................................ 54
`Liu in Combination With Oldham Would Not Render Claim 8
`Obvious (Ground 6) ............................................................................ 58
`Liu in Combination With Wen Would Not Render Claim 10
`Obvious (Ground 5) ............................................................................ 59
`Liu With Wen in Combination With Ying Would Not Render
`Claim 9 Obvious (Ground 6) ............................................................... 59
`Liu With Riseman in Combination With Kusunoki Would Not
`Render Claim 17 Obvious (Ground 6) ................................................ 60
`Liu With Riseman in Combination With Oldman Would Not
`Render Claim 18 Obvious (Ground 7) ................................................ 61
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`XII. Conclusion ..................................................................................................... 61
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`
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`Appendix 1 – Curriculum Vitae
`Appendix 2 – List of Documents Considered
`ii
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`Raytheon2001-0003
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`I, Dr. Eugene A. Fitzgerald, hereby declare, affirm and state the following:
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`I.
`1.
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`Introduction
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`The facts set forth below are known to me personally, and I have firsthand
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`knowledge of them.
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`2.
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`I make this Declaration in support of the Patent Owner’s response to the
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`Petition for inter partes review (“IPR”) of U.S. Patent No. 5,591,678 (“the ’678
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`Patent”).
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`3.
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`I have been retained by Steptoe & Johnson LLP on behalf of the Patent
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`Owner, Raytheon Company (“Raytheon”).
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`4.
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`I have been asked to provide my technical review, analysis, insights, and
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`opinions on the materials I have reviewed in this case related to the ’678 Patent,
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`including the references cited in Petitioner’s grounds of rejection set forth in
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`Petition No. IPR2016-00309 for Inter Partes Review of the ’678 Patent
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`(“Petition”), and the scientific and technical knowledge regarding the same subject
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`matter at the time of the inventions disclosed in the ’678 Patent.
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`II. Qualifications and Compensation
`5.
`I am over the age of eighteen and I am a citizen of the United States.
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`Raytheon2001-0004
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`6.
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`I have summarized in this section my educational background, career
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`history, and other relevant qualifications. My curriculum vitae, including my
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`qualifications, a list of the publications that I have authored during my technical
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`career, and a list of the cases in which, during the previous four years, I have
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`testified as an expert at trial or by deposition, is attached to this declaration as
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`Appendix 1.
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`7.
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`I received a B.S. in Materials Science and Engineering from the
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`Massachusetts Institute of Technology in 1985, a M.S. in Materials Science and
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`Engineering from Cornell University in 1987 and a Ph.D. in Materials Science and
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`Engineering from Cornell University in 1989.
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`8.
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`From 1988 to 1994, I worked as a research scientist at AT&T Bell
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`Laboratories in Murray Hill, N.J., in the Materials Science and Engineering
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`Department. While at AT&T Bell Laboratories, I conducted fundamental research
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`in semiconductor materials and devices.
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`9.
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`From 1994 to 2000, I was an Associate Professor at MIT. From 2000 to the
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`present, I have been a Professor of Materials Science at MIT, in the Materials
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`Science and Engineering Department. I am currently the Merton C. Flemings-
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`Singapore-MIT-Alliance Professor of Materials Science and Engineering and
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`currently the Lead Principal Investigator of MIT SMART LEES (Singapore-MIT
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`Alliance for Research and Technology, MIT’s Research Center in Singapore, Low
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`Raytheon2001-0005
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`Energy Electronics Systems), where I manage the fifty-million-dollar research
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`program.
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`10. My specialization is electronic materials, devices, and circuits, and I have
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`operated as a researcher, scientist, and entrepreneur in this area since the mid-
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`1980s. I researched and innovated in the areas related to the critical aspects of the
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`claimed inventions in question, such as semiconductor manufacturing and
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`processing techniques. The vast majority of my own inventions involve such
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`processing of materials and electronic devices (as only a portion of examples,
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`United States Patent Nos. 6,171,936; 6,291,321; and 7,081,410). I also research
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`processes like wafer bonding and substrate removal processes to create novel
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`monolithic 3-D integrated circuits. (E. A. Fitzgerald et al., "Monolithic 3D
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`integration
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`in
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`a CMOS
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`process
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`flow,"
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`2014 SOI-3D-Subthreshold
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`Microelectronics Technology Unified Conference (S3S), Millbrae, CA, 2014, pp.
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`1-3. doi: 10.1109/S3S.2014.7028197)
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`11.
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`I have received numerous honors and awards for my work. For example, I
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`was a co-recipient of the Institute of Electrical and Electronics Engineers (“IEEE”)
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`2011 Andrew S. Grove Award for outstanding contributions to solid state devices
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`and technology including “seminal contributions to the demonstration of Si/Ge
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`lattice mismatch strain engineering for enhanced carrier transport properties in
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`MOSFET devices,” the IEEE 2004 EDS George Smith Award for Best Paper for a
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`Raytheon2001-0006
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`paper I co-authored entitled “Fully Depleted Strained-SOI n- and p- MOSFETs on
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`Bonded SGOI Substrates and Study of the SiGe/BOX Interface,” and the TMS
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`1994 Robert Lansing Hardy Medal Award for exceptional promise of a successful
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`career in the field of metallurgy and materials science.
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`12.
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`I am the founder, co-founder or a founding team member of the following
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`companies and organizations: AmberWave Systems Corporation (a company
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`focused on strained silicon semiconductor technology); Contour Semiconductor (a
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`company focused on a unique semiconductor fabrication process for non-volatile
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`memory); 4Power LLC (manufacturer of high efficiency, low cost solar cells using
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`III-V thin films on silicon substrates); Paradigm Research LLC (commercializing
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`true monolithic III-V/Si CMOS integrated circuits); The Innovation Interface (a
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`not-for-profit organization that trains future innovators through university-
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`corporate innovation projects); and The Water Initiative (creating customized
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`point-of-drinking water solutions and scaling those solutions through micro-
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`entrepreneurs, developers and government entities).
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`13.
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`I have authored or co-authored more than 200 scientific publications. I am
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`named as an inventor or co-inventor on over 90 issued patents. Most of these
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`publications and patents relate to the growth of semiconductor materials. I have
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`supervised at least 30 doctoral candidates submitting thesis papers relating to
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`semiconductor materials and device processing.
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`Raytheon2001-0007
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`14.
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`I am being compensated for my time at the rate of $500 per hour for my
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`work in connection with this matter. The compensation is not dependent in any
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`way on the contents of this Declaration, the substance of any further opinions or
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`testimony that I may provide, or the ultimate outcome of this matter.
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`III. Materials Considered
`15.
`I have carefully reviewed the ’678 Patent and its file history. I have also
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`reviewed the references cited in the Petition (Paper No. 2) and the supporting
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`declaration of Dr. Blanchard (Ex. 1002). I have also reviewed the parties’ claim
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`construction positions from the related district court proceedings in Raytheon v.
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`Samsung Elecs. Co., Ltd. et al., Case No. 2:15-cv-00341 (E.D.T.X) (Dkt. Nos. 90,
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`and 116-1) (Ex. 2011) and the Declaration of Dr. A. Bruce Buckman submitted by
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`Patent Owner as part of that briefing (Dkt. No. 100-2) (attached as Ex. 2012).
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`16. For convenience, all of the sources that I considered in preparing this
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`declaration are listed in Appendix 2.
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`IV. Level of Ordinary Skill in the Art
`17.
`I have been informed that my analysis of the interpretation of the claims of
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`the ’678 Patent must be undertaken from the perspective of a person possessing
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`ordinary skill in the art of the ’678 Patent. I have reviewed Dr. Buckman’s
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`declaration submitted as part of the district court claim construction briefing, as
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`noted above, and Dr. Buckman opines therein that a person of hypothetical
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`ordinary skill in the art (PHOSITA) at the time of the ’678 Patent would have been
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`an individual with a Bachelor’s degree in electrical engineering, materials science,
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`or the like, with advanced classwork or industry experience in fabrication of
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`microelectronic devices. (Ex. 2012, ¶14.) I agree with this opinion and hereby
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`adopt it herein. I possess these qualifications, and I have considered the issues
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`herein from the perspective of a person of ordinary skill in the art.
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`18.
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`I have also reviewed Dr. Blanchard’s proposal as to the level of ordinary
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`skill, which does not materially differ from Dr. Buckman’s opinion noted above.
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`(See Ex. 1002, ¶56.) Thus, my opinions and assertions contained herein would not
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`differ if the Board adopted Dr. Blanchard’s proposal or Dr. Buckman’s. However,
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`I disagree with Dr. Blanchard’s assessment that a PHOSITA would be familiar
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`with flip-chip arrangements. (Id. ¶58.) In the early 1990s, flip-chip arrangements
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`would have been very leading edge and a PHOSITA would have limited
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`knowledge about the area, if any. I also disagree with Dr. Blanchard’s statement
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`that a PHOSITA “would have considered CMP and etching to be similar
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`techniques.” (Id. ¶59.)
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`19.
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`I also disagree with Dr. Blanchard’s statement that “[e]xamples of particular
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`skills possessed by the person of ordinary skill in the art are visible from the prior
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`art…” to the extent he is referring to the prior art cited in his declaration and the
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`Petition for Inter Partes Review. (Id. ¶57.) Dr. Blanchard cites to art that would
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`Raytheon2001-0009
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`have been entirely outside of the understanding of a person possessing ordinary
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`skill in the art of the ’678 Patent. For example, as described herein, a PHOSITA
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`would be totally unfamiliar with U.S. 4,426,768 to Black (“Black”), which
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`concerns pressure sensors, a specific application outside of the microelectronic
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`device fabrication subject matter of the ’678 Patent. (See Ex. 1007 at Abstract; Ex.
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`1001, 1:11-14.)
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`V. My Understanding of Patent Law
`20.
`I am not an attorney but I have had the concept of patentability explained to
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`me. I understand that a patent claim can be unpatentable under the United States
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`patent laws for various reasons, including, for example, anticipation or obviousness
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`in light of the prior art. In arriving at my opinions, I have applied the following
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`legal standards and analyses regarding patentability.
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`A. Burden of Proof
`I understand that Petitioner has the burden to prove a proposition of
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`21.
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`unpatentability by a preponderance of the evidence. I also understand that this is a
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`lower standard than the clear and convincing evidence standard that is required to
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`prove unpatentability in patent litigation before a district court.
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`B. Anticipation
`I understand that a claim is anticipated by a prior art reference if the prior art
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`22.
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`reference discloses every element in the claim. Such a disclosure can be express (it
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`Raytheon2001-0010
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`says or shows it), or it can be inherent (the element must necessarily be there even
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`if the prior art does not say it or show it). If the claim is anticipated, the claim is
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`unpatentable.
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`23.
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`I understand that the first step in an anticipation analysis is to construe the
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`claim, and the second step is to compare the construed claim to the prior art
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`reference.
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`C. Obviousness
`I understand that a patent claim may be unpatentable for obviousness even if
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`24.
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`it is not anticipated by the prior art. I understand that a patent claim is obvious if
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`the differences between the claimed intervention and the prior art are such that the
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`subject matter of the claimed invention, as a whole, would have been obvious to
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`one of ordinary skill in the art at the time the invention was made. If the claim is
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`obvious, the claim is unpatentable.
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`25.
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`I understand that before an obviousness determination is made, the level of
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`ordinary skill in the art must be considered, and the scope and content of the prior
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`art must be considered, as well. I understand that to determine the scope and
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`content of prior art, one must determine what prior art is reasonably pertinent to the
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`particular problem the inventor faced. I understand that prior art is reasonably
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`pertinent if it is in the same field as the claimed invention, or is from another field
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`that a person of ordinary skill in the art would look to in trying to solve the
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`problem.
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`26.
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`I understand that a patent claim may be obvious if the prior art would have
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`suggested, motivated, or provided a reason to one of ordinary skill in the art to
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`combine certain prior art references to arrive at the elements of the claim. I also
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`understand that one can look at interrelated teachings of multiple patents, the
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`effects of demands known to the design community or present in the marketplace,
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`and the background knowledge possessed by a person having ordinary skill in the
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`art—all in order to determine whether there was an apparent reason to combine the
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`known elements in the fashion claimed by the patent at issue. I further understand
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`that a person of ordinary skill is a person of ordinary creativity, not an automaton.
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`This person of ordinary creativity works in the contexts of a community of
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`inventors and of the marketplace. The obviousness inquiry needs to reflect these
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`realities within which inventions and patents function. In order to arrive at a
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`conclusion that an invention is obvious, it can be helpful to identify a reason that
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`would have prompted a person of ordinary skill in the relevant field to combine the
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`elements in the way the claimed invention does.
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`D. Claim Construction
`27. For the purposes of my opinions related to the issue of patentability of the
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`’678 Patent, I have been informed that, because the ’678 Patent is now expired and
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`its claims cannot be amended in this proceeding, the claims of the ’678 Patent are
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`to be interpreted using the same claim construction standards as are applied in a
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`district court proceeding, which I understand are generally their ordinary and
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`customary meaning as understood by a person of ordinary skill in the art at the
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`time of invention considering the specification, claims and file history of the
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`patent.
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`VI. Relevant Time Frame
`28.
`I understand that anticipation and obviousness must be evaluated at the time
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`the invention was made. I understand that the declarations of the inventors of the
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`’678 Patent were submitted in connection with IPR 2015-01201. Like my
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`declaration in IPR2015-01201 (See IPR2015-01201, Ex. 2019), I assume for
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`purposes this declaration that that Claims 1-5, 8-10, and 13-18 were conceived and
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`reduced to practice by August 9, 1990 and that Claims 6-7 and 11-12 were
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`conceived and reduced to practice by June 1991. I will assume for the purpose of
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`this declaration that August, 1990 was the date the inventions in Claims 1-5, 8-10,
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`and 13-18 were made, and that June 1991 was the date the inventions in Claims 6-
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`7 and 11-12 were made, with the understanding that my testimony will also be
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`applicable to some time prior to those dates, approximately the early 1990s. I may
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`refer to this time period as the “relevant time frame,” and my testimony concerning
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`obviousness is directed to this time frame, even if I occasionally do not explicitly
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`use a past tense.
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`29.
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`I also understand that the front page of the ’678 Patent (left column, field
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`“[63] Continuation of Ser. No. 6,120”) indicates the first application related to the
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`’678 Patent was filed on January 19, 1993. (Ex. 1001.) For purposes of my
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`declaration and analysis, whether the Board decides to accept the August 1990 and
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`June 1991 invention dates or the January 19, 1993 filing date of the earlier-filed
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`application is inconsequential. The analysis presented herein also applies if the
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`Board decides that the ’678 Patent has a later date of invention and therefore the
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`relevant time frame is in 1993 rather than in 1990.
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`VII. Technical Background
`A.
`Integrated Circuit Manufacturing
`1. Moore’s Law
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`30. To understand the invention of the ’678 Patent, it is important to consider
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`the status of the miniaturization of integrated circuits at the time of the invention in
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`the early 1990s. The progress in miniaturization is central to the context of the
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`invention since the ’678 Patent describes a method for closely integrating silicon
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`integrated circuits into a more complex and compact integrated system, i.e.
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`miniaturization of integrated electronic systems.
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`31.
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`In the 1950s when transistors (also called “solid state amplifiers”, an
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`evolutionary
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`jump from existing vacuum
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`tube
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`technology) first became
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`commercially practical, designers of electronic products composed of such
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`components realized the “tyranny of numbers” would limit that miniaturization.1
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`The phrase refers to the fact that the components would need many electrical
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`connections to other components and, as the components got smaller, such
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`interconnection in the desired systems could not be practically accomplished by
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`hand. The ability to place many transistors next to each other simultaneously in
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`the same piece of semiconducting silicon allowed for these transistors to be
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`connected to each other in one step by depositing metal films across the piece of
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`semiconductor and etching the film such that metal line traces connected
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`transistors to each other in desired patterns. This processing was known as “planar
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`processing”2 and it formed modern “integrated circuits.” Over time, layers of
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`metal line traces separated by dielectric insulation were applied, building a planar
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`network of metal lines interconnecting the various transistors to each other. Many
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`1 “The Technological Impact of Transistors”, J.A. Morton and W.J. Pietenpol,
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`Proceedings of Institute the of Radio Engineers (1958) 955. (Ex. 2013.)
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`2 U.S. Patent No. 2,981,877. (Ex. 2014.)
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`processes across silicon wafers were developed to manufacture many such
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`integrated circuits in a silicon wafer, and in batches of silicon wafers in
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`production.3 Thus, planar processing produces transistors in a plane, that is, the
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`plane of the starting silicon wafer blank.
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`32. These methods of producing integrated circuits resulted in an economic
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`feedback loop, in which investment in equipment and processes to produce
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`evermore increased transistor densities, and therefore, integrated circuit density,
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`resulted in an exponential rise in manufactured transistor density. In other words,
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`more and more transistors were being rapidly squeezed into smaller areas in the
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`plane of the wafer. This two-dimensional (2-D) techno-economic law, in which
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`transistor density in integrated circuits exponentially increases with time in the
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`silicon wafer-plane, is referred to as Moore’s Law, named after an Intel founder
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`that recognized the trend in 19654 and updated it in 1975.5 Since Moore’s Law is
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`3 “VLSI Technology,” S.M. Sze, McGraw-Hill, New York (1983). (Ex. 2015.)
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`4 “Cramming more components onto integrated circuits”, G.E. Moore, Electronics
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`38 (1965). (Ex. 2016.)
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`5 “Progress in Digital Integrated Electronics”, G.E. Moore, International Electron
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`Devices Meeting, IEEE, 1975, pp. 11-13. (Ex. 2017.)
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`exponential, it dominated the design of integrated systems from the 1960s and into
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`the new millennium. Thus, at the time of the invention, the central driving force
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`for miniaturization was this 2-D integration. Integrating pieces of silicon in three
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`dimensions, for the majority of those creating integrated systems, was unnecessary
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`at the time of invention, since at that time Moore’s Law reliably allowed a much
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`higher degree of integration in-plane at very low cost, year after year.
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`2.
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`Advanced Packaging
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`33. Moore’s Law resulted in a standardized packaging industry in which the
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`integrated circuit could be mounted, and connections from the integrated circuit to
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`the pins of the package could be accomplished inexpensively. The package
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`requirements are minimized by the progress of Moore’s Law: increased transistor
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`density also decreased power use per function, resulting in thermal requirements
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`that could be managed with evolutionary package development.
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`34. The ’678 Patent describes methods of three-dimensional (3-D) integration,
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`in which integrated circuits processed from methods used in microelectronic
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`processing3 can be stacked in the dimension perpendicular to the 2-D plane of
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`Moore’s Law microelectronic fabrication. At the time of invention, these methods
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`were ahead of their time and forward-looking since chip design and Moore’s Law
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`were making such rapid progress that conventional low-cost silicon packaging (in
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`2-D) was sufficient. 3-D would become most significant when Moore’s Law no
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`longer delivered progress in 2-D that scaled with the goals of integrated systems.
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`Indeed, 3-D has gained importance as Moore’s Law has slowed and now does not
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`deliver the required increases demanded by integrated systems, and hence the
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`importance of the ’678 Patent has increased as manufacturers have increasingly
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`applied such methods of 3-D integration.
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`35. The defense industries were leaders in much of the advanced packaging
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`industry and 3-D integration due to their need to miniaturize ahead of the
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`commercial capability, but their defense customers could support the costs. The
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`’678 Patent was born from such early investigations into increasing component and
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`circuit density. As Moore’s Law has slowed today, advanced 3-D packaging is
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`deployed more commonly underscoring the significance and early timing of
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`the’678 Patent.
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`36. The groundbreaking methods disclosed in the ’678 Patent were driven by
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`possible new configurations of semiconductors that would transform the field of
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`image processing, important in early defense applications. Specifically, exposing
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`the backside of a chip (through the transfer, flip and etch methods described in the
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`’678 Patent) would allow electronics to be placed behind an image sensor. This
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`allows better low-light performance (because the light photons don’t have to
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`navigate through a mesh of wires in a back-illuminated sensor (BSI) arrangement)
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`and less image signal noise (again, because the electronics are behind the image
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`sensor). Such advanced cameras were a very early example of what we call “3-D”
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`integration today.
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`3. Microelectronic Processes
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`37. Many processes were developed to allow modern microelectronics to
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`become a reality.6 General materials deposition and material removal processes
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`are the key to microelectronic fabrication. By combining with photolithography,
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`patterns can be created in multiple layers that form the microelectronic circuit.
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`Layers of a material are deposited across a silicon wafer, and
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`then
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`photolithography is used to pattern that material with a mask, followed by methods
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`to remove areas of the deposited material. This process sequence is repeated
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`multiple times to create transistors and their interconnections in the plane of the
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`silicon wafer.
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`VIII. Predictability in the Art
`38.
`I disagree with Dr. Blanchard’s opinion that the field of the ’678 Patent was
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`predictable in the relevant time frame. (Ex. 1002, ¶61.) The most valuable patents
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`are seemingly simple ideas that may only appear predictable in hindsight. It is
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`6 “Silicon Processing”, D.C. Gupta, ASTM Special Technical Publication 804,
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`Philadelphia (1983). (Ex. 2018.)
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`important to view the ’678 Patent with respect to the time frame that the processes
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`and technologies were readily available to a PHOSITA.
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`39. First, as described above, the semiconductor industry was largely focused on
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`2-D miniaturization at the time of invention of the ’678 Patent. The ’678 Patent
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`pioneered 3-D integration for applications like state-of-the-art image sensors for
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`defense and introduced a technique for semiconductor fabrication that would
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`greatly enhance image processing.
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`40.
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`In the early 1990s, the progression of Moore’s Law (the approximate
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`doubling of transistor density every two years) broadly obviated the need for
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`thinking about ways to integrate electronics outside of the power-law progression
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`of integration continuing in two-dimensions. In other words, with opportunity
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`occurring everywhere simply by following industrial trend of Moore’s Law, new
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`integrated circuits could be designed with increased integration without the need
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`for the methods described in the ’678 Patent. Microelectronic silicon wafers were
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`progressing so fast that design and invention centered around silicon processes and
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`new integrated circuit designs based on such fast-changing processes. Mainstream
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`packaging solutions over time advanced, but “tight integration” was progressing
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`fine in two-dimensions.
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`41. Second, the three-layer substrates (known in silicon integrated circuit area as
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`“silicon on insulator” or “SOI”) discussed as a preferred embodiment for the “first
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`substrate” in the ’678 Patent were new and only becoming realized commercially
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`at that time. Integrated circuit manufacture on such substrates in the late 1980’s
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`and early 1990’s was not considered mainstream. It is the rise of the availability of
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`such new materials processes and structures at the time, combined with a future
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`vision of increased integration beyond two-dimensions, that stimulated the field of
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`invention of the ’678 Patent.
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`42. At the time of the ’678 Patent, processing new SOI substrate technology
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`with silicon microelectronics at wafer-scale
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`to
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`increase
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`three-dimensional
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`integration was not obvious or predictable. In addition, such innovation was
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`contemporarily unwarranted in most driving markets since silicon microelectronics
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`itself was then-satisfactorily progressing in two-dimensions, eliminating the need
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`for a more complex and expensive process involving multiple wafers and
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`additional processing for increased integration. The inventors of the ’678 Patent
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`foresaw that, as two-dimensional transistor density increased and progress slowed,
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`integrated circuit density could be increased in other complex products, leading to
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`higher system-level advantages.
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`IX. The ’678 Patent
`43.
`I have reviewed the Technology Tutorial presented in Patent Owner’s
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`district court cases (Ex. 2019A-F) and agree it accurately depicts the background
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`of the technology. The ’678 Patent covers methods for making microelectronic
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`devices, also known as semiconductors. The claimed methods require furnishing a
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`first substrate with three layers, (1) an etchable layer, (2) an etch-stop layer
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`overlying the etchable layer, and (3) a wafer overlying the etch-stop layer; forming
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`a microelectronic circuit element in the exposed side of the wafer of the first
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`substrate opposite to the side overlying the etch-stop layer; and then transferring
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`the microelectronics-carrying wafer from a first substrate support to a second
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`substrate support, called the second substrate. (Ex. 1001, 2:15-23.) Then using an
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`etchant, the claimed methods remove the etchable layer located at the bottom
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`portion of the first substrate support to complete the device (the device can then be
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`further processed or incorporated into a larger assembly). (Id.)
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`44. The patented methods permit access to the back side of the wafer. Engineers
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`can use the back side of the device alone, such as for an image sensor, or in
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`combination with additional micro-circuits to build a stacked semiconductor chip.
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`(Ex. 1001, 2:9-15, 32-33.)
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`X.
`45.
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`Prosecution History of the ’678 Patent
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`I understand of the ’678 Patent faced a single Office Action in its
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`prosecution history. (Ex. 2002.) I understand that the Examiner cited the
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`“Riseman” reference in support of this rejection. (See Id.)
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`46. The Examiner also cited two references that describe epoxy, U.S. Patent
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`Nos. 4,612,083 (“Yasumoto”) (Ex. 2003) and 4,815,208 (“Raschke”) (Ex. 2004).
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`Yasumoto teaches two circuits that are “adhered by an adhesive resin.” (Ex. 2002
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`at 3 (citin