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`U.S. UTILITY Patent Application
`PATENT DATE
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`„,,,„SC (cid:9)
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`'AUG 31 2004
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`DRAWINGS
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`FILED WITH: F.: DISK (CRF) 0 FICHE (cid:9)
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`90
`91
`92
`93
`94
`95
`96
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`

`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`II
`111111111 1111
`11
`11
`Bib Data Sheet
`
`II
`111
`
`11
`
`II
`
`II V
`
`III (cid:9)
`
`FILING DATE
`03/31/2000
`
`RULE
`
`SERIAL NUMBER
`09/540,610
`
`APPLICANTS
`
`James E. Nulty, San Jose, CA;
`
`Christopher J. Petti, Mountain View, CA;
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virgima 22313-1450
`www.uspto.gov
`
`CONFIRMATION NO. 2171
`
`CLASS
`257
`
`GROUP ART UNIT
`2815
`
`ATTORNEY DOCKET
`NO.
`16820.P097
`
`
`** CONTINUING DATA
`This application is a DIV of 08/577,751 12/22/1995 PAT 6,066,555
`
`FOREIGN APPLICATIONS
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`IF REQUIRED, FOREIGN FILING LICENSE GRANTED
`** 06/02/2000
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`Foreign Priority clairo3d (cid:9)
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`35 USC 119 (a-d) colditions met (cid:9)
`
`yes D no
`yes (:3 no El Met after Allowance
`erified and Acknoihiedged Examiner's Signature (cid:9)
`Initials
`
`1111nMINMENNIN
`
`DDRESS
`3320
`EVAN L =kW GROUP LLC
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`STATE OR
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`SHEETS
`
`TOTAL
`
`INDEPENDENT
`
`COUNTRY
`CA
`
`DRAWING
`8
`
`CLAIMS
`13
`
`CLAIMS
`2
`
`TITLE
`STRUCTURE HAVING REDUCED LATERAL SPACER EROSION
`
`FILING FEE
`
`RECEIVED
`990
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`FEES: Authority has been given in Paper
`to charge/credit DEPOSIT ACCOUNT
`No. (cid:9)
`for following:
`No.
`
`(cid:9)+.10116111111111111
`
`D All Fees
`
`1.16 Fees ( Filing)
`
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`D 1.18 Fees ( Issue )
`1:1 Other (cid:9)
`
`
`
`5
`
`(cid:9)
`

`
`111111111111111111114$ (cid:9)
`Bib Data Sheet
`
`.J1111111111
`
`UNITED STATES DEPARTMENT OF COMMERCE
`Patent and Trademark Office
`Address: COMMISSIONER OF PATENTS AND TRADEMARKS
`Washington, D.C. 20231
`
`SERIAL NUMBER
`09/540,610
`
`FILING DATE
`03/31/2000
`RULE (cid:9)
`
`—
`
`F. • • (cid:9)
`
`,
`James E. Nulty, San Jose, CA;
`Christopher J. Petti, Mountain View, CA;
`
`** CONTINUING DATA *************************
`
`** FOREIGN APPLICATIONS ******************** (cid:9)
`
`CLASS
`438
`
`GROUP ART UNIT
`2812
`
`ATTORNEY
`DOCKET NO.
`16820.P097
`
`App
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`IF REQUIRED, FOREIGN FILING LICENSE GRANTED
`—
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`Foreign Priority claimed (cid:9)
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`35 USC 119 (a-d) conditions (cid:9) LI (cid:9)
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`Initials
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`STATE OR
`COUNTRY
`CA
`
`SHEETS
`DRAWING
`8
`
`TOTAL
`CLAIMS
`13
`
`INDEPENDENT
`CLAIMS
`2
`
`Blakely Sokoloff Taylor & Zafman
`12400 Wilshire Boulevard
`Seventh Floor
`Los Angeles ,CA 90025
`
`TITLE
`
`—
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`STRUCTURE HAVING REDUCED LATERAL SPACER EROSION
`r
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`FILING FEE (cid:9)
`RECEIVED
`690
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`
`'FEES: Authority has been given in Paper
`No. (cid:9)
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`No. (cid:9)
`for following:
`
`U All Fees
`
`IZ1 1.16 Fees ( Filing)
`
`1:1 1.17 Fees ( Processing Ext. of
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`
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`
`L.1 Other
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`
`6
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`(cid:9)
`

`
`•UNXTEE) STATE,
`PATENT 'Afar)
`TRADEMARK OFF E
`
`11 11 1[111111111111 1111111111111111111 11 11
`Bib Data Sheet
`
`SERIAL NUMBER
`09/540,610
`
`Page 1 of 1
`
`.C‘trimiSialO'ner'fcir Piderit.s.
`Wash gton. DC 2021.
`' wvptcts:gov
`
`CONFIRMATION NO. 2171
`
`FILING DATE
`03/31/2000
`RULE
`
`CLASS
`257
`
`GROUP ART UNIT
`2815
`
`ATTORNEY
`DOCKET NO.
`16820.P097
`
`APPLICANTS
`James E. Nulty, San Jose, CA;
`Christopher J. Petti, Mountain View, CA;
`
`** CONTINUING DATA ************************* Ye5 (cid:9) P\ 111"L.'"."`' (cid:9)
`' C 4 VI, (cid:9)
`
`* FOREIGN APPLICATIONS ******************** ilon e
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`
`IF REQUIRED, FOREIGN FILING LICENSE GRANTED
`06/02/2000
`1:.1 yes frifio
`Foreign Priority claimed (cid:9)
`35 USC 119 (a-d) conditions (cid:9) 0 yes Lid no ZI Metafter
`met
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`'.ADDRESS
`26263
`
`Initials
`
`STATE OR
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`
`SHEETS
`DRAWING
`8
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`TOTAL
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`13 (cid:9)
`
`INDEPENDENT
`CLAIMS
`2
`
`TITLE
`
`STRUCTURE HAVING REDUCED LATERAL SPACER EROSION
`
`FILING FEE
`RECEIVED
`690
`
`FEES: Authority has been given in Paper
`No. (cid:9)
`to charge/credit DEPOSIT ACCOUNT
`No. (cid:9)
`for following:
`
`0 All Fees
`
`lj 1.16 Fees ( Filing )
`
`ZI 1.17 Fees ( Processing Ext. of
`time)
`
`1.18 Fees ( Issue )
`
`2 Other
`
`121 Credit
`
`PAW, PPPPP
`
`PPPPPP
`
`7
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`

`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United Sitar'', Pa in nt and 'Crud tam, rk Of San
`Addrces: COMMISSIONER FOR PATENTS
`P.O. Box 1450
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`wv, W.1.1/11,g0V
`
`CONFIRMATION NO. 2171
`
`1111111111111111
`11
`Bib Data Sheet
`
`SERIAL NUMBER
`09/540,610
`
`..........,
`
`APPLICANTS
`
`FILING DATE
`03/31/2000
`
`RULE
`
`CLASS
`257
`
`GROUP ART UNIT
`2815
`
`ATTORNEY DOCKET
`NO,
`16820.P097
`
`,
`
`James E. Nulty, San Jose, CA;
`
`Christopher J. Petti, Mountain View, CA;
`
`
`** CONTINUING DATA
`This application is a DIV of 08/577,751 12/22/1995 PAT 6,066,555
`
`** FOREIGN APPLICATIONS ********************
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`** 06/02/2000
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`TITLE
`STRUCTURE HAVING REDUCED LATERAL SPACER EROSION
`
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`To the AsOitariPamatConer for Patents:
`
`PATENT APPLICATION TRANSMITTAL LETTER
`
`Case No. 10200/12
`
`Transmitted herewith for filing is the patent application of: NULTY, et al. for: METHOD FOR ELIMINATING LATERAL SPACER
`
`EROSION ON ENCLOSED CONTACT TOPOGRAPHIES DURING RF SPUTTER CLEANING. Enclosed are:
`
`El (cid:9)
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`8 sheet(s) of drawings, 34 pages of application (including title page), and the following Appendices:
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`or
`or
`Or
`Or
`Or
`or
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`Other Than
`Smal Entit
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`Rate
`
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`3/V
`Date
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`Paul E. Rauch, Ph.D.
`BRINKS HOFER GILSON & LIONE
`Registration No. 38,591
`
`Rev. Nov-98
`X:\PER\10200-12 Transmittal letter 000331.doc
`
`10
`
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`Our Reference: 16820.P097
`
`APPLICATION FOR UNITED STATES PATENT
`
`FOR
`
`METHOD FOR ELIMINATING LATERAL SPACER
`EROSION ON ENCLOSED CONTACT TOPOGRAPHIES
`DURING RF SPUTTER CLEANING
`
`Inventors: JAMES E. NULTY
`CHRISTOPHER J. PE ill
`
`Prepared by:
`
`BLAKELY SOKOLOFF TAYLOR & ZAFMAN
`12400 Wilshire Boulevard
`Seventh Floor
`Los Angeles, CA 90025
`(310) 207-3800
`
`I hereby certify that this correspondence is
`being deposited with the United States Postal'
`Service as Express Mail (Label No: 113 -7Ccotc'1 (.S1_
`in an envelope addressed to: Commissioner of Patents
`gton, D.C. 20231 on: Vsa)--titrve-22..., 119S—
`and (cid:9)
`(2,12a /9C
`
`Name
`
`Date
`
`11
`
`

`
`DACKGROUND OF THE INVENTION
`
`Field of the Invention:
`
`The invention relates to semiconductor device processes, and more
`
`particularly, to improved methods for etching openings in insulating layers and a
`
`5
`
`semiconductor device with well defined contact openings.
`
`Background of the Invention
`
`In the fabrication of semiconductor devices, numerous conductive device
`
`regions and layers are formed in or on a semiconductor substrate. The conductive
`
`regions and layers of the device are isolated from one another by a dielectric.
`
`10 (cid:9)
`
`Examples of dielectrics include silicon dioxide, Si02, tetraethyl orthosilicate glass
`
`("TEOS"), silicon nitrides, SixNy, silicon oxynitrides, SiOxNy(Hz), and silicon
`
`dioxide/silicon nitride/silicon dioxide ("ONO"). The dielectrics may be grown, or
`
`may be deposited by physical deposition (e.g., sputtering) or by a variety of chemical
`
`deposition methods and chemistries (e.g., chemical vapor deposition ("CVD")).
`
`15 Additionally, the dielectrics may be undoped or may be doped, for example with
`
`boron, phosphorous, or both, to form, for example, borophosphosilicate glass
`
`("BPSG"), phOsphosilicated glass ("PSG"), and borophosphosilicate tetraethyl
`
`orthosilicate glass ("BPTEOS").
`
`At sev al stages of the fabrication of semiconductor devices; it is necessary to
`
`972.
`20 make openings in e dielectric to allow for contact to underlying regions or layers.
`
`PA
`
`Generally, an opening "through a dielectric exposing a diffusion region or an
`
`opening through a dielect c layer between polysilicon and the first metal layer is
`
`called a "contact opening", wÌik an opening in other oxide layers such as an
`opening through an intermetal di ectric layer is referred to as a "via". For purposes
`
`JCS/W113/mp
`
`-1- N (cid:9)
`
`16820.P097
`
`12
`
`

`
`of the cla. ed invention, henceforth "contact opening" or "contact region" will be
`
`used to refer "to contact openings and/or via. The opening may expose a device
`
`region within ti- silicon substrate, such as a source or drain, or may expose some
`
`other layer or strutçre, for example, an underlying metallization layer, local
`
`interconnect layer, or' tructure such as a gate. After the opening has been formed
`
`exposing a port-ion of the egion or layer to be contacted, the opening is generally
`
`cleaned with a sputter etch, e.g., a Radio-Frequency ("RF") sputter etch, and then the
`
`opening is filled with a cond t\ive material deposited in the opening and in
`i.
`
`electrical contact with the under xingregiony. 1 .er.—
`
`10 (cid:9)
`
`To form the openings a patterning layer of photoresist is first formed over the
`
`dielectric layer having openings corresponding to the regions of the dielectric where
`
`the dielectric layer openings are to be formed. In most modern processes a dry etch
`
`is then performed wherein the wafer is exposed to a plasma, formed in a flow of one
`
`or more gases. Typically, one or more halocarbons and/or one or more other
`
`15
`
`halogenated compounds are used as the etchant gas. For example, CF4, CHF3 (Freon
`
`23), SF6, NF3, and other gases may be used as the etchant gas. Additionally, gases
`
`such as 02, Ar, Ni and others may be added to the gas flow. The particular gas
`
`mixture used will depend on, for example, the characteristics of the dielectric being
`
`etched, the stage of processing, the etch tool being used, and the desired etch
`
`20 (cid:9)
`
`characteristics, i.e., etch rate, sidewall slope, anisotropy, etc.
`
`Many of the etch characteristics are generally believed to be affected by
`
`polymer residues that deposit during the etch. For this reason, the fluorine to
`
`carbon (F/C) ratio in the plasma is considered an important determinant in the etch.
`
`In general, a plasma with a high F/C ratio will have a faster etch rate than a plasma
`
`25 with a low F/C ratio. At very low rates, i.e., high carbon content, polymer
`
`deposition occurs and etching ceases. The etch rate as a function of the F/C ratio is
`
`jCS/W113/mp (cid:9)
`
`-2- (cid:9)
`
`16820.P097
`
`13
`
`

`
`typically different for different materials. The difference is used to create a selective
`
`etch, by using a gas mixture that puts the F/C ratio in the plasma at a value that
`
`leads to etching at a reasonable rate for one material, and that leads to no etching or
`
`polymer deposition for another. For example, an etchant that has an etch rate ratio
`
`or a selectivity ratio of two to one for silicon nitride compared to silicon dioxide is
`
`an effective stripper of silicon nitride from the semiconductor substrate, because it
`
`will selectively strip silicon nitride over silicon dioxide on a substrate surface. An
`
`etchant that has an etch rate ratio or a selectivity ratio of 0.85 to one for silicon
`
`nitride compared to silicon dioxide is not considered an effective stripper of silicon
`
`10 nitride from the semiconductor substrate because the etchant will not effectively
`
`strip silicon nitride to the exclusion of silicon dioxide.
`
`The selectivity of the etch process is a useful parameter for monitoring the
`
`process based on the etch rate characteristic of the particular etchant. As noted
`
`above, particular etchants or etchant chemistries attack different materials at
`
`15
`
`different etch rates. With respect to dielectrics, for example, particular etchants
`attack silicon dioxide, BPTEOS, mos, and silicon nitride dielectrics at different rates.
`
`To make openings in a substrate comprising a contact region surrounded by
`
`different dielectric layers, e.g., a dielectric layer of TEOS surrounded by a dielectric
`
`layer of silicon nitride, a process will utilize different etchants to make openings
`
`20 (cid:9)
`
`through the different dielectrics. Thus, the different etch rates of particular dielectric
`
`layers for an etchant may be used to monitor the creation of an opening through a
`
`dielectric layer.
`
`Further, by adjusting the feed gases, the taper of the sidewall in the etched
`
`opening of the dielectric can be varied. If a low sidewall angle is desired, the
`
`25
`
`chemistry is adjusted to try to cause some polymer buildup on the sidewall.
`
`Conversely, if a steep sidewall angle is desired, the chemistry is adjusted to try to
`
`JCS/WTB/mp (cid:9)
`
`-3- (cid:9)
`
`16820.P097
`
`14
`
`

`
`prevent polymer buildup on the sidewall. Varying the etch gas pressure, for
`
`example, has a significant effect on the shape of the opening. This is because the
`
`etchant ions generally arrive in a direction perpendicular to the substrate surface,
`
`and hence strike the bottom surfaces of the unmasked substrate. The sidewalls of
`
`etched openings, meanwhile, are subjected to little or no bombardment. By
`
`increasing the pressure of the etch gas, the bombardment directed toward the
`
`sidewalls is increased; by decreasing the pressure of the etch gas, the bombardment
`
`directed toward the sidewalls is decreased. The changing of the etch chemistry is
`also directly related to selectivity. Etchants that provide a near 900 sidewall angle are
`
`10 generally not highly selective while highly selective etches typically produce a
`
`sloped sidewall.
`
`Following the dielectric etch(es) and prior to any conductive material
`
`deposition in a contact region, native oxide on top of the conducting layers in the
`
`contact region is removed or cleaned through a non-chemical sputter etch, e.g., an
`
`15 RF sputter etch. In addition to alleviating the contact region of native oxide, the
`
`sputter etch can erode any insulating dielectric layer or layers. Thus, the parameters
`
`of the sputter etch must be carefully monitored so as not to excessively erode the
`
`insulating dielectric layer(s) and expose other underlying conductive material.
`
`Exposing insulated conductive material adjacent to the conductive material in the
`
`20 (cid:9)
`
`contact region results in poor quality contacts or a short circuit through the
`
`underlying conductive material. For a thorough discussion of oxide etching, see S.
`
`Wolf and R.N. Tauber, Silicon Processing for the VLSI Era, Vol. 1, pp. 539-85 (1986).
`
`The preced (cid:9)
`
`discussion focused on the making of openings, e.g., contact
`
`openings, in dielectri material on a semiconductor substrate. The same principles
`
`are used in constructin device regions with a dielectric layer or layers. As
`
`geometries shrink, the for ing of discreet devices on a semiconductor substrate
`
`JCS/WTB/mp (cid:9)
`
`-4- (cid:9)
`
`16820.1)097
`
`15
`
`

`
`becomes mi:re:) cialzed. Specialized deposition and etching techniques permit
`
`the density of semiconitor elements on a single chip to greatly increase, which
`
`translates into larger memory, faste (cid:9)
`
`rating speeds, and reduced production costs.
`
`A typical metal oxide semiconductor (MOS) transistor, e.g., NMOS or PMOS
`
`transistor, generally includes source/drain regions in a substrate, and a gate
`
`electrode formed above the substrate between the source/drain regions and
`
`separated from the substrate by a relatively thin dielectric. Contact structures can be
`
`inserted to the source/drain regions and interlays can overlie the contact structures
`
`and connect neighboring contact structures. These contact structures to the
`
`10 diffusion region are isolated from the adjacent gate by dielectric spacer or shoulder
`
`portions. The dielectric spacer or shoulder portions also isolate the gate from the
`
`diffusion region.
`
`Conventional contact structures limit the area of the diffusion region, because
`
`the contact hole is aligned to these regions with a separate masking step, and extra
`
`15
`
`area must be allocated for misalignment. Proper alignment is necessary to avoid
`
`shorting the contact structure to the gate or the diffusion well. The larger contact
`
`area means a smaller density of elements on a structure. The larger contact area is
`
`also responsible for increased diffusion-to-substrate junction capacitance, which
`
`limits device speed.
`
`20 (cid:9)
`
`A self-aligned contact eliminates the alignment problems associated with
`
`conventional contact structures and increases the. device density of a structure. A ,
`
`self-aligned contact is a contact to a source or drain diffusion region. A self-aligned
`
`contact is useful in compact geometries because it can overlap a conducting area to
`
`which it is not supposed to make electrical contact and can overlap the edge of a
`
`25 (cid:9)
`
`diffusion region without shorting out to the well beneath. Consequently, less
`
`JCS/WT13/mp (cid:9)
`
`-5- (cid:9)
`
`16820.P097
`
`16
`
`

`
`contact area is needed and gates or conductive material lines, e.g., polysilicon lines,
`
`can be moved closer together allowing more gates or lines on a given substrate than
`
`traditional contacts.
`
`gure 1 illustrates a self-aligned contact between two gate structures. Figure
`
`1(A) is a e anar top view of the contact. Figure 1(B) is a planar cross-sectional view
`
`of a self-ali:, ed contact between a pair of gates taken through line 1(B) of Figure
`
`1(A). Figure 1 C) is a planar cross-sectional view of a self-aligned contact between a
`
`pair of gates tak through line 1(C) of Figure 1(A).
`
`The self-align
`
`contact is a contact to a source or drain diffusion region (n+
`
`10 or p+ silicon) 140 that
`
`n overlap the edge of the diffusion region 140 without
`
`shorting out to the well be eath the diffusion region 140. This can be seen most
`
`illustratively through Figure C). In Figure 1(C), the contact 130 does not lie directly
`
`in the diffusion region 140, but i misaligned and slightly overlaps the field oxide.
`
`In this illustration, the self-aligned contact is not directly over the diffusion region
`
`15 but extends over (i.e., overlaps) a wel portion 170. The self-aligned contact does not
`
`short to the well portion 170 because th self-aligned contact is separated from the
`
`well 170 by the field oxide.
`
`The self-aligned contact 130 is separate from a conducting polysilicon layer
`
`110 by an encapsulating dielectric layer 120 such at the contact 130 can also overlap
`
`20
`
`the polysilicon layer 110 without making electrical ontact to the layer 110 or gate.
`
`The polysilicon layer 110 is separated from the source drain diffusion region 140 by
`
`a dielectric spacer or shoulder 150 of the same or differe t dielectric material as the
`
`dielectric layer 120 directly above the conducting polysilic
`
`A distinct dielectric etch stop layer 125 overlies the enca sulating dielectric
`
`25
`
`layer 120. The etch stop layer 125 permits subsequent etching of\ the substrate
`
`JCS/WTB/mp (cid:9)
`
`-6- (cid:9)
`
`16820.P097
`
`17
`
`

`
`without ris of exposing the device structures and layers because the device
`
`structuring and (cid:9)
`
`ers are protected from excessive etching by the etch stop layer.
`
`The diffusion contact self-aligning because the structure can be etched to the
`
`substrate over the source rain diffusion region 140 while the dielectric spacer 150
`
`5 protects the polysilicon layer. (cid:9)
`
`Even
`Even if a photoresist that protects the polysilicon
`
`layer 110 from the etchant is misati ed with respect to the polysilicon layer 110, the
`
`dielectric spacer 150 prevents shorts t (cid:9)
`
`e polysilicon layer 110 when the contact (cid:9) 130
`
`is provided for the diffusion region 140. -
`
`e current practice with respect to forming contact regions, particularly self-
`
`\ 12h>
`aligned c. tact regions, that are in electrical contact with gates, interconnect lines, or
`10 (cid:9)
`
`other struc es in small feature size structures utilize etchants with high selectivity
`
`to protect unde ing regions, like the etch stop layer and the first insulating layer.
`
`Figure 2 demonstr es a typical prior art process of forming a sell-aligned contact
`
`region adjacent to a gate. In Figure 2(A), a gate oxide layer 210 is formed on a
`
`15
`
`substrate 200 with a conc\i‘ cting layer, for example a polysilicon layer 220, overlying
`
`the gate oxide layer 210, and n insulating layer, for example a TEOS layer 230,
`
`overlying the polysilicon layer 29,0. Adjacent to the polysilicon layer is a contact
`\\.
`opening region 270. The polysilico layer 220 is separated from the contact region
`
`270 by an insulating spacer portion, foi'xample a TEOS spacer portion 235. A
`
`20
`
`separate insulating or etch stop layer, for\ xample a silicon nitride layer 240 overlies
`
`the TEOS layer 230 and the contact region 2 . A blanket layer, for example a doped
`
`insulating layer like a BPTEOS layer 250, plana (cid:9)
`
`overlies the etch stop layer 240.
`
`A layer of photoresist material 280 overlies t e planarized BPTEOS layer 250
`
`to expose the contact opening 270. In Figure 2(A), a co ,tact opening 270 has been
`
`25
`
`opened through the BPTEOS layer 250. The etchant utili ed to make the opening
`
`had a high selectivity toward BPTEOS relative to silicon ru çie. When the contact
`
`JCS/WTB/mp (cid:9)
`
`-7- (cid:9)
`
`16820.P097
`
`18
`
`

`
`opening was through the BPTEOS material, the etchant did not etch or did not
`
`effectively di the silicon nitride layer 240 material. Hence the description of the
`
`silicon nitrideÌàyer 240 as an etch stop layer. The silicon nitride etch stop layer
`
`protected the under (cid:9)
`
`TEOS layer so that the polysilicon remains completely
`
`encapsulated.
`
`gure 2(A) illustrates an etch 260 to remove the silicon nitride etch stop layer
`(11.),fr 6((' 240. In t • etch illustrated in Figure 2(A), a high selectivity etch toward silicon
`nitride relati e to the underlying TEOS layer 230 material is practiced to efficiently
`
`etch the silicon tride layer and to protect the underlying 11,0S layer 230 from the
`
`10 etchant. An exam le of a high selectivity etch recipe to effectively strip silicon
`
`nitride as compared the TEOS layer is 30 sccm CHF3 and 30 sccm 02 at 60 mtorr
`
`and 100 watts of power. The result of the high selectivity etch is illustrated in Figure
`
`2(B).
`
`Figure 2(B) shows that tke silicon nitride selective etch effectively removed
`silicon nitride 240 from the conta opening 270. The selective etch for silicon
`
`15
`
`nitride compared to TEOS material, owever, left the TEOS layer 230 with a spacer
`
`portion 235 wherein the spacer portion sloping or tapered toward the contact
`
`opening. This result follows even where e spacer portion 235 is originally
`
`substantially rectangular as in Figure 2(A). (cid:9)
`
`properties of the highly selective
`
`20
`
`etch of the overlying etch stop layer will transfs m a substantially rectangular spacer
`
`into a sloped spacer. Figure 2(B) presents a polys con layer 220 encapsulated in a
`
`i hOS layer 230 with a spacer portion 235 adjacent to e contact opening 270, the
`
`spacer portion 235 having an angle 290 that is less than 5°.
`
`In addition to providing stopping points or selectivi between materials, the
`
`25
`
`use of high selectivity etches to form sloped spacer portions is the preferred practice
`
`JCS/WTB/mp (cid:9)
`
`-8- (cid:9)
`
`16820.P097
`
`19
`
`

`
`because the slo ed shape will result in good step coverage by the metal that is
`
`deposited into it. The filling of contact openings or gaps (