`
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`Nulty, et al.
`In re Patent of:
`U.S. Patent No.: 6,784,552
`Issue Date:
`August 31, 2004
`Appl. Serial No.: 09/540,610
`Filing Date:
`March 31, 2000
`Title:
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`STRUCTURE HAVING REDUCED LATERAL SPACER
`
`
`
`EROSION
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`
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`DECLARATION OF DR. VIVEK SUBRAMANIAN
`
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`I, Vivek Subramanian, of Berkeley, California, declare that:
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`1.
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`I have been retained by counsel for Petitioner SK hynix, Inc. to provide my
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`independent analysis of the issues raised in the petition for inter partes review of
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`U.S. Patent No. 6,784,552 (“the ʼ552 Patent”).
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`2.
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`I am not currently and have not at any time in the past been an employee of
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`SK hynix, Inc., SK hynix America, Inc.; SK hynix Memory Solutions, Inc.; and
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`Hynix Semiconductor Manufacturing America, Inc.
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`3.
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`I am being compensated for my time expended in connection with this
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`matter at the rate of $600 per hour, plus reimbursement of any expenses I incur. I
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`have no financial stake in this matter, and my compensation is not contingent upon
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`the outcome of this inter partes review of the ʼ552 Patent.
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`Petitioner Hynix - HYNIX-1003
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`I.
`4.
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`QUALIFICATIONS AND PROFESSIONAL EXPERIENCE
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`I am an expert in the fields of semiconductor design and semiconductor
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`fabrication, among other fields. I have over 19 years of experience as a practicing
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`engineer, researcher, technical manager and educator in these fields.
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`5.
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`I received a Bachelor’s degree summa cum laude in electrical engineering
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`from Louisiana State University in 1994, and an M.S. and Ph.D. in electrical
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`engineering, in 1996 and 1998, respectively, from Stanford University. During my
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`tenure as a graduate student at Stanford University, I received a prestigious
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`Eastman Kodak fellowship from Kodak. Between 1992 and 1994, I performed
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`research on high-performance highly scaling field effect transistors in a
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`collaborative effort with IBM. From 1994 to 1998, I performed research in high-
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`performance thin film transistors for high-performance 3D integrated logic,
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`memory, and display applications.
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`6.
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`Between 1998 and 2000, I served as a Consulting Assistant Professor in the
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`Electrical Engineering Department of Stanford University, and as a Visiting
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`Research Engineer in the Department of Electrical Engineering and Computer
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`Sciences at the University of California, Berkeley, where my research focused on
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`25nm MOSFET technologies for giga-scale integration. In this role, I worked on
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`technologies for high-performance transistor processes, and published several
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`papers as a direct outcome of this technology development.
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`7.
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`In 1998, I co-founded Matrix Semiconductor, Inc., a company that pioneered
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`the design and development of three-dimensional (3-D) integrated circuits for use
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`in high density nonvolatile memory products. A significant focus of my activities
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`was on the development of process technology for manufacturing these novel
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`memory systems. I both worked on and directly managed engineers and
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`technicians working on developing these processes. Several patents resulted from
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`this work. Following initial volume production deliveries in 2004, Matrix
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`Semiconductor was acquired by SanDisk Corporation and its memory products
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`were put into high volume production. Matrix Semiconductor was nominated to
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`the 2002 Scientific American SA50 list for visionary technology, became a Finalist
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`for the 2003 World Technology Award for Information Technology Hardware, and
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`won the 2005 EDN Innovation Award.
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`8.
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`Although my involvement with Matrix Semiconductor ended upon its
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`acquisition by SanDisk, I remain involved in the application of pioneering
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`technology through other start-up companies. I served as a Founding Scientific
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`Advisor for Kovio, Inc., a start-up company focused on semiconductor
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`manufacturing technology based on nano-particle inks and proprietary printing
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`methods for large area electronics, which was subsequently acquired by Thin Film
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`Electronics. In this role, I specifically worked on packaging issues relevant to
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`semiconductor integrated circuits. In addition, I served as the Chief Scientific
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`Advisor to QuSwami, Inc., a start-up company focusing on novel energy
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`conversion devices, through 2011. Most recently, I serve as a co-founder of
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`Dragonfly Technology, Inc., a venture-funded startup company working on
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`“Internet of Things” Devices.
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`9.
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`In July of 2000, I became an assistant professor in the University of
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`California, Berkeley’s Department of Electrical Engineering & Computer
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`Sciences. In 2005, I was promoted to the position of tenured Associate Professor of
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`Electrical Engineering & Computer Sciences at the University of California,
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`Berkeley, and, in July of 2011, I was promoted to my current position of full
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`Professor of Electrical Engineering and Computer Sciences. My current research
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`interests include advanced CMOS devices and technology and thin film
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`technologies for displays and integration applications, with a substantial focus on
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`low-cost electronics for display, low-cost logic, and sensing applications. I also
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`maintain a substantial research effort in advanced memory technology and have a
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`large research program focused on semiconductor packaging, including specific
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`efforts focused on development of interconnection strategies for packaging. I am
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`also responsible for all the semiconductor device and technology courses offered
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`within
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`the department; I
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`teach
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`these courses routinely,
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`including both
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`undergraduate and graduate courses.
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`10. My service on various electrical engineering industry groups over the years
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`includes the following:
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` serving on the International Electron Device Meeting (IEDM)’s
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`Technical Program Committee (2001-2002) and Executive Committee
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`(2003 to 2009);
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` serving on the Technical Program Committee for the Device Research
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`Conference (2000-2002);
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` serving on the Technical Program Committee for the VLSI-TSA
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`Conference (2005);
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` serving as a reviewer for the peer-reviewed publication IEEE Electron
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`Device Letters;
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` serving as a reviewer for
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`the peer-reviewed publication IEEE
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`Transactions on Electron Devices;
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` serving as a proposal reviewer/panelist for the National Science
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`Foundation;
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` serving as a proposal reviewer for the American Chemical Society;
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` being a member of the Institute of Electrical and Electronic Engineers
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`(IEEE);
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` being a member of the IEEE Electron Devices Society Organic
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`Electronics Committee (2003 to 2007); and
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` serving on the scientific advisory board to the Large Area, Organic, and
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`Printed Electronics Conference, LOPE-C (2009 to 2013).
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`11. Furthermore, I have received a number of academic awards and honors over
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`the years, including the following:
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` nominated to MIT’s Technology Review top 100 young innovators list
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`(TR100), 2002;
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` National Science Foundation Young Investigator (CAREER) Award,
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`FY2002;
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` nominated
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`to National Academy of Engineering’s Frontiers of
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`Engineering, 2002-03;
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` winner of 2002 Paul Rappaport Award for best paper in an IEEE EDS
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`Journal;
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` Best paper award, 2004 IEEE Device Research Conference;
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` Outstanding Teaching Award, EECS Department, UC Berkeley, 2005;
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`Winner of the Printed Electronics Champion Award 2008 from the
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`Printed Electronics USA Conference, 2008;
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` Awarded an adjunct Professorship from the World-Class University
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`Program at Sunchon National University in Korea; and
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` Outstanding paper award, 2012 IMAPS Microelectronics Conference,
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`for a paper specifically focused on semiconductor packaging.
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` Winner of the 2015 IEEE Kiyo Tomiyasu Award.
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`12.
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`I have also authored or co-authorized over 200 technical papers in
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`international journals and conferences and have been named inventor or co-
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`inventor on more than 40 patents covering several aspects of semiconductor
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`devices, materials, circuit design, process technology, and memory architecture.
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`13.
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`In the course of my educational and professional activities, I have become
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`familiar with the state of the art in the field of semiconductor technologies during
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`the late 1990s and early 2000s.
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`14. A complete list of my qualifications is set forth in my curriculum vitae,
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`which is attached to this report as Exhibit 1 (“Vivek Subramanian Curriculum
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`Vitae”).
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`II. MATERIALS CONSIDERED
`15.
`In writing this Declaration I have considered the following: my own
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`knowledge and experience, including my work experience in the field of
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`semiconductor design and fabrication, my industry experience in semiconductor
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`design and fabrication, and my experience in working with others involved in the
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`field. In addition, I have analyzed the following publications and materials:
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` U.S. Patent No. 6,784,552 and its accompanying prosecution file history
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`(Ex. HYNIX-1001);
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` U.S. Patent No. 5,482,894 (“Havemann”, Ex. HYNIX-1004);
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` U.S. Patent No. 4,686,000 (“Heath”, Ex. HYNIX-1005); and
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` Admitted Prior Art of the ʼ552 Patent (“APA”, Ex. HYNIX-1001).
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`16. Although for the sake of brevity this Declaration refers to selected portions
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`of the cited references, it should be understood that one of ordinary skill in the art
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`would view the references cited herein in their entirety, and in combination with
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`other references cited herein or cited within the references themselves. The
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`references used in this Declaration, therefore, should be viewed as being
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`incorporated herein in their entirety.
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`III. PERSON OF ORDINARY SKILL IN THE ART
`17.
`I am familiar with the content of the ’552 Patent, which, I have been
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`informed by counsel, has an earliest possible filing date of December 22, 1995
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`(hereinafter “the Priority Date”).
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`18. Additionally, I have reviewed the other references cited above in this
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`Declaration. Counsel has informed me that I should consider these materials
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`through the lens of one of ordinary skill in the art related to the ’552 Patent at the
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`time of the invention. I believe one of ordinary skill around December 22, 1995
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`would have had either a (i) Bachelor of Science in Electrical Engineering with 5
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`years of experience in semiconductor design and manufacture, (ii) or a masters or
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`Ph.D. degree
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`in Electrical Engineering with equivalent experience
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`in
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`semiconductor design and manufacture.
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`A. Grounds for Invalidating Patent Claims in an Inter Partes
`Review: 35 U.S.C. § 102 and/or 35 U.S.C. § 103
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`19.
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`I understand that the following restriction—which is set forth in 35 U.S.C. §
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`311(b)—limits an IPR petition to anticipation and obviousness grounds, using only
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`prior art consisting of patents or printed publications. In other words, an IPR
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`petitioner can only discuss whether another published prior art reference
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`anticipates under 35 U.S.C. § 102 or renders the challenged patent claims obvious
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`under 35 U.S.C. § 103.
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`20.
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`I understand that an IPR petitioner is prohibited from challenging a patent on
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`other grounds such as the on-sale bar, non-patentable subject matter, or invalidity
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`under 35 U.S.C. § 112 for unsupported claims or indefiniteness.
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`A. Anticipation
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`21.
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` I understand that the following standards—which are taken from 35 U.S.C.
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`§ 102—govern the determination of whether a claim in a patent is invalid as
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`“anticipated.”
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`22.
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`In general, a patent claim is invalid as “anticipated” if each and every feature
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`of the claim is found, expressly or inherently, in a single item of prior art. In
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`determining whether the single item of prior art anticipates the claim, one
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`considers not only what is expressly disclosed in the particular item of prior art, but
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`also what is inherently present or disclosed in that prior art or what inherently
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`results from its practice. Claim limitations that are not expressly found in a prior
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`art reference are inherent if the prior art necessarily functions in accordance with,
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`or includes, the claim limitations, or if the missing element or feature would be the
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`natural result of following what the prior art teaches to persons of ordinary skill in
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`the art. It is acceptable to examine evidence outside the prior art reference
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`(extrinsic evidence), including experimental testing, in determining whether a
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`feature, while not expressly discussed in the reference, is necessarily present in it.
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`Mere probabilities are not enough, but it is not required that persons of ordinary
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`skill actually recognized the inherent disclosure at the time the prior art was first
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`known or used.
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`23.
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`I understand that there are a number of different ways that anticipation can
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`occur. First, if the claimed invention was “known or used by others” in this country
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`before the asserted date of invention, then the claim is anticipated. A
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`demonstration or oral presentation could suffice; printed publications are not
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`required. Second, if the claimed invention was “in public use” in this country more
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`than one year prior to the date of the application for the patent in the United States,
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`then the claim is anticipated. Public knowledge of the invention or an enabling
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`disclosure is not required; only public use is required. Third, if the claimed
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`invention was “described in a printed publication” anywhere in the world prior to
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`the alleged invention or more than one year prior to the date of the application for
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`the patent in the United States, then the claim is anticipated. To anticipate,
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`however, the printed publication must also enable one skilled in the art to make
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`and use the claimed invention. Fourth, if the claimed invention was made in this
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`country by another inventor before the asserted date of invention, and not
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`abandoned, suppressed, or concealed, then the claim is anticipated. It is normally
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`the first inventor to conceive, rather than the first to reduce to practice, who is
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`entitled to priority, assuming that the first to conceive was reasonably diligent in
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`reducing the invention to practice from a time prior to conception by the other.
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`B. Obviousness
` I understand that the following standards govern the determination of
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`24.
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`whether a claim in a patent is obvious: Under 35 U.S.C. § 103, a claim in a patent
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`is obvious when the differences between the subject matter sought to be patented
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`and the prior art are such that the subject matter as a whole would have been
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`obvious at the time the invention was made to a person having ordinary skill in the
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`art to which said subject matter pertains.
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`25. The relevant inquiry requires consideration of four factors (although not
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`necessarily in the following order):
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` The scope and content of the prior art,
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` The differences between the prior art and the claims at issue,
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` The level of ordinary skill in the pertinent art at the time of the invention,
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`and
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` Objective factors indicating obviousness or non-obviousness.
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`26.
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` A prior art reference may be considered if it discloses information designed
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`to solve any problem or need addressed by the patent or if the reference discloses
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`information that has obvious uses beyond its main purpose that a person having
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`ordinary skill in the art would reasonably examine to solve any problem or need
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`addressed by the patent. The combination of familiar elements according to known
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`methods is likely to be obvious when it does no more than yield predictable results.
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`27. When a work is available in one field of endeavor, design incentives and
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`other market forces can prompt variations of it, either in the same field or a
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`different one. If a person of ordinary skill can implement a predictable variation,
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`§103 likely bars its patentability. For the same reason, if a technique has been used
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`to improve one device, and a person of ordinary skill in the art would recognize
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`that it would improve similar devices in the same way, using the technique is
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`obvious unless its actual application is beyond his or her skill.
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`28. The obviousness analysis need not seek out precise teachings directed to the
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`specific subject matter of the challenged claim, for a court can take account of the
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`inferences and creative steps that a person of ordinary skill in the art would employ
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`at the time of the invention. Indeed, often, it will be necessary to look to
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`interrelated teachings of multiple patents; the effects of demands known to the
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`design community or present in the marketplace; and the background knowledge
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`possessed by a person having ordinary skill in the art, all in order to determine
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`whether there was an apparent reason to combine the known elements in the
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`fashion claimed by the patent at issue. Importantly, the question is not whether the
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`combination was obvious to the patentee but whether the combination was obvious
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`to a person with ordinary skill in the art. Under the correct analysis, any need or
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`problem known in the field of endeavor at the time of invention and addressed by
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`the patent can provide a reason for combining the elements in the manner claimed.
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`29. The obviousness analysis cannot be confined by a formalistic conception of
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`the words “teaching, suggestion, and motivation,” or by overemphasis on the
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`importance of published articles and the explicit content of issued patents.
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`30.
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` In determining whether the subject matter of a patent claim is obvious,
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`neither the particular motivation nor the avowed purpose of the patentee controls.
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`What matters is the objective reach of the claim. If the claim extends to what is
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`obvious, it is invalid. One of the ways in which a patent's subject matter can be
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`proved obvious is by noting that there existed at the time of invention a known
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`problem for which there was an obvious solution encompassed by the patent's
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`claims.
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`31.
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` A person of ordinary skill attempting to solve a problem will not be led only
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`to those elements of prior art designed to solve the same problem. Common sense
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`teaches that familiar items may have obvious uses beyond their primary purposes,
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`and in many cases a person of ordinary skill will be able to fit the teachings of
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`multiple patents together like pieces of a puzzle. A person of ordinary skill is also a
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`person of ordinary creativity, not an automaton.
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`32. When there is a design need or market pressure to solve a problem and there
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`are a finite number of identified, predictable solutions, a person of ordinary skill
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`has good reason to pursue the known options within his or her technical grasp. If
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`this leads to the anticipated success, it is likely the product not of innovation but of
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`ordinary skill and common sense. In that instance the fact that a combination was
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`obvious to try might show that it was obvious.
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`33. One should be aware of the potential for distortion caused by hindsight bias
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`and must be cautious of arguments reliant upon ex post reasoning.
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`IV. OVERVIEW OF THE ʼ552 PATENT
`34. The ʼ552 Patent is directed to a semiconductor device with purported
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`reduced lateral spacer erosion. ʼ552 Patent, Abstract. A color annotated version of
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`Figure 4(L) of the ʼ552 Patent, reproduced below, illustrates a cross-sectional
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`planar side view of the disclosed semiconductor device:
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`35. As illustrated in Figure 4(L), the semiconductor device includes insulating
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`spacers in yellow which are at an angle relative to the substrate surface of between
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`85 and 90 degrees. An etch stop layer with etch resistant properties is highlighted
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`in red. There is also disclosed an insulating layer in orange which insulates the
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`conductive layer 415. ʼ552 Patent, 10:31-65; 11:63 – 12:20. Shown in blue is a
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`transistor contact point which is deposited in what the patent calls a contact region
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`or contact opening. ʼ552 Patent, 13:43-45. As shown, the etch stop material is
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`etched away from the bottom of the contact opening and allows electrical contact
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`with the conductive region 445. ʼ552 Patent, 11:60-62.
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`V. HAVEMANN
`36.
`I have been asked by counsel for Petitioner to review the asserted claims of
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`the ʼ552 Patent in view of Havemann. I have performed that analysis and it is my
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`opinion that Havemann anticipates Claims 1-12 of the ʼ552 Patent.
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`A. Overview of Havemann
`37. Havemann describes a semiconductor device
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`incorporating “organic
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`dielectric materials to form self-aligned contacts (SACTs)” in deep, narrow gaps.
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`ʼ894 Patent, Abstract. Figure 2D of Havemann illustrates an embodiment of its
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`self-aligned contact:
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`38. Figure 2D is annotated below and shows conductors 26 (purple) with
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`insulating conductor caps 28 (orange) formed over a silicon substrate 20 (green).
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`A conformal dielectric layer 30 shown in yellow is formed as shown. An
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`insulating layer 32 shown in lime green is also deposited. As shown in red (42), a
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`conformal dielectric overlayer is taught. Havemann discloses that the preferred
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`conformal layer (42) in red is a nitride, whereas the preferred underlying dielectric
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`insulator (30) shown in yellow is an oxide: “If conformal layer 30 and overlayer 42
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`differ in materials (e.g., thermal oxide and nitride), relative selectivity between the
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`two materials may also be exploited to design a structure wherein conductor caps
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`28 are extremely thin.” ʼ894 Patent at 5:27-31. Havemann discloses that the gap
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`43 can be used for a “contact plug” to make electrical connection with the
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`substrate. ʼ894 Patent at 4:62-5:1. This optional contact plug is shown in blue.
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`39. Shown below is colored figure 4(L) from the ’552 Patent with the colored
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`Figure 2D of the ʼ894 Patent.
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`Claim 1
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`40.
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`It is my opinion that Havemann anticipates Claim 1 of the ʼ552 Patent.
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`[1.0] “A structure, comprising”
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`41. Havemann discloses “a structure for self-aligned contacts on semiconductor
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`devices.” (emphasis added). ʼ894 Patent, 2:10-11.
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`[1.1] “(a) a conductive layer disposed over a substrate;”
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`42. Havemann discloses a SACT embodiment with “[c]onformal dielectric 30
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`deposited on the sidewalls of conductors 26….” (emphasis added). ʼ894 Patent,
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`5:10-11. Figure 2D of Havemann illustrates the conductors 26, in purple, as a
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`conductive layer disposed over a substrate 20 shown in green:
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`Thus, it is my opinion that Havemann discloses the claim limitations recited in
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`[1.1].
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`[1.2] “(b) a first insulating layer on the conductive layer;”
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`43. Havemann discloses a structure that includes insulating conductor caps 28.
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`(emphasis added). ʼ894 Patent at 3:62-65. The insulating conductor caps 28 are on
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`the conductive layer 26 and are illustrated in Figure 2D below in orange:
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`As shown in the table at column 6 line 5 in the Havemann patent, the preferred
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`material for these insulating caps is CVD oxide, which is explicitly listed as an
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`alternative material. This aligns with the ’552 Patent’s disclosure that the
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`insulating layer is made up of a TEOS oxide, which is a type of CVD oxide.
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`Thus, it is my opinion that Havemann discloses the claim limitations recited in
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`[1.2].
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`[1.3] “(c) a contact region in said first insulating layer;”
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`44. Havemann discloses that “preferably a short anisotropic etch of the
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`conformal layer follows these steps if contact is to be made to the substrate in the
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`gap (which may then be followed by a deposition of conducting material in the gap
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`to form an electrical contact to the substrate).” ʼ894 Patent at 2:62-66. The contact
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`region identified in Figure 2D below is an example of a gap between the first
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`insulating layers 28.
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`In fact, Havemann discloses “contact plug 40, formed of a conducting material
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`(e.g. a composite comprised of a refractory metal underlayer with a tungsten
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`overlayer) may be deposited in cap window 39 and contact window 41 (which
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`includes the portion of insulated gap 29 underlying window 39) to form a contact
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`to the substrate at gap bottom 43.” ʼ894 Patent at 4:63-5:1. Thus, it is my opinion
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`that Havemann discloses the claim limitations recited in [1.3].
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`[1.4] “(d) at least one insulating spacer in the contact region adjacent to the
`first insulating layer; and”1
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`1 Claims 1, 4, and 5 recite an “insulating spacer” while claims 8-10 recite an
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`“insulative spacer.” In performing my analysis herein, I have used the following
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`construction for those terms: “electrically insulating material next to a conductive
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`portion and within the contact region/opening” which in my opinion, is consistent
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`with the understanding of this term to a person of skill in the art in view of the
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`specification of the ʼ552 Patent.
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`45.
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`In the table at column 6, line 16, Havemann discloses a conformal layer 30
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`made of a material, such as CVD oxide. (emphasis added). ʼ894 Patent at 6:16.
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`As explained in the ’552 Patent, oxide layers (e.g., TEOS oxide layers) are
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`insulators. ʼ552 Patent at 4:37-38. CVD oxide is a known disclosure of an oxide
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`layer because it is an oxide deposited via chemical vapor deposition.
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`46. The conformal layer 30, shown in yellow below in Figure 2D is electrically
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`insulating material next to a conductive portion and within the contact
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`region/opening:
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`As illustrated in Figure 2D, the conformal layer 30 is adjacent to the
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`insulating conductor caps 28 (i.e., the first insulating layer). ʼ894 Patent, Figure
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`2D. Notably, in the table in column 6, the insulating spacers 30 are disclosed as
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`the same material as insulating layer 28—CVD oxide. Likewise, in the ’552
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`Patent, the insulating spacers and the first insulating layer are both TEOS oxides,
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`which is a type of CVD oxide. ʼ552 Patent at 11:41-42. In fact, the only thing that
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`distinguishes the insulating layer and the insulating spacers in the ’552 Patent is
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`that the spacers are distinguished by “ghost lines.” Id. Thus, it is my opinion that
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`Havemann discloses the claim limitations recited in [1.4].
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`[1.5] “(e) an etch stop material over said first insulating layer and adjacent
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`to the insulating spacer, the etch stop material being a different material
`from the insulating spacer,”2
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`47. Havemann discloses that “[a]dditional material may subsequently be
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`deposited as a conformal dielectric overlayer 42, e.g., using thermal oxide or
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`silicon nitride (see FIG. 2C).” (emphasis added). ʼ894 Patent at 5:16-18. The ’552
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`Patent explains that silicon nitride is a known etch stop material. ʼ552 Patent 4:42-
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`44. This is also disclosed in Havemann, which says “[i]f conformal layer 30 and
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`2 Claims 1-5, 8-10 all recite an “etch stop material.” In applying these terms in my
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`analysis herein, I have used the following construction: “etch resistant material
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`applied to permit subsequent etching of the substrate without risk of exposing the
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`device structures and layers.” This understanding comes directly from the
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`specification (ʼ552 Patent at 4:13-18) and is consistent with the understanding of
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`this term to a person of skill in the art in light of the specification. Claim 1 recites
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`an “etch stop material over said first insulating layer and adjacent to the insulating
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`spacer.” In performing my analysis here, I have interpreted this term to mean
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`“etch stop material over at least a portion of an electrically insulating layer and
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`next to at least a portion of the insulating spacer.” This construction is consistent
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`with the understanding of a person of ordinary skill in view of the ʼ552 Patent’s
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`specification.
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`overlayer 42 differ in materials (e.g., thermal oxide and nitride), relative selectivity
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`between the two materials may also be exploited to design a structure wherein
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`conductor caps 28 are extremely thin.” ʼ894 Patent at 5:27-31. One of ordinary
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`skill in the art at the time knew that silicon nitride was a known etch stop material.
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`As shown in Figure 2D below, layer 42 is over the first insulating layer 28 and
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`adjacent to the insulating spacer 30. ʼ894 Patent at 5:15-22. Importantly, the table
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`in column 6 identifies “silicon nitride” as the preferred material for layer 42.
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`48. Havemann clarifies that the etch stop material and insulators should be
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`different materials: “If conformal layer 30 and overlayer 42 differ in materials
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`(e.g. thermal oxide and nitride), relatively selectively between the two materials
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`may also be exploited to design a structure wherein conductor caps 28 are
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`extremely thin.” (emphasis added). ʼ894 Patent at 5:27-31. One of skill in the art
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`at the time would have understood that the conformal dielectric 42 is an etch stop
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`material over the first insulating layer and adjacent to the insulating spacer.
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`[1.6] “wherein a side of the insulating spacer has an angle relative to the
`substrate surface that is either a right angle or an acute angle of more
`than 85°.”
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`49. Figure 2D of Havemann illustrates that the insulating spacers, in yellow, are
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`perpendicular to the substrate surface 20:
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`Specifically, Havemann discloses that “[c]ap window 39 supplies a pattern for
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`etching a contact window through organic-containing layer 32 by a suitable
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`anisotropic (substantially in one direction, usually vertical) etch.” ʼ894 Patent, col.
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`4, lines 37-40.
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`50. Havemann further discloses that “limited etch anisotropy” is the “ability to
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`etch in one direction only, e.g. vertically.” (emphasis added). ʼ894 Patent at col.
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`2, lines 4-5. Thus, it is my opinion that Havemann discloses the limitations recited
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`in [1.6].
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`51.
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`See claim chart A in Exhibit HYNIX-1008.
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`Claim 2
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`52.
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`It is my opinion that Havemann anticipates Claim 2 of the ʼ552 Patent.
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`[2.0] “The semiconductor apparatus of claim 1 wherein said etch stop
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`material comprises silicon nitride.”
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`53. Havemann discloses that “silicon nitride and silicon dioxide (of different
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`varieties) are used for the dielectric layers;….” (emphasis added). ʼ894 Patent at
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`1:56-60. As explained above, the table in column 6 clarifies that the preferred
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`material for the etch stop layer 42 is silicon nitride. Thus, Havemann discloses the
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`claim limitations recited in [2.0].
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`54.
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`See claim chart A in Exhibit HYNIX-1008.
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`Claim 3
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`55.
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`It is my opinion that Havemann anticipates Claim 3 of the ʼ552 Patent.
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`[3.0] “The semiconductor apparatus of claim 1 wherein said etch stop
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`material comprises silicon dioxide.”
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`56. Havemann discloses that “[s]ilicon nitride and silicon dioxide (of different
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`varieties) are used for the dielectric layers;….” (emphasis added). ʼ894 Patent at
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`1:56-60 Havemann makes clear that either silicon nitride or silicon dioxide are
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`useable as an etch stop material for drawing element 42, as shown in the table
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`below. ʼ894 Patent, Table at 6:30-31.
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`Thermal oxidation and CVD oxide are and were well-known methods for
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`providing silicon dioxide. It is my opinion that one of skill in the art at the time
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`would understand that by disclosing thermal oxide and CVD oxide above,
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`Havemann is disclosing silicon dioxide as an alternative for silicon nitride to be
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`used as the etch stop material. Moreover, claim 5 of Havemann discloses that the
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`conformal dielectric layer can be CVD silicon dioxide. Thus, it is my opinion that
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`Havemann discloses the claim limitations recited in [3.0].
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`57.
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`See claim chart A in Exhibit HYNIX-1008.
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`Claim 4
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`58.
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`It is my opinion that Havemann anticipates Claim 4 of the ʼ552 Patent.
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`[4.0] “The structure of claim 1, wherein the insulating spacer has a surface
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`portion in the contact region without overlying etch stop material.”
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`59. As illustrated below, Figure 2D of Havemann discloses that after etching the
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`top portion of the insulating spacer is not covered by etch stop. ʼ894 Patent at 5:6-
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`9, Figure 2D. The surface o