Trials@uspto.gov
`571-272-7822
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`Paper 8
`Entered: May 11, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC.,
`SK HYNIX MEMORY SOLUTIONS INC., and
`HYNIX SEMICONDUCTOR MANUFACTURING AMERICA INC.,
`Petitioner,
`
`v.
`
`DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-00192
`Patent 6,784,552 B2
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`
`
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`571-272-7822
`
`
`
`
`
`Paper 8
`Entered: May 11, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC.,
`SK HYNIX MEMORY SOLUTIONS INC., and
`HYNIX SEMICONDUCTOR MANUFACTURING AMERICA INC.,
`Petitioner,
`
`v.
`
`DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-00192
`Patent 6,784,552 B2
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
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`I. INTRODUCTION
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`SK Hynix Inc., SK Hynix America Inc., SK Hynix Memory Solutions
`Inc., and Hynix Semiconductor Manufacturing America Inc. (collectively,
`“Petitioner”) filed a Petition (Paper 1, “Pet.”) requesting an inter partes
`review of claims 1–12 (the “challenged claims”) of U.S. Patent No.
`6,784,552 B2 (Ex. 1001, “the ’552 patent”). DSS Technology Management,
`Inc. (“Patent Owner”) filed a Waiver of Preliminary Response. Paper 7. We
`have jurisdiction under 35 U.S.C. § 314.
`The standard for instituting an inter partes review is set forth in
`35 U.S.C. § 314(a), which provides that an inter partes review may not be
`instituted “unless the Director determines . . . there is a reasonable likelihood
`that the petitioner would prevail with respect to at least 1 of the claims
`challenged in the petition.” For the reasons described below, we conclude
`Petitioner has established a reasonable likelihood of prevailing in showing
`the unpatentability of claims 1–10. Accordingly, we institute an inter partes
`review of claims 1–10 of the ’552 patent.
`
`A. Related Proceedings
`According to the parties, the ’552 patent is the subject of the
`following patent infringement cases: DSS Tech. Mgmt., Inc. v. SK Hynix,
`Inc., et al., Case No. 6:15-cv-691 (E.D. Tex.); DSS Tech. Mgmt., Inc. v.
`Samsung Elec. Co., Ltd. et al., Case No. 6:15-cv-690 (E.D. Tex.); DSS Tech.
`Mgmt., Inc. v. Qualcomm, Inc., Case No. 6:15-cv-692 (E.D. Tex.); and DSS
`Tech. Mgmt., Inc. v. Intel, Corp. et al., Case No. 6:15-cv-130 (E.D. Tex.).
`Pet. 2; Paper 6, 2–3.
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`B. The ’552 Patent
`The ’552 patent describes a process of semiconductor device
`fabrication and a structure of a semiconductor device having “substantially
`rectangular” lateral insulating spacers adjacent to gate electrodes. Ex. 1001,
`Abstract. The ’552 patent defines the term “substantially rectangular” to
`mean that “a side of the spacer has an angle relative to the substrate surface
`of more than 85°.” Id. at col. 8, ll. 40–42. Figure 4(D) of the ’552 patent is
`reproduced below.
`
`
`Figure 4(D) illustrates a cross-sectional view of a series of gates 415 (also
`called conducting layers or polysilicon layers) completely encapsulated in
`insulating material 420, e.g., TEOS (tetraethyl orthosilicate glass), where
`spacers 435 of the insulating material adjacent to the gates have substantially
`rectangular profiles. Id. at col. 9, ll. 9–13; col. 11, ll. 40–46. As shown in
`Figure 4(D), gates 415 are insulated from sources or drains 405 by insulating
`dielectric layers 410. See id. at col. 10, ll. 49–50. The ’552 patent describes
`a process of making high quality contacts to the sources or drains, such as
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`“self-aligned” contacts, by etching structures over substrate 400 and sources
`or drains 405. Id. at col. 7, ll. 19–22; col. 8, ll. 4–6.
`Figure 4(I) of the ’552 patent is reproduced below.
`
`
`Figure 4(I) illustrates additional structures deposited and etched over the
`structure described in Figure 4(D), such as second dielectric layer 440
`(called etch stop layer), blanket layer 450, and photoresist mask layer 455.
`Id. at col. 9, ll. 33–39; col. 11, ll. 63–65; col. 12, ll. 34–42. According to the
`’552 patent, etch stop layer 440, e.g., silicon nitride layer 440, depicted in
`Figure 4(I) is distinct or different from the underlying TEOS insulating
`layer. Id. at col. 12, ll. 10–11. The etch stop layer protects the underlying
`TEOS layer when blanket layer 450 made of BPTEOS1 is etched away to
`create contact openings 460 and 465 above source or drain 445. See id. at
`col. 12, ll. 36–42; col. 4, ll. 41–59.
`
`
`1 BPTEOS is an acronym for borophosphosilicate tetraethyl orthosilicate
`glass. See Ex. 1001, col. 11, ll. 6–7.
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`A second etch is then performed to remove etch stop layer 440
`covering source or drain 445 in contact openings 460 and 465. Id. at col. 12,
`ll. 48–52; col. 7, ll. 43–45. The ’552 patent describes that the second etch is
`“almost completely anisotropic,” which means that the etchant etches in the
`vertical direction, or perpendicular relative to the substrate surface. Id. at
`col. 7, ll. 45–48; col. 12, ll. 55–58. Hence, the etch removes the etch stop
`material covering the area of the contact openings or contact regions 460 and
`465, but does not significantly etch the etch stop material adjacent to the
`spacer portions 435. Id. at col. 7, ll. 53–55; col. 12, ll. 58–61. Figures 4(J)
`and 4(K) of the ’552 patent are reproduced below.
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`Figures 4(J) and 4(K) illustrate the structure of the semiconductor device of
`the ’552 patent after the second etch for removing the etch stop layer from
`the contact regions 460 and 465 is completed. As shown in Figures 4(J) and
`4(K), due to the anisotropic or vertical nature of the second etch, only a
`small portion, i.e., portion 475, of the TEOS spacer portion 435 is removed
`during the etch. Id. at col. 13, ll. 6–9. Of primary significance, according to
`the ’552 patent, the spacer portion 435 of the TEOS insulating layer 420
`retains its substantially rectangular profile, in contrast to the conventional
`prior art method which transforms a substantially rectangular spacer into a
`sloped spacer. Id. at col. 13, ll. 9–10; col. 7, ll. 48–51; col. 5, ll. 4–14.
`C. Illustrative Claim
`Of the challenged claims, claims 1 and 8 are independent. Claims 2–7
`depend directly or indirectly from claim 1, and claims 9–12 depend directly
`or indirectly from claim 8. Claim 1 is illustrative of the challenged claims
`and is reproduced below with the key limitation (the “acute angle
`limitation”) emphasized in italics:
`1. A structure, comprising:
`(a) a conductive layer disposed over a substrate;
`(b) a first insulating layer on the conductive layer:
`(c) a contact region in said first insulating layer;
`(d) at least one insulating spacer in the contact region adjacent
`to the first insulating layer; and
`(e) an etch stop material over said first insulating layer and
`adjacent to the insulating spacer, the etch stop material being a
`different material from the insulating spacer,
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`wherein a side of the insulating spacer has an angle relative to
`the substrate surface that is either a right angle or an acute
`angle of more than 85°.
`
`D. Asserted Grounds of Unpatentability
`Petitioner asserts the following grounds of unpatentability (Pet. 4–5,
`13–58):
`
`Claim(s) Challenged Statutory Basis
`
`Ground
`
`1–12
`
`§ 102(e)
`
`1, 2, 4–10
`
`§ 102(b)
`
`3
`
`1, 4, 5
`
`§ 103(a)
`
`§ 102(a)
`
`Anticipated by Havemann2 (Pet.
`14–34, Ground 1)
`
`Anticipated by Heath3 (Pet. 34–49,
`Ground 2)
`
`Obvious over Heath and Haveman
`(Pet. 49–53, Ground 3)
`
`Anticipated by APA4 (Pet. 53–58,
`Ground 4)
`
`
`II. CLAIM CONSTRUCTION
`The ’552 patent has expired. Pet. 5. Thus, we construe the claims in
`accordance with the standard set forth in Phillips v. AWH Corp., 415 F.3d
`1303 (Fed. Cir. 2005) (en banc). See In re Rambus, 694 F.3d 42, 46 (Fed.
`
`
`2 Ex. 1004, U.S. Patent No. 5,482,894 (issued Jan. 9, 1996; filed Aug. 23,
`1994) (“Havemann”).
`3 Ex. 1005, U.S. Patent No. 4,686,000 (Aug. 11, 1987) (“Heath”).
`4 Petitioner relies on Figures 1(A), 1(B), 1(C), 2(A), 2(B), and 3 and the
`description at column 1, line 14 to column 6, line 65 of the ʼ552 patent as
`admitted prior art (“APA”).
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`Cir. 2012) (“While claims are generally given their broadest possible scope
`during prosecution, the Board’s review of the claims of an expired patent is
`similar to that of a district court’s review.”). “In determining the meaning of
`the disputed claim limitation, we look principally to the intrinsic evidence of
`record, examining the claim language itself, the written description, and the
`prosecution history, if in evidence.” DePuy Spine, Inc. v. Medtronic
`Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips,
`415 F.3d at 1312–17). Only those terms which are in controversy need to be
`construed, and only to the extent necessary to resolve the controversy. Vivid
`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`Petitioner proposes the following claim constructions:
`
`Term
`
`Proposed Construction
`
`“insulating spacer” /
`“insulative spacer”
`
`“etch stop material”
`
`“electrically insulating material next to a
`conductive portion and within the contact
`region/opening.” Pet. 6–8.
`
`“etch resistant material applied to permit
`subsequent etching of the substrate without
`risk of exposing the device structures and
`layers.” Id. at 8–9.
`
`“etch stop material over said
`first insulating layer and
`adjacent to the insulating
`spacer”
`
`“etch stop material (as construed) over at
`least a portion of an electrically insulating
`layer and next to at least a portion of the
`insulating spacer (as defined).” Id. at 9–10.
`
`For purposes of this Decision, we do not find it necessary to make any
`formal claim constructions because our decision does not rest on express
`construction of any of these terms.
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`III. ANALYSIS OF PETITIONER’S PRIOR ART CHALLENGES
`
`A. Anticipation By Havemann
`Petitioner contends claims 1–12 are unpatentable under 35 U.S.C.
`§ 102(e) as anticipated by Havemann. Pet. 14–34. We are not persuaded
`that Petitioner has established a reasonable likelihood of prevailing on the
`asserted ground for the reasons explained below.
`
`1. Principles of Law
`A claim is unpatentable under 35 U.S.C. § 102 only if a single prior
`art reference expressly or inherently describes each and every limitation set
`forth in the claim. See Perricone v. Medicis Pharm. Corp., 432 F.3d 1368,
`1375 (Fed. Cir. 2005); Verdegaal Bros., Inc. v. Union Oil Co., 814 F.2d 628,
`631 (Fed. Cir. 1987). Further, a reference cannot anticipate “unless [it]
`discloses within the four corners of the document not only all of the
`limitations claimed[,] but also all of the limitations arranged or combined in
`the same way as recited in the claim.” Net MoneyIN, Inc. v. VeriSign, Inc.,
`545 F.3d 1359, 1371 (Fed. Cir. 2008). Although the elements must be
`arranged in the same way as in the claim, “the reference need not satisfy an
`ipsissimis verbis test,” i.e., identity of terminology is not required. In re
`Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond, 910 F.2d 831,
`832 (Fed. Cir. 1990). We analyze this asserted ground based on anticipation
`with the principles identified above in mind.
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`2. Overview of Havemann
`Havemann describes a semiconductor device and a process of making
`a semiconductor device which incorporates organic dielectric materials to
`form self-aligned contacts reliably. Ex. 1004, Abstract. Havemann
`discloses at least two embodiments—the first embodiment is illustrated in
`Figures 1D to 1I (id. at col. 3, ll. 38–40; col. 3, l. 53–col. 5, l. 1), whereas the
`second embodiment is depicted in Figures 2A to 2D (id. at col. 3, ll. 41–43;
`col. 5, ll. 2–31).
`
`Claims 1 and 8
`
`3. Analysis
`
`Petitioner contends that the second embodiment of Havemann,
`including Figure 2D, discloses every limitation of claim 1. Pet. 15–21.
`Figure 2D of Havemann, as annotated by Petitioner in colors, is reproduced
`below.
`
`
`Id. at 20. Annotated Figure 2D above depicts a cross-sectional view of the
`structure constructed in the second embodiment of Havemann. Ex. 1004,
`col. 3, ll. 41–43; col. 5, ll. 2–3. Referencing Figure 2D, Petitioner asserts
`that layer 30 and layer 42 depicted in Figure 2D disclose an “insulating
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`spacer” and an “etch stop material” recited in claim 1, respectively. Id. at
`18–20 (citing Ex. 1004, col. 2, ll. 14–17; col. 5, ll. 15–22, 27–31).
`Petitioner further contends that Havemann discloses the acute angle
`limitation, i.e., “a side of the insulating spacer has an angle relative to the
`substrate surface that is either a right angle or an acute angle of more than
`85°,” because Havemann describes that “[c]ap window 39 supplies a pattern
`for etching a contact window through organic-containing layer 32 by a
`suitable anisotropic (substantially in one direction, usually vertical) etch.”
`Id. at 20–21 (quoting Ex. 1004, col. 4, ll. 37–40). However, the passage of
`Havemann cited by Petitioner describes the first embodiment of Havemann,
`not the second embodiment depicted in Figure 2D relied upon by Petitioner.
`See Ex. 1004, col. 4, ll. 36–53 (describing the process and the semiconductor
`structure of the first embodiment illustrated in Figures 1G and 1H).
`Petitioner does not explain how the disclosure of an anisotropic vertical
`etching in the first embodiment is applicable to the second embodiment.
`Petitioner also asserts that Havemann discloses that “limited etch
`anisotropy” is the “ability to etch in one direction only, e.g.[,] vertically.”
`Pet. 21 (quoting Ex. 1004, col. 2, ll. 4–5). The passage cited by Petitioner,
`however, describes the shortcomings of the prior art method identified by
`Havemann: “At some geometry, [the prior art method] becomes ineffective
`for reliably forming such self-aligned contacts; the limited selectivity
`between dielectric layers and limited etch anisotropy (ability to etch in one
`direction only, e.g.[,] vertically) make such a process difficult for high aspect
`ratio gaps.” Ex. 1004, col. 2, ll. 1–6 (emphasis added). Again, Petitioner
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`does not explain how this disclosure shows that the second embodiment of
`Havemann discloses the acute angle limitation.
`To establish anticipation, each and every element in a claim, arranged
`as recited in the claim, must be found in a single prior art reference. Net
`MoneyIN, 545 F.3d at 1369. To anticipate, a prior art reference must
`disclose more than “multiple, distinct teachings that the artisan might
`somehow combine to achieve the claimed invention.” Id. at 1371.
`Petitioner’s anticipation argument with respect to claim 1 is deficient
`because the Petition does not explain how “picking, choosing, and
`combining” the disclosures of the first and second embodiments of
`Havemann is justified to show anticipation. See In re Arkley, 455 F.2d 586,
`587 (CCPA 1972) (“[T]he [prior art] reference must clearly and
`unequivocally disclose the claimed [invention] or direct those skilled in the
`art to the [invention] without any need for picking, choosing, and combining
`various disclosures not directly related to each other by the teachings of the
`cited reference.”). Petitioner’s anticipation argument with respect to claim 8
`is similarly deficient because Petitioner relies upon the same deficient
`argument and evidence as claim 1 to satisfy the acute angle limitation recited
`in claim 8. See Pet. 32. Accordingly, on this record, the information
`presented in the Petition does not demonstrate a reasonable likelihood of
`Petitioner prevailing in its challenge to claims 1 and 8 under 35 U.S.C.
`§ 102(e) as anticipated by Havemann.
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`Dependent Claims 2–7 and 9–12
`Claims 2–7 depend from claim 1, and claims 9–12 depend from claim
`8. Petitioner’s arguments and evidence presented with respect to these
`dependent claims do not remedy the deficiencies in Petitioner’s analysis of
`the challenged independent claims. Therefore, Petitioner fails to
`demonstrate a reasonable likelihood of Petitioner prevailing in its challenge
`to claims 2–7 and 9–12 under 35 U.S.C. § 102(e) as anticipated by
`Havemann.
`
`B. Anticipation By Heath
`Petitioner contends claims 1, 2, and 4–10 are unpatentable under
`35 U.S.C. § 102(b) as anticipated by Heath. Pet. 34–49. Petitioner provides
`detailed explanations and specific citations to Heath indicating where in the
`reference the claimed features are disclosed. Id. In addition, Petitioner
`relies upon the Declaration of Dr. Vivek Subramanian (“Subramanian
`Decl.,” Ex. 1003) to support its position. Id.
`
`1. Overview of Heath
`Heath describes a process for forming a self-aligned contact window
`in a semiconductor device, such as an integrated circuit. Ex. 1005, Abstract.
`Heath describes a two-step etching process which comprises the steps of first
`etching a dielectric layer down to a silicon nitride etch stop layer, and then
`etching the etch stop, leaving a “stick” of the etch stop material on the
`vertical sidewall of the layer to be protected. Id. Figure 8B of Heath is
`reproduced below.
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`Figure 8B depicts a cross-sectional view of a semiconductor structure after
`the first etching step, including gate electrode 16 insulated from contact
`window 32 and source or drain 20 by silicon nitride layer 10. See Ex. 1005,
`col. 9, ll. 50–67. In the second etching step, etch stop layer 10 is removed to
`open contact window 32 to source or drain 20. Heath describes that, because
`the nitride removal is anisotropic, vertical “stick” 10a of nitride layer 10 will
`remain on the side of gate electrode 16 so that no electrical short occurs
`between the gate electrode and the contact window or the source or drain
`region. Id. at col. 10, ll. 1–11.
`
`Claim 1
`
`2. Analysis
`
`Petitioner contends that the embodiment depicted in Figure 8C of
`Heath discloses every limitation of claim 1. Figure 8C of Heath, as
`annotated by Petitioner in colors, is reproduced below.
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`Pet. 40. Annotated Figure 8C above depicts a cross-sectional view of a
`semiconductor structure at the same stage of processing as Figure 8B
`combined with the addition of a sidewall spacer 16a. Ex. 1005, col. 10,
`ll. 14–19. Referencing Figure 8C, Petitioner provides detailed explanations
`and specific citations to Heath indicating where in the reference each
`limitation of claim 1 is disclosed. Pet. 35–40. For example, Petitioner
`asserts that gate electrode 16 and oxide layer 24b depicted in Figure 8C
`discloses “a conductive layer” and “a first insulating layer” recited in claim
`1, respectively. Id. at 36 (citing Ex. 1005, col. 9, ll. 50–55; Fig. 8C).
`Petitioner also contends that sidewall spacer 16a depicted in Figure 8C
`discloses an “insulating spacer” recited in claim 1. Id. at 38 (citing Ex.
`1005, col. 10, ll. 17–25; Fig. 8C). Petitioner further asserts that nitride layer
`10 depicted in Figure 8C discloses an “etch stop material over said first
`insulating layer and adjacent to the insulating spacer” recited in claim 1. Id.
`at 38–39 (citing Ex. 1005, col. 9, ll. 66–67; Fig. 8C). Petitioner argues that
`Heath describes layer 10 as an etch stop layer. Id. at 38 (citing Ex. 1005,
`col. 8, ll. 18–21). Petitioner further contends that Heath discloses the acute
`angle limitation recited in claim 1. According to Petitioner, Heath describes
`that “because the nitride removal is anisotropic, the ‘stick’ 10a will remain
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`on the side, so no short to electrode 16 can occur.” Id. at 39–40 (citing Ex.
`1005, col. 10, ll. 7–11; Fig. 8C); see also id. at 34 (citing Ex. 1005, col. 10,
`ll. 2–5 (“[T]he part of layer 10 between dashed lines 56 is removed, leaving
`the vertical ‘stick’ 10a of layer 10. Also, the etch continues downward
`through the then-exposed parts of oxide 24a and 24b.”); Fig. 8C). As shown
`in Figure 8C, because the vertical ‘stick’ 10a remains on the sidewall of the
`insulating spacer 16a after the anisotropic etching of the etch stop layer 10,
`the insulating spacer stands at a right angle or has a substantially rectangular
`profile relative to the substrate surface. Therefore, we are persuaded that
`Heath discloses the acute angle limitation of claim 1. On this record, for the
`purposes of this Decision, we are satisfied that Petitioner has cited sufficient
`disclosure from Heath to show Heath discloses all of the limitations of claim
`1.
`
`Based on the foregoing discussion, we are persuaded Petitioner has
`provided sufficient evidence that establishes a reasonable likelihood of
`prevailing in its challenge to claim 1 under 35 U.S.C. § 102(b) as anticipated
`by Heath.
`
`Claim 8
`Independent claim 8 is similar to claim 1 but includes additional
`limitations, such as “(a) a first electrically conductive material formed in
`and/or on a surface of a substrate” and “(e) a blanket layer over the etch stop
`material.” See Ex. 1001, col. 14, ll. 19–67. Both claims recite essentially
`the same acute angle limitation. For similar limitations of claims 1 and 8,
`Petitioner relies on the same or similar structures disclosed in Heath for both
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`claims. For example, for both “insulating spacer” recited in claim 1 and
`“electrically insulative spacer” recited in claim 8, Petitioner relies on
`sidewall spacer 16a depicted in Figure 8C. Pet. 38 (claim 1), 45 (claim 8).
`Similarly, for the acute angle limitations in claims 1 and 8, Petitioner relies
`on the same disclosure in Heath regarding an anisotropic etching that leaves
`vertical “stick” 10a on the insulator sidewalls. Id. at 39–40 (claim 1), 47–48
`(claim 8).
`For additional limitations recited in claim 8, Petitioner provides
`detailed explanations and specific citations to Heath indicating where in the
`reference each of the additional limitations of claim 8 is disclosed. Id. at
`44–46. For example, Petitioner asserts that the source or drain region 20
`depicted in Figure 8C of Heath discloses limitation (a), i.e., “a first
`electrically conductive material formed in and/or on a surface of a
`substrate,” recited in claim 8. Id. at 44 (citing Ex. 1005, col. 10, ll. 19–20;
`Fig. 8C). For limitation (e) of claim 8 reciting “a blanket layer over the etch
`stop material,” Petitioner contends that “interlevel dielectric layer 34
`overlying the etch stop layer 10” depicted in Figure 8C of Heath discloses
`the limitation. Id. at 46–47 (citing Ex. 1005, col. 9, ll. 63–65; col. 10, ll. 50–
`51; Fig. 8C). On this record, for the purposes of this Decision, we are
`satisfied that Petitioner has cited sufficient disclosure from Heath to show
`Heath discloses all of the limitations of claim 8.
`Based on the foregoing discussion, we are persuaded Petitioner has
`provided sufficient evidence that establishes a reasonable likelihood of
`prevailing in its challenge to claim 8 under 35 U.S.C. § 102(b) as anticipated
`by Heath.
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`Dependent Claims 2, 4–7, 9, and 10
`For claims 2, 4–7, 9, and 10, which depend from claims 1 or 8,
`Petitioner provides detailed explanations and specific citations to Heath
`indicating where in the reference the additionally recited limitations of the
`dependent claims are disclosed. Pet. 40–43, 48–49. For some of these
`dependent claims, the additionally recited limitations identify well-known
`materials or structures that are used for conventional purposes. Petitioner
`asserts that Heath discloses these conventional materials or structures. For
`example, with respect to claim 2, which depends from claim 1 and further
`recites “said etch stop material comprises silicon nitride,” the ’552 patent
`describes silicon nitride layer 240 of “prior art” Figure 2(A) as an etch stop
`layer. Ex. 1001, col. 4, ll. 41–43, 55–56. Petitioner asserts that Heath also
`discloses “[a] silicon nitride layer acting as an etch stop.” Pet. 40 (citing
`Ex. 1005, Abstract, col. 8, ll. 18–21). Regarding claim 6, which depends
`from claim 1 and recites “further comprising a second insulating layer on the
`etch stop layer and over the conductive layer,” the additionally recited
`limitation appears to encompass a structure similar to the structure identified
`in limitation (e) of claim 8 discussed above. In fact, Petitioner relies on
`essentially the same disclosure in Heath, i.e., interlevel dielectric layer 34
`overlying the etch stop layer 10 and gate electrode 16, for claim 6 and
`limitation (e) of claim 8. See id. at 42. Hence, on this record, we are
`persuaded that Heath discloses the limitations recited in claims 2 and 6.
`Claim 4 depends from claim 1 and further recites “the insulating
`spacer has a surface portion in the contact region without overlying etch stop
`material.” Claim 5 depends from claim 4 and additionally recites “the
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`insulating spacer surface portion without overlying etch stop material
`comprises an insulating spacer surface portion most distant from said
`substrate.” Claims 9 and 10, which depend from claim 8, recite additional
`limitations similar to claims 4 and 5, respectively, with claims 9 and 10
`reciting “electrically insulative spacer” instead of “insulating spacer” recited
`in claim 4 and 5. Petitioner points to the structures depicted in Figure 8C of
`Heath and asserts that Heath discloses these additionally recited limitations,
`providing description of the relevant structures and explanations in support
`of its argument. Id. at 40–41 (citing Ex. 1005, col. 10, ll. 2–5; Fig. 8C), 48–
`49. Upon reviewing Figure 8C and the structures or geometries evidently
`shown in the figure, we are persuaded that Heath discloses the limitations
`recited in claims 4, 5, 9, and 10.
`Claim 7 depends from claim 6 and additionally recites “further
`comprising a second conductive material in the contact region.” Petitioner
`contends that Heath discloses the additionally recited limitation of claim 7
`because Heath describes that “metallization can be added, and contact can be
`made to the source/drain region without shorting to the top or edge of a
`polysilicon element or the substrate under the edge of a field oxide.” Id. at
`42 (citing Ex. 1005, col. 6, ll. 11–15). We are persuaded by Petitioner’s
`argument because “metallization . . . added to the source/drain region
`without shorting . . . a polysilicon element” would constitute a second
`conductive material distinct from the polysilicon gate electrode 16 (see
`Ex. 1005, col. 8, ll. 8–11 (identifying polysilicon gate electrode 16 in Figure
`4 as the gate electrode)), i.e., the (first) conductive layer recited in claim 1.
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`On this record, for the purposes of this Decision, we are satisfied that
`Petitioner has cited sufficient disclosure from Heath to show Heath discloses
`all of the limitations of claims 2, 4–7, 9, and 10. Based on the foregoing
`discussion, we are persuaded Petitioner has provided sufficient evidence that
`establishes a reasonable likelihood of prevailing in its challenge to claims 2,
`4–7, 9, and 10 under 35 U.S.C. § 102(b) as anticipated by Heath.
`
`C. Obviousness Based on the Combination of Heath and Havemann
`Claim 3 depends from claim 1 and further recites “said etch stop
`material comprises silicon dioxide.” Petitioner contends claim 3 is
`unpatentable under 35 U.S.C. § 103(a) over the combination of Heath and
`Havemann. Pet. 49. Petitioner acknowledges Heath does not disclose
`explicitly that the etch stop material comprises silicon dioxide. Id. To
`satisfy this limitation, Petitioner contends Havemann teaches that CVD
`silicon dioxide can be used for layer 42, which corresponds to the etch stop
`recited in claims 1 and 3. Id. at 49–50 (citing Ex. 1004, col. 6, ll. 5–34).
`Relying upon the testimony of Dr. Subramanian, Petitioner also
`contends a person of ordinary skill in the art would have been motivated to
`combine Heath and Havemann because such simple substitution of known
`materials would have produced predictable results. Id. at 51 (citing Ex. 1003
`¶ 147). According to Petitioner and Dr. Subramanian, a person of ordinary
`skill in the art would have readily understood that the teachings of the self-
`aligned contacts in Havemann would have applied to the teachings of the
`self-aligned contacts in Heath, particularly with respect to choices of
`materials for the described etch stop layers. Id. (citing Ex. 1003 ¶ 148).
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`We credit the testimony of Dr. Subramanian and are persuaded that
`Petitioner has provided sufficient evidence to demonstrate a reasonable
`likelihood it will prevail in its challenge to claim 3 under 35 U.S.C. § 103(a)
`as obvious over the combination of Heath and Havemann.
`
`D. Anticipation Based on APA
`Petitioner contends claims 1, 4, and 5 are unpatentable under
`35 U.S.C. § 102 as anticipated by the admitted prior art of the ’552 patent,
`which includes Figures 1(A), 1(B), 1(C), 2(A), 2(B), and 3 and the
`description at column 1, line 14 to column 6, line 65 of the ʼ552 patent. Pet.
`5, 53–58.
`Petitioner contends that the APA discloses the acute angle limitation
`of claim 1, i.e., “a side of the insulating spacer has an angle relative to the
`substrate surface that is either a right angle or an acute angle of more than
`85°,” because “the dielectric spacer 150 has a right angle relative to the
`substrate surface, as illustrated in Figure 1B.” Id. at 56–57 (emphasis
`added). However, other than pointing to Figure 1(B) of the ’552 patent,
`Petitioner provides no further explanation or supporting evidence to show
`why the dielectric spacer 150 depicted in Figure 1(B) has a right angle
`relative to the substrate surface.
`Contrary to Petitioner’s contention, the ʼ552 patent describes in detail
`that the prior art method of forming contact regions transforms a
`substantially rectangular spacer into a sloped spacer due to the properties of
`the highly selective etch used in the conventional method to make a contact
`opening in the source or drain region. See Ex. 1001, col. 4, l. 26–col. 6,
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`l. 12; Figs. 2(A), 2(B), 3. Petitioner provides no explanation or supporting
`evidence why the illustration in Figure 1(B) departs from this description
`and, instead, discloses a spacer at a right angle relative to the substrate
`surface. Hence, we are not persuaded that Petitioner has cited sufficient
`disclosure from the admitted prior art to show it discloses all of the
`limitations of claim 1, including the acute angle limitation.
`Accordingly, on this record, the information presented in the Petition
`does not demonstrate a reasonable likelihood of Petitioner prevailing in its
`challenge to claim 1 under 35 U.S.C. § 102 as anticipated by the admitted
`prior art.
`Petitioner’s arguments and evidence presented with respect to
`dependent claims 4 and 5 do not remedy the deficiencies in Petitioner’s
`analysis of base claim 1. Therefore, Petitioner fails to demonstrate a
`reasonable likelihood of Petitioner prevailing in its challenge to claims 4 and
`5 under 35 U.S.C. § 102 as anticipated by the APA.
`
`IV. CONCLUSION
`Based on the arguments and evidence presented in the Petition, we
`conclude Petitioner has demonstrated a reasonable likelihood that it will
`prevail in showing unpatentability of claims 1–10 of the ’552 patent.
`Any discussion of facts in this Decision are made only for the
`purposes of institution and are not dispositive of any issue related to any
`ground on which we institute review. The Board has not made a final
`determination as to the patentability of any of the challenged claims. The
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`Board’s final determination will be based on the record as fully developed
`during trial.
`
`V. ORDER
`In consideration of the foregoing, it is hereby:
`ORDERED that pursuant to 35 U.S.C. § 314, an inter partes revie
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