Hybrid Process for Forming Metal Gates of MOS Devices
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`CROSS-REFERENCE TO RELATED APPLICATION
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`[0001]
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`This application relates to the following commonly assigned U.S. Patent Application:
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`Application Serial No. 11/552,704, filed October 25, 2006, entitled "Semiconductor Devices
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`with Dual-Metal Gate Structures and Fabrication Methods Thereof," which patent application is
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`incorporated herein by reference.
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`TECHNICAL FIELD
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`[0002]
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`This invention relates generally to semiconductor devices, and more particularly to
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`structures of metal-oxide-semiconductor (MOS) devices and manufacturing methods for forming
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`the same.
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`BACKGROUND
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`[0003] Metal-oxide-semiconductor (MOS) devices are basic building elements in integrated
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`circuits. A conventional MOS device typically has a gate electrode comprising polysilicon doped
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`with p-type or n-type impurities, using doping operations such as ion implantation or thermal
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`diffusion. It is preferred to adjust the work function of the gate electrode to the band-edge of the
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`silicon; that is: for an NMOS device, adjusting the work function close to the conduction band,
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`and for a PMOS device, adjusting the work function close to the valence band. Adjusting the
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`work function of the polysilicon gate electrode can be achieved by selecting appropriate
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`impurities.
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`[0004] MOS devices with polysilicon gate electrodes exhibit carrier depletion effect, which
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`is also referred to as a poly depletion effect. The poly depletion effect occurs when applied
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`electrical fields sweep away carriers from regions close to gate dielectrics, forming depletion
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`layers. In ann-doped polysilicon layer, the depletion layer includes ionized non-mobile donor
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`sites, whereas in a p-doped polysilicon layer, the depletion layer includes ionized non-mobile
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`acceptor sites. The depletion effect results in an increase in the effective gate dielectric thickness,
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`making it more difficult for an inversion layer to be created at the surface of the semiconductor.
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`[0005]
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`The use of thin gate dielectrics tends to make the carrier depletion effect worse. With
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`thin gate dielectrics, the depletion layer in the polysilicon gate becomes more significant in
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`thickness when compared to the thickness of the thin gate dielectrics, and thus device
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`performance degradation worsens. As a result, the carrier depletion effect in the gate electrodes
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`limits device scalability by imposing a lower bound on how much the effective gate dielectric
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`thickness can be reduced.
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`[0006]
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`The poly depletion effect was previously solved by forming metal gate electrodes or
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`metal silicide gate electrodes, wherein the metallic gates used in NMOS devices and PMOS
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`devices also preferably have band-edge work functions. Currently, materials suitable for forming
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`gate electrodes ofNMOS devices, such as TaC, have been found. However, for PMOS devices,
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`even though metallic materials having band-edge work functions have been found, these
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`materials have poor thermal stability. When exposed to the high temperatures in the
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`front-end-of-line processes, the work functions of these metallic materials shift, for example,
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`toward the mid-gap level. The performance of the resulting PMOS devices is thus adversely
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`affected.
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`[0007]
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`Existing processes for forming dual-metal complementary MOS (CMOS) devices
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`include two main categories, gate-first approach and gate-last approach. Both approaches have
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`advantageous and disadvantageous features. In a typical gate-first approach, two metal layers
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`having different work functions are separately formed in PMOS and NMOS regions. The metal
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`layers are then patterned to form gate electrodes. Other components ofMOS devices, such as
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`spacers, lightly doped source/drain (LDD) regions, source/drain regions, silicides, and contact
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`etch stop layers are then formed. This process is relatively simple, and the resulting contact etch
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`stop layers are continuous, so that they can effectively apply stresses. However, since the metal
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`gates are formed before the formation and the activation ofLDD regions and source/drain
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`regions, they suffer from high thermal budgets, and the work functions of PMOS devices may
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`shift. In addition, if composite metal layers are used, the oxygen in the composite metal layer
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`may be released under the thermal budgets, and cause interfacial layer re-growth. Further,
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`patterning metal layers by etching is relatively difficult, particularly for metals used for the
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`PMOS devices.
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`[0008]
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`Gate-last approach, on the other hand, typically includes the steps of forming dummy
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`gates for both PMOS and NMOS devices. LDD regions, gate spacers, source/drain regions, and
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`contact etch stop layers are then formed. The dummy gates of PMOS and NMOS devices are
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`then removed, and metals with different work functions are then filled into the openings for
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`PMOS and NMOS devices. In the gate-last approach, metal gates of PMOS devices and NMOS
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`devices both take the advantage of low thermal budgets since they are formed after the formation
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`and activation ofLDD regions and source/drain regions. However, the process is complex. In
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`addition, in the cases wherein the formation ofhigh-k dielectrics also uses gate-last approach, the
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`quality of the high-k dielectrics was often not satisfactory. Besides, forming high-k dielectrics on
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`sidewalls of the openings will adversely increase the fringing capacitance between the gate and
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`nearby features, such as source/drain regions and contacts.
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`[0009]
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`Accordingly, what is needed in the art is a semiconductor structure and respective
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`formation methods that may incorporate dual metal gates thereof to take advantage of the
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`benefits associated with band-edge work functions while at the same time overcoming the
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`deficiencies of the prior art.
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`SUMMARY OF THE INVENTION
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`[0010]
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`In accordance with one aspect of the present invention, a semiconductor structure
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`includes a first MOS device including a first gate, and a second MOS device including a second
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`gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second
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`high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k
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`dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a
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`second metal layer over the first metal layer. The second gate includes a third high-k dielectric
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`over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of
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`same materials, and have substantially a same thickness; a third metal layer over the third high-k
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`dielectric, wherein the third metal layer and the first metal layer are formed of same materials,
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`and have substantially a same thickness; and a fourth metal layer over the third metal layer.
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`[0011]
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`In accordance with another aspect of the present invention, a semiconductor structure
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`includes a first MOS device including a first gate, and a second MOS device including a second
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`gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second
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`high-k dielectric over the first high-k dielectric, wherein the first and the second high-k
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`dielectrics are formed of different materials; a first metal layer over the second high-k dielectric,
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`wherein the first metal layer has a thickness great enough for dominating a work-function of the
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`first MOS device; a second metal layer over the first metal layer, wherein the first and the second
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`metal layers are formed of different materials; and a third metal layer over the second metal
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`layer, wherein the third metal layer has a work function close to a valence band of silicon. The
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`second gate includes the first high-k dielectric over the semiconductor substrate; the second
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`metal layer over the first high-k dielectric, wherein the second metal layer in the second gate has
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`a bottom surface lower than a bottom surface of the second metal layer in the first gate; and the
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`third metal layer over the second metal layer.
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`[0012]
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`In accordance with yet another aspect of the present invention, a semiconductor
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`structure includes a semiconductor substrate; a first high-k dielectric over the semiconductor
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`substrate; a second high-k dielectric over the first high-k dielectric, wherein the first and the
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`second high-k dielectrics include different materials; a first metal layer over the second high-k
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`dielectric, wherein the first metal layer has a mid-gap work function; a polysilicon layer over the
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`first metal layer; and a second metal layer over the first metal layer.
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`[0013]
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`In accordance with yet another aspect of the present invention, a method for forming a
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`semiconductor structure includes providing a semiconductor substrate; forming a first MOS
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`device including a first gate, and forming a second MOS device including a second gate. The
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`step of forming the first gate includes forming a first high-k dielectric over the semiconductor
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`substrate; forming a second high-k dielectric over the first high-k dielectric, wherein the first and
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`the second high-k dielectrics are formed of different materials; forming a first metal layer over
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`the second high-k dielectric, wherein the first metal layer has a thickness great enough for
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`dominating a work-function of the first MOS device; and forming a second metal layer over the
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`first metal layer, wherein the first and the second metal layers are formed of different materials.
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`The step of forming the second gate includes forming a third high-k dielectric over the
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`semiconductor substrate, wherein the first and the third high-k dielectrics include same materials,
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`and have substantially a same thickness; forming a third metal layer over the third high-k
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`dielectric, wherein the third metal layer and the second metal layer include same materials, and
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`have substantially a same thickness; and forming a fourth metal layer over the third metal layer,
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`wherein the third and the fourth metal layers are formed of different materials.
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`[0014]
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`In accordance with yet another aspect of the present invention, a method for forming a
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`semiconductor structure includes providing a semiconductor substrate having a first MOS device
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`region and a second MOS device region; blanket forming a first high-k dielectric layer over the
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`semiconductor substrate; blanket forming a second high-k dielectric layer over the first high-k
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`dielectric layer, wherein the first and the second high-k dielectric layers are formed of different
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`materials; removing the second high-k dielectric layer from the second MOS device region;
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`blanket forming a first metal layer over the first and the second high-k dielectric layers, wherein
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`the first metal layer has a thickness great enough for dominating a work-function of a respective
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`MOS device; forming a polysilicon layer over the first metal layer; patterning the first and the
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`second high-k dielectric layers, the first metal layer, and the polysilicon layer to form a first gate
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`stack in the first MOS device region, and a second gate stack in the second MOS device region;
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`forming gate spacers on sidewalls of the first and the second gate stacks; forming an inter-layer
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`dielectric (ILD) over the semiconductor substrate and the first and the second gate stacks;
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`performing a planarization and exposing a top surface of the polysilicon layer; etching the second
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`gate stack until at least an upper portion of the first metal layer is removed to form a first
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`opening; etching the first gate stack until at least an upper portion of the polysilicon layer is
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`removed to form a second opening, wherein the first metal layer in the first gate stack is not
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`etched; blanket forming a second metal layer extending into the first and the second openings;
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`forming a third metal layer to fill remaining portions of the first and the second openings; and
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`performing a planarization to remove portions of the second and the third metal layers over the
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`ILD.
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`[0015]
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`In accordance with yet another aspect of the present invention, a method for forming a
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`semiconductor structure includes providing a semiconductor substrate; forming a first high-k
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`dielectric layer over the semiconductor substrate; forming a second high-k dielectric layer over
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`the first high-k dielectric layer, wherein the first and the second high-k dielectric layers are
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`formed of different materials; forming a first metal layer over the second high-k dielectric layer,
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`wherein the first metal layer has a thickness great enough for dominating a work-function of a
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`respective MOS device; forming a polysilicon layer over the first metal layer; patterning the first
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`and the second high-k dielectric layers, the first metal layer, and the polysilicon layer to form a
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`gate stack; forming a gate spacer on a sidewall of the gate stack; forming an inter-layer dielectric
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`(ILD) over the semiconductor substrate and gate stack; performing a planarization and exposing
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`a top surface of the polysilicon layer; etching the gate stack to form an opening, until at least an
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`upper portion of the polysilicon layer is removed, and wherein the first metal layer is not
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`removed by the etching; forming a second metal layer lining the opening; and forming a third
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`metal layer to fill the opening.
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`[0016]
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`The hybrid method of the present invention provides band-edge work functions for
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`both PMOS and NMOS devices. The stresses applied to the channel regions of PMOS devices
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`are increased due to the adoption of the gate-last approach in PMOS devices. In addition, the
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`threshold voltages of both PMOS and NMOS devices are both reduced.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`[0017]
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`For a more complete understanding of the present invention, and the advantages
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`thereof, reference is now made to the following descriptions taken in conjunction with the
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`accompanying drawings, in which:
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`[0018]
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`Figures 1 through 11 are cross-sectional views of intermediate stages in the
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`manufacturing of an embodiment of the present invention.
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`DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
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`[0019]
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`The making and using of the presently preferred embodiments are discussed in detail
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`below. It should be appreciated, however, that the present invention provides many applicable
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`inventive concepts that can be embodied in a wide variety of specific contexts. The specific
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`embodiments discussed are merely illustrative of specific ways to make and use the invention,
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`and do not limit the scope of the invention.
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`[0020]
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`A method for forming hybrid complementary metal-oxide-semiconductor (CMOS)
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`devices with dual metal gates is provided. The method combines gate-first and gate-last
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`approaches to achieve better effects. The intermediate stages of manufacturing a preferred
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`embodiment of the present invention are illustrated. Throughout the various views and
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`illustrative embodiments of the present invention, like reference numbers are used to designate
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`like elements.
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`[0021]
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`Referring to Figure 1, substrate 20 is provided, which may be formed of commonly
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`used semiconductor materials and structures such as bulk silicon, silicon-on-insulator (SOl),
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`silicon-germanium (SiGe ), embedded SiGe ( eSiGe ), germanium, and the like. Shallow trench
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`isolation regions 18 are formed in substrate 20, and may be used to define NMOS device region
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`100 and PMOS device region 200. Interfacial layer 22 is formed on substrate 20. Interfacial layer
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`22 helps buffer substrate 20 and the overlying high-k dielectric layer, and may be formed of
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`chemical oxide, thermal oxide, silicon oxynitride, and the like. In an exemplary embodiment, the
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`nitrogen atomic ratio of interfacial layer 22 is less than about 15 atomic percent.
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`[0022]
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`A first high-k dielectric layer 24 is formed on interfacial layer 22. Preferably, the first
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`high-k dielectric layer 24 has a k value of greater than about 7.0, and may include a metal oxide
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`or a silicate ofHf, Al, Zr, combinations thereof, and multi-layers thereof. The thickness ofhigh-k
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`dielectric layer 24 may be between about 1 nm and about 1 0 nm. One skilled in the art will
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`realize, however, that the dimensions recited throughout the specification are merely examples,
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`and will change with the down-scaling of the formation technology.
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`[0023]
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`A second high-k dielectric layer 26, preferably having a k value greater than about
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`10.0, is formed on the first dielectric layer 24. The second high-k dielectric layer 26 may include
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`metals such as La, Mg, Ba, Ti, Pb, Zr, and may be in the form of metal oxides, metal alloyed
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`oxides, and combinations thereof. Exemplary materials include MgOx, BaTixOy, BaSrx TiyOz,
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`PbTixOy, PbZrx TiyOz, and the like. Although high-k dielectric layer 26 is referred to as a
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`dielectric layer, it may actually be formed of pure metals such as La and/or Mg. Preferably, the
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`second high-k dielectric layer 26 has the function of depriving substrate 20 from the oxygen that
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`may be released by the first high-k dielectric layer 24 and/or interfacial layer 22. During the
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`subsequent annealing such as source/drain activations, layer 26 may be turned into metal oxides.
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`The thickness ofhigh-k dielectric layer 26 may be between about 0.3 nm and about 3 nm. The
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`formation methods of dielectric layers 24 and 26 include molecular-beam deposition (MBD),
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`atomic layer deposition (ALD), physical vapor deposition (PVD), and the like. Next, photo resist
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`28 is formed and patterned, exposing PMOS region 200. The exposed portion ofhigh-k dielectric
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`layer 26 is then removed, leaving high-k dielectric layer 26 in NMOS region 100.
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`[0024]
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`Referring to Figure 2, thick metal layer 32, polysilicon layer 34, and hard mask layer
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`36 are sequentially formed. Preferably, metal layer 32 has a mid-gap work function (in the
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`middle ofthe conduction and valence bands of silicon), for example, between about 4.1 eV and
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`about 5.2 eV. Alternatively, metal layer 32 may have a conduction band-edge work function
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`(close to the conduction band of silicon, which is about 4.1 eV). The exemplary materials include
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`Exhibit 1106
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`tantalum or titanium containing materials such as TaC, TaN, TiN, TaAlN, TaSiN, and
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`combinations thereof. These metal-containing materials may be in the form of metal carbides,
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`metal nitrides, or conductive metal oxides. Metal layer 32 determines the work function ofthe
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`resulting NMOS device, and hence has a thickness greater than the thickness required for
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`dominating the work function of the respective NMOS device. In an exemplary embodiment, the
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`thickness of metal layer 32 is greater than about 3 nm. The formation methods of metal layer 32
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`include ALD, PVD, metal-organic chemical vapor deposition (MOCVD), and the like.
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`[0025]
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`Polysilicon layer 34 may have a thickness ofbetween about 30 nm and about 100 nm.
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`The functions of polysilicon layer 34 include preventing contamination of metal layer 32, and
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`maintaining the height of the gate stack to a level convenient for the gate formation processes.
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`Polysilicon layer 34 is preferably pre-doped with ann-type impurity. Mask layer 36 is preferably
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`formed of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon
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`carbide, and the like.
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`[0026]
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`Figure 3 illustrates the patterning of the previously formed stacked layers, forming
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`gate stack 138 in NMOS region 100, and gate stack 238 in PMOS region 200. Gate stack 138
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`includes high-k dielectrics 124 and 126, metal layer 132, polysilicon layer 134, and mask layer
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`136. Gate stack 238 includes high-k dielectric 224, metal layer 232, polysilicon layer 234, and
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`mask layer 236. Interfacial layer 22 is also patterned as layers 122 and 222. For a clear view,
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`interfacial layers 122 and 222 are not shown in subsequent drawings.
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`[0027]
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`Figure 4 illustrates the formation of source/drain extension regions 142 and 242,
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`spacers 143 and 243, source/drain regions 144 and 244, and source/drain silicides 146 and 246,
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`which are the components ofNMOS device 102 and PMOS device 202, respectively. Contact
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`etch stop layer (CESL) 140, preferably having a tensile stress, is formed over NMOS device 102.
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`Exhibit 1106
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`Contact etch stop layer (CESL) 240, preferably having a compressive stress, is formed over
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`PMOS device 202. PMOS device 202 may further include stressors 248 (preferably formed of
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`silicon germanium) overlapping portions of source/drain regions 244. The formation methods
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`and materials of the above-discussed regions are known in the art, and thus are not repeated
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`herein.
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`[0028]
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`In Figure 5, inter-layer dielectric (ILD) 54 is blanket formed to a height higher than
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`the top surface of hard masks 136 and 236. In an embodiment, ILD 54 may include carbon(cid:173)
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`containing oxides. A chemical mechanical polish (CMP) is then performed to remove top
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`portions ofiLD 54, and hard masks 136 and 236, hence exposing polysilicon layers 134 and 234.
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`[0029]
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`Figure 6 illustrates the selective removal of the dummy gate including polysilicon
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`layer 234 and at least an upper portion of metal layer 232, which is preformed by applying and
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`patterning photo resist 156 to cover NMOS region 100. The removal ofpolysilicon layer 234
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`may be performed using either dry or wet etching. In the case dry etching is used, the process gas
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`may include CF4, CHF3, NF3, SF6, Br2, HBr, Cb, or combinations thereof. Diluting gases such as
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`N 2 , 0 2 , or Ar may optionally be used. In the case wet etching is used, the chemicals may include
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`NH40H:HzOz:HzO (APM), NHzOH, KOH, HN03:NH4F:HzO,
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`ethylenediamine: C6H4(0H) z:HzO, HF:NH4F:HzO, HF:HN03:HzO, KCl:HzO, KOH:HzO:Brz/lz,
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`KOH, HF:HN03:Hac:h:triton, HF:HN03:Hac, Iodine Etch:Hac, Nai, NaOH, HF:HN03,
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`HF:HN03:H20, and/or the like. The removal of metal layer 232 may also be performed using
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`either dry or wet etching. In the case dry etching is used, a chlorine containing gas mixture such
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`as BCh, Cb, or a combined gas ofN2 and CHF3, may be used as the etchant gas. In the case wet
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`etching is used, the wet etching chemicals may include H2S04:H20 2 : H20 (SPM),
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`HzO:HF:HN03, HzO:HF:HzOz, RCA-I, x%Brz:ethyl acetate (hot), x%h:MeOH (hot),
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`HF:CuS04NH40H:HzOz, HF:HN03:HzO, COOHCOOH:HzO, HF:HzOz:HN03,
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`HF:HzO,HF:HCl:HzO, HCl, %KOH, %NaOH, HzS04, CCbCOOCzHs, HCOOH, H3P04, HF, or
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`the like.
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`[0030]
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`In the preferred embodiment, metal layer 232 is fully removed without damaging
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`high-k dielectric layer 224. If, however, the selectivity of the etching is not high enough, a thin
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`metal layer 232 may be left un-etched to protect the underlying high-k dielectric layer 224. In
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`this case, the thickness of the remaining metal layer 232 is preferably less than 2 nm, for example,
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`between about 0.5 nm and about 2 nm, so that it will not substantially affect the work function of
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`PMOS device 202. After the etching of the dummy gate, photo resist 156 is removed. In
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`alternative embodiments, if the selectivity of etching between polysilicon layer 134 and the
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`underlying high-k dielectric layer 224 is high, photo resist 156 is not needed.
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`[0031]
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`Figure 7 illustrates the selective removal of the dummy gate in NMOS region 100
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`including at least an upper portion of polysilicon layer 134, which is preformed by applying and
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`patterning photo resist 256 to cover PMOS region 200. In the preferred embodiment, polysilicon
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`layer 134 is fully removed without damaging the underlying metal layer 132. If, however, the
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`selectivity of the etching is not high enough, a thin polysilicon layer 134 may be left un-etched.
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`In this case, the thickness of the remaining polysilicon layer 134 is preferably less than about 10
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`nm, and more preferably between about 1 nm and about 5 nm, and even more preferably between
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`about 1 nm and about 2 nm. Photo resist 256 is then removed. In alternative embodiments, if the
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`selectivity of etching between polysilicon layer 134 and the underlying metal layer 132 is high,
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`photo resist 256 is not needed.
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`[0032]
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`Referring to Figure 8, thin metal layer 60 is blanket formed. Preferably, metal layer
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`60 is formed of a material selected from the same category of metal layer 32 (refer to Figure 2),
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`Exhibit 1106
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`which material may be a mid-gap material, or a material having a work function close to the
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`conduction band of silicon. Exemplary materials include tantalum or titanium containing
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`materials such as TaC, TaN, TiN, TaAlN, TaSiN, and combinations thereof. The thickness of
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`metal layer 60 is preferably less than about 2 nm. More preferably, metal layer 60 and metal
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`layer 32 are formed of a same material.
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`[0033]
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`Next, metal layer 62 is formed to fill the remaining openings, as shown in Figure 9.
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`The exemplary materials include tungsten-containing materials such as tungsten and tungsten
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`nitride, ruthenium-containing materials such as ruthenium and ruthenium oxynitride,
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`molybdenum-containing materials such as molybdenum and molybdenum nitride, and
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`combinations thereof. The preferred work function of metal layer 62 is higher than about 5.0 eV,
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`and more preferably close to the valence band of silicon, which is about 5.2 eV. Metal layer 62
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`may be formed of PVD or applicable CVD methods.
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`[0034]
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`Optionally, metal layer 62 may include three layers, layer 62 1 for determining the
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`work function of the resulting PMOS device, layer 622 as a barrier layer, and layer 623 as are(cid:173)
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`flow layer. Layer 62 1 may be formed of essentially the same high work function material as
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`discussed in the preceding paragraph. Barrier layer 622 may include TiN, TaN, Ti, Ta, and the
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`like. The thickness of barrier layer 622 is preferably between about 1nm and about 5nm. Re-flow
`
`layer 623 may include aluminum, tungsten, and the like, and has a low melting temperature, so
`
`that it can be re-flowed to improve the gap-filling ability. The formation methods ofre-flow layer
`
`623 include ALD, PVD, MOCVD, and the like. In subsequent steps, re-flow layer 623 is re(cid:173)
`
`flowed.
`
`[0035]
`
`Figure 10 illustrates the removal of excess metal layers 60 and 62, which may be
`
`performed either by a CMP process or a wet etch. The portions of metal layer 60 and 62 over
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`TSM07-0747
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`- 15 -
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`NVIDIA Corp.
`Exhibit 1106
`Page 015
`
`

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`ILD 54 are removed, resulting in metal layers 160 and 260, and metal layers 162 and 262,
`
`respectively. The gates ofNMOS 102 and PMOS 202 are thus formed. Figure 11 illustrates a
`
`structure after the formation ofiLD 70 and contacts 72.
`
`[0036]
`
`The work function ofNMOS device 102 is mainly determined by metal layer 132. In
`
`the front-end-of-processes, thermal budgets (such as a source/drain activation) are applied. As a
`
`result, high-k dielectric layer 124 and 126 are inter-mixed, resulting in a charging effect to pull
`
`down the work function of metal layer 132 to the conduction band of silicon.
`
`[0037]
`
`The work function of PMOS device 202 is mainly determined by metal layer 262.
`
`Advantageously, metal layer 260 and 262 form an alloy in subsequent thermal annealing, for
`
`example, at about 500°C to 600°C, which annealing may be simultaneously performed with the
`
`formation ofre-flow layer 623 . The work function of the alloy will be even higher than the work
`
`function of metal layer 260 alone. As a result, the work function of PMOS device 202 is also
`
`close to the valence band of silicon. Figure 11 schematically illustrates the alloys 174 (as an alloy
`
`of metal layers 160 and 162) and 274 (as an alloy of metal layers 260 and 262). Typically, before
`
`the thermal annealing, metal layers 160 and 260 are thinner on the sidewalls and thicker at the
`
`bottom. Accordingly, there may be remaining portions of metal layers 160 and 260 at the
`
`bottoms even after the thermal annealing, although sidewall portions of metal layers 160 and 260
`
`may be fully alloyed.
`
`[0038]
`
`Experiment results have revealed that the embodiments of the present invention have
`
`improved band-edge work functions for both PMOS and NMOS devices, wherein the work
`
`functions ofNMOS devices are about 4.05 eV to about 4.1 eV, and the work function of PMOS
`
`devices are about 5.1eV. The flat band voltages of the NMOS devices shift toward the
`
`conduction band edge, causing the reduction of threshold voltages. Advantageously, the gate-first
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`TSM07-0747
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`- 16-
`
`NVIDIA Corp.
`Exhibit 1106
`Page 016
`
`

`
`approach allows NMOS devices to undergo high thermal budget, resulting in the intermixing of
`
`high-k dielectric layers 124 and 126. On the other hand, the gate-last approach in PMOS devices
`
`allows the flat band of the PMOS devices to be tuned to the valence band edge. Overall, the span
`
`of flat band voltages ofPMOS and NMOS devices is enlarged to about 900 mV or higher, and
`
`the capacitance-equivalent thickness may be as low as about 14.2A to about 14.5A.
`
`[0039]
`
`Additionally, the gate-last approach in the PMOS devices causes the increase in the
`
`compressive stresses applied on the channel regions of PMOS devices. Simulation results have
`
`indicated significant stress increase, sometimes over 1.3 GPa, depending on the raised height of
`
`the SiGe stresses. The stress increase is observed even if CESL 240 (Figure 4) applies no
`
`compressive and tensile stresses.
`
`[0040]
`
`Although the present invention and its advantages have been described in detail, it
`
`should be understood that various changes, substitutions and alterations can be made herein
`
`without departing from the spirit and scope of the invention as defined by the appended claims.
`
`Moreover, the scope of the present application is not intended to be limited to the particular
`
`embodiments of the process, machine, manufacture, and composition of matter, means, methods
`
`and steps described in the specification. As one of ordinary skill in the art will readily appreciate
`
`from the disclosure of the present invention, processes, machines, manufacture, compositions of
`
`matter, means, methods, or steps, presently existing or later to be developed, that perform
`
`substantially the same function or achieve substantially the same result as the corresponding
`
`embodiments described herein may be utilized according to the present invention. Accordingly,
`
`the appended claims are intended to include within their scope such processes, machines,
`
`manufacture, compositions of matter, means, methods, or steps.
`
`TSM07-0747
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`- 17-
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`NVIDIA Corp.
`Exhibit 1106
`Page 017
`
`

`
`WHAT IS CLAIMED IS:
`
`1.
`
`A semiconductor structure comprising:
`
`a semiconductor substrate;
`
`a first MOS device comprising a first gate, wherein the first gate comprises:
`
`a first high-k dielectric over the semiconductor substrate;
`
`a second high-k dielectric over the first high-k dielectric, wherein the first and the
`
`second high-k dielectrics comprise different materials;
`
`a first metal layer over the second high-k dielectric, wherein the first metal layer
`
`has a thickness great enough for dominating a work-function of the first MOS device; and
`
`a second metal layer over the first metal layer, wherein the first and the second
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10 metal layers comprise different materials; and
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`a second MOS device comprising a second gate, wherein the second gate comprises:
`
`a third high-k dielectric over the semiconductor substrate, wherein the first and
`
`the third high-k dielectrics comprise same materials, and have substantially a same thickness;
`
`a third metal layer over the third high-k dielectric, wherein the third metal layer
`
`and the first metal layer comprise same materials; and
`
`a fourth metal layer over the third metal layer, wherein the third and the fourth
`
`17 metal layers comprise different materials.
`
`2.
`
`The se