111111111111111111111111111111111111111111111111111111111111111111111111111
`US008252675B2
`
`c12) United States Patent
`Lee et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,252,675 B2
`Aug. 28, 2012
`
`(54) METHODS OF FORMING CMOS
`TRANSISTORS WITH HIGH CONDUCTIVITY
`GATE ELECTRODES
`
`(75)
`
`Inventors: Jongwon Lee, Hwaseong-si (KR); Boun
`Yo on, Seoul (KR); Sang Yeob Han,
`Anyang-si (KR); Chae Lyoung Kim,
`Hwaseong-si (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd. (KR)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 12/942,763
`
`(22) Filed:
`
`Nov. 9, 2010
`
`(65)
`
`Prior Publication Data
`
`US 2011/0136313 Al
`
`Jun. 9, 2011
`
`(30)
`
`Foreign Application Priority Data
`
`Dec. 8, 2009
`
`(KR) ........................ 10-2009-0121108
`
`(51)
`
`Int. Cl.
`HOJL 211336
`(2006.01)
`HOJL 21144
`(2006.01)
`HOJL 21188
`(2006.01)
`HOJL 2114763
`(2006.01)
`(52) U.S. Cl. ........ 438/592; 438/299; 438/637; 438/926;
`438/183; 257/E21.177; 257/E21.621; 257/E21.626;
`257/E21.64
`(58) Field of Classification Search ................... 438/296
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`6,130,123 A
`10/2000 Liang eta!.
`12/2000 Bai eta!.
`6,166,417 A
`
`6,265,258 B1
`6,373,111 B1
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`
`7/2001 Liang eta!.
`4/2002 Zheng et al.
`12/2002 Bai eta!.
`(Continued)
`
`JP
`JP
`JP
`KR
`KR
`KR
`
`FOREIGN PATENT DOCUMENTS
`2002-329794
`1112002
`2005-197748
`7/2005
`2006-351580
`12/2006
`1020020075732 A
`10/2002
`1020050073541 A
`7/2005
`1020060129959 A
`12/2006
`
`OTHER PUBLICATIONS
`
`Steigerwald, Joseph M., "Chemical Mechanical Polish: The
`Enabling Technology," 2008 IEEE, pp. 37-40.
`
`Primary Examiner- Fernando L Toledo
`Assistant Examiner- Valerie N Brown
`(74) Attorney, Agent, or Firm- Myers Bigel Sibley &
`Sajovec, P.A.
`
`ABSTRACT
`(57)
`Provided is a method for manufacturing a MOS transistor.
`The method comprises providing a substrate having a first
`active region and a second active region; forming a dummy
`gate stack on the first active region and the second active
`region, the dummy gate stack comprising a gate dielectric
`layer and a dummy gate electrode; forming source/drain
`regions in the first active region and the second active region
`disposed at both sides of the dummy gate stack; forming a
`mold insulating layer on the source/drain region; removing
`the dummy gate electrode on the first active region to form a
`first trench on the mold insulating layer; forming a first metal
`pattern to form a second trench at a lower portion of the first
`trench, and removing the dummy gate electrode on the second
`active region to from a third trench on the mold insulating
`layer; and forming a second metal layer in the second trench
`and the third trench to form a first gate electrode on the first
`active region and a second gate electrode on the second active
`region.
`
`15 Claims, 19 Drawing Sheets
`
`32
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`30
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`NVIDIA Corp.
`Exhibit 1101
`Page 001
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`

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`US 8,252,675 B2
`Page 2
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`2002/0058374 AI*
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`* cited by examiner
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`2/2007 Chau eta!.
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`9/2008 Chau eta!.
`9/2008 Barns eta!.
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`5/2002 Kimet al. ..................... 438/228
`112006 Brask eta!. ................... 438/206
`3/2006 Brask eta!. ................... 438/637
`12/2006 Nagahama
`
`
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`NVIDIA Corp.
`Exhibit 1101
`Page 002
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`U.S. Patent
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`Aug. 28, 2012
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`Sheet 1 of 19
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`US 8,252,675 B2
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`Fig. 1
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`16
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`22
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`NVIDIA Corp.
`Exhibit 1101
`Page 003
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`Aug. 28, 2012
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`Sheet 2 of 19
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`US 8,252,675 B2
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`Fig. 3
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`16
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`25
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`16
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`22
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`12
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`NVIDIA Corp.
`Exhibit 1101
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`Aug. 28, 2012
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`Sheet 3 of 19
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`US 8,252,675 B2
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`27
`-22}
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`20 24
`18
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`26
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`16
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`Fig. 5
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`Fig. 6
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`NVIDIA Corp.
`Exhibit 1101
`Page 005
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`Aug. 28, 2012
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`Sheet 4 of 19
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`US 8,252,675 B2
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`Fig. 7
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`29
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`26
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`Fig. 8
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`31
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`18
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`NVIDIA Corp.
`Exhibit 1101
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`1
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`NVIDIA Corp.
`Exhibit 1101
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`Sheet 6 of 19
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`US 8,252,675 B2
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`Fig. 12
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`22
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`NVIDIA Corp.
`Exhibit 1101
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`Sheet 7 of 19
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`US 8,252,675 B2
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`NVIDIA Corp.
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`NVIDIA Corp.
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`Sheet 9 of 19
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`42-
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`Fig. 17
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`NVIDIA Corp.
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`18
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`NVIDIA Corp.
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`NVIDIA Corp.
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`NVIDIA Corp.
`Exhibit 1101
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`NVIDIA Corp.
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`NVIDIA Corp.
`Exhibit 1101
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`Sheet 17 of 19
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`NVIDIA Corp.
`Exhibit 1101
`Page 019
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`NVIDIA Corp.
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`Sheet 19 of 19
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`Fig. 37
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`NVIDIA Corp.
`Exhibit 1101
`Page 021
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`US 8,252,675 B2
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`1
`METHODS OF FORMING CMOS
`TRANSISTORS WITH HIGH CONDUCTIVITY
`GATE ELECTRODES
`
`REFERENCE TO PRIORITY APPLICATION
`
`This application claims priority to Korean Patent Applica(cid:173)
`tion No. 10-2009-0121108, filed Dec. 8, 2009, the contents of
`which are hereby incorporated herein by reference.
`
`FIELD OF THE INVENTION
`
`This invention relates to methods for manufacturing MOS
`transistors and, more particularly, to methods for manufac(cid:173)
`turing MOS transistors having gate electrodes formed of dif(cid:173)
`ferent metals.
`
`BACKGROUND OF THE INVENTION
`
`AMOS transistor is widely used as switching devices. In
`contrast to conventional MOS transistors containing a gate
`electrode which is formed of poly silicon, a metal material
`with superior electric conductivity better than the poly silicon
`have been used as the gate electrode ofMOS transistors. MOS
`transistors are classified as n-M OS transistors or p-MOS tran(cid:173)
`sistors in accordance with the channel type which is induced
`beneath the gate electrode. The gate electrodes of the n-MOS
`transistor and the p-MOS transistor may be formed of differ(cid:173)
`ent metals so that the n-MOS transistor and the p-MOS tran(cid:173)
`sistor have different threshold voltages.
`
`SUMMARY
`
`10
`
`2
`layer using the dummy filler layer and the mold layer as an
`etching mask. This first metal layer may include titanium
`nitride.
`Still further embodiments of the invention include methods
`5 of forming CMOS transistors by forming first and second
`gate insulating layers on a substrate and forming first and
`second dummy gate electrodes on the first and second gate
`insulating layers, respectively. First and second electrically
`insulating spacers are formed on sidewalls of the first and
`second dummy gate electrodes, respectively. These first and
`second spacers and the first and second dummy gate elec(cid:173)
`trodes are covered with an electrically insulating mold layer.
`An upper portion of the mold layer is removed to expose an
`15 upper surface of the first dummy gate electrode and an upper
`surface of the second dummy gate electrode. The first dummy
`gate electrode is selectively removed from between the first
`spacers using a mask to prevent removal of the second
`dummy gate electrode. A first metal layer is deposited onto an
`20 upper surface of the mold layer and onto inner sidewalls of the
`first spacers. A space between the inner sidewalls of the first
`spacers is filled with a dummy filler layer that contacts the
`first metal layer. An upper portion of the first metal layer is
`removed from between the inner sidewalls of the first spacers
`25 and the dummy filler layer. The dummy filler layer is removed
`from between the inner sidewalls of the first spacers to expose
`the first metal layer. This step is performed concurrently with
`removing the second dummy gate electrode from between
`inner sidewalls of the second spacers. A second metal layer is
`30 then deposited onto a portion of the first metal layer extending
`between the inner sidewalls of the first spacers to thereby
`define a first metal gate electrode including a composite of the
`first and second metal layers. This step is performed concur-
`35 rently with depositing the second metal layer into a space
`between the inner sidewalls of the second spacers to thereby
`define a second metal gate electrode.
`
`Methods of forming insulated-gate field effect transistors
`according to embodiments of the invention includes forming
`a gate insulating layer on a substrate and forming a dummy
`gate electrode on the gate insulating layer. Electrically insu(cid:173)
`lating spacers are formed on sidewalls of the dummy gate
`electrode. These spacers and the dummy gate electrode are
`covered with an electrically insulating mold layer. An upper 40
`portion of the mold layer is then removed to expose an upper
`surface of the dummy gate electrode. The dummy gate elec(cid:173)
`trode is then removed from between the spacers by selectively
`etching back the dummy gate electrode using the mold layer
`and the spacers as an etching mask. A first metal layer is 45
`deposited onto an upper surface of the mold layer and onto
`inner sidewalls of the spacers. A space between the inner
`sidewalls of the spacers is filled with a dummy filler layer
`(e.g., polysilicon) that contacts the first metal layer. An upper
`portion of the first metal layer is removed from between the 50
`inner sidewalls of the spacers and the dummy filler layer. The
`dummy filler layer is then removed from between the inner
`sidewalls of the spacers to expose the first metal layer. A
`second metal layer is then deposited onto a portion of the first
`metal layer extending between the inner sidewalls of the 55
`spacers, to thereby define a metal gate electrode containing a
`composite of the first and second metal layers.
`According to some of these embodiments of the invention,
`the step of filling a space between the inner sidewalls of the
`spacers is followed by a step of planarizing the dummy filler
`layer to expose a portion of the first metal layer on the upper
`surface of the mold layer. In addition, the step of forming a
`dummy gate electrode on the gate insulating layer may be
`preceded by forming a buffer gate electrode containing tita(cid:173)
`nium nitride or tantalum nitride on the gate insulating layer. In 65
`addition, the step of removing an upper portion of the first
`metal layer may include selectively etching the first metal
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The accompanying drawings are included to provide a
`further understanding of the inventive concept, and are incor(cid:173)
`porated in and constitute a part of this specification. The
`drawings illustrate exemplary embodiments of the inventive
`concept and, together with the description, serve to explain
`principles of the inventive concept. In the figures:
`FIGS. 1 through 17 are cross-sectional views illustrating a
`method for manufacturing aMOS transistor according to a
`first embodiment of the inventive concept; and
`FIGS. 18 through 37 are cross-sectional views illustrating
`a method for manufacturing a MOS transistor according to a
`second embodiment of the inventive concept.
`
`DETAILED DESCRIPTION OF THE
`EMBODIMENTS
`
`Exemplary embodiments of the inventive concept will be
`described below in more detail with reference to the accom-
`parrying drawings. The embodiments of the inventive concept
`60 may, however, be embodied in different forms and should not
`be construed as limited to the embodiments set forth herein.
`Rather, these embodiments are provided so that this disclo(cid:173)
`sure will be thorough and complete, and will fully convey the
`scope of the inventive concept to those skilled in the art.
`Hereinafter, exemplary embodiments of the inventive con(cid:173)
`cept will be described in detail with reference to the accom(cid:173)
`panying drawings.
`
`
`
`NVIDIA Corp.
`Exhibit 1101
`Page 022
`
`

`
`US 8,252,675 B2
`
`3
`FIGS. 1 through 17 are cross-sectional views illustrating a
`method for manufacturing a MOS transistor according to a
`first embodiment of the inventive concept.
`Referring to FIG. 1, a first well and a second well may be
`respectively formed in a first active region 14 and a second 5
`active region 16 which are defined by a device isolation layer
`12 on a substrate 10. The first well may be formed in an ion
`implantation process in which impurities of a first conductiv-
`ity type are injected in the substrate 10. The impurity of the
`first conductivity type may comprise a donor ion such as 10
`phosphorus or arsenic. For example, the impurities of the first
`conductivity type may be injected at an energy of about 100
`KeY-300 KeY and a concentration of about 1x1013
`ea/cm3 -1x10 16 ea/cm3
`. The second well may be formed by
`an ion implantation process in which impurities of a second 15
`conductivity type opposite to the first conductivity type are
`injected in the substrate 10. The impurity of the second con(cid:173)
`ductivity type may comprise an acceptor ion such as boron.
`For example, the impurities of the second conductivity type
`may be injected at an energy of about 70 KeY-200 KeY and 20
`a concentration of about 1x1013 ea/cm3 -1x10 16 ea/cm3
`. The
`device isolation layer 12 may be formed after forming the first
`well and the second well. The device isolation layer 12 may
`comprise silicon oxide that is formed by a plasma enhanced
`chemical vapor deposition (PECYD). The silicon oxide is
`formed in a trench where a predetermined depth of the sub(cid:173)
`strate 10 is removed.
`Referring to FIG. 2, a gate insulating layer 18, a buffer gate
`electrode 20 and a dummy gate electrode 22 may be stacked
`on the substrate 10. The gate insulating layer 18 may be 30
`formed of a high-k dielectric layer such as a hafnium oxide
`layer, a tantalum oxide layer and a silicon oxide layer. The
`gate insulating layer 18 may be formed to have thickness of
`about 30 A-200 A by a method such as chemical vapor
`deposition (CYD), atomic layer deposition (ALD) or rapid 35
`thermal process (RTP). The buffer gate electrode 20 may
`comprise a titanium nitride layer or a tantalum nitride layer.
`The buffer gate electrode 20 may be formed to have thickness
`of about 20 A-50 A by a method such as CYD or ALD. The
`dummy gate electrode 22 may comprise poly silicon that is 40
`formed by a chemical vapor deposition.
`Referring to FIG. 3, a dummy gate stack 24 comprising the
`gate insulating layer 18, the buffer gate electrode 20 and the
`dummy gate electrode 22 may be formed on the first active
`region 14 and the second active region 16. The dummy gate 45
`stack 24 may be patterned using a photo lithography process
`and an etching process. The photo lithography and the etching
`process may be performed as follows. Initially, a first photo
`resist pattern (not shown) may be formed on the dummy gate
`electrode 22. The dummy gate electrode 22, the buffer gate 50
`electrode 20 and the gate insulating layer 18 may be succes(cid:173)
`sively etched using the first photo resist pattern as an etch
`mask.
`Referring to FIG. 4, a second photo resist pattern25 may be
`formed to cover the second active region 16. A lightly doped
`drain (LDD) 26 is formed using the second photo resist pat(cid:173)
`tern 25 and the dummy gate electrode 22 as an ion implanta(cid:173)
`tion mask. The impurities of the second conductivity type
`may be injected into the first active region 14. The impurities
`of the second conductivity type may be injected at an energy 60
`of about 1 KeY -20KeYandaconcentrationofabout 1x1013
`ea/cm3 -1x10 16 ea/cm3
`. The second photo resist pattern 25 is
`removed.
`Referring to FIG. 5, a third photo resist pattern 27 may be
`formed to cover the first active region 14. A LDD 26 may be 65
`formed in the second active region using the third photo resist
`pattern 27 and the dummy gate electrode 22 as an ion implan-
`
`4
`tation mask. Impurities of the first conductivity type may be
`injected into the second active region 16. The impurities of the
`first conductivity type may be injected at an energy of about
`5 KeY-30 KeY and a concentration of about 1x1013
`ea/cm3 -1x10 16 ea/cm3
`. The LDDs 26 may be formed of the
`same depth in the first active region 14 and the second active
`region 16, and diffused to the same distant below the dummy
`gate stack 24. The photo resist pattern 27 is removed.
`Referring to FIG. 6, a spacer 28 may be formed on a
`sidewall of the dummy gate stack 24. The spacer 28 may
`comprise a silicon nitride layer which is formed by a chemical
`vapor deposition process. The spacer 28 may be formed by a
`self alignment method. For example, a silicon nitride layer is
`formed to cover the dummy gate stack 24, and the silicon
`nitride layer is then anisotropically etched to remain on the
`sidewall of the dummy gate stack 24.
`Referring to FIG. 7, a fourth photo resist pattern 29 may be
`formed to cover the second active region 16. A source/drain
`region 30 may be formed in the first active region using the
`fourth photo resist pattern 29, the dummy gate electrode 22
`and the spacer 28 as an ion implantation mask. The source/
`drain region 30 may comprise impurities of the second con(cid:173)
`ductivity type. The impurities of the second conductivity type
`maybe injected at an energy of about 10 KeY-40 KeY and a
`25 concentration of about 1x1016 ea/cm3 -1x10 17 ea/cm3
`. The
`fourth photo resist pattern 29 on the second active region 16 is
`removed.
`Referring to FIG. 8, a fifth photo resist pattern 31 is formed
`to cover the first active region 14. A source/drain region 30
`may be formed in the second active region 16 using the fifth
`photo resist pattern 31, the dummy gate electrode 22 and the
`spacer 28 as an ion implantation mask. The source/drain
`region 30 in the second active region 16 may comprise impu(cid:173)
`rities of the first conductive type. For example, The impurities
`of the first conductivity type may be injected in the second
`active region 16 at an energy of about 10 KeY-50 KeY and a
`concentration of about 1x1016 ea/cm3 -1x10 17 ea/cm3
`. The
`source/drain regions 30 in the first active region 14 and the
`second active region may be the same depth. The photo resist
`pattern 31 may be then removed.
`Although not shown in drawings, the source/drain region
`30 may be formed by removing portions of the first active
`region 14 and the second active region 16 and filling an
`epitaxial silicon germanium with impurities of respective
`conductivity type in the removed portions of the first active
`region 14 and the second active region 16.
`Referring to FIG. 9, a mold insulating layer 32 is formed to
`cover the source/drain region 30 and the dummy gate stack
`24. The mold insulating layer 32 may comprise a silicon
`oxide layer. The mold insulating layer 32 may be formed in a
`low pressure chemical vapor deposition (LPCYD) process or
`plasma enhanced chemical vapor deposition (PECYD) pro(cid:173)
`cess. The mold insulating layer 32 may be planarized such
`that the dummy gate electrode 22 may be formed. The pia-
`55 narization of the mold insulating layer 32 may be performed
`by a method such as chemical mechanical polishing (CMP) or
`etch-back.
`Referring to FIG. 10, the dummy gate electrode 22 on the
`first active region 14 may be selectively removed to form a
`first trench 35. The removing of the dummy gate electrode 22
`may comprise forming a sixth photo resist pattern 34 to cover
`the second active region 16 while exposing the dummy gate
`electrode 22 on the first active region 14, and etching the
`dummy gate electrode 22 in a dry or wet etching process. The
`sixth photo resist pattern 34, the mold insulating layer 32 and
`the spacer 28 on the substrate 10 may be used as an etch mask
`while the dummy gate electrode 22 is removed. The buffer
`
`
`
`NVIDIA Corp.
`Exhibit 1101
`Page 023
`
`

`
`US 8,252,675 B2
`
`5
`gate electrode 20 may be used as an etch stop layer during the
`dummy gate electrode 22 etching. The sixth photo resist
`pattern 34 formed on the second active region 16 is removed.
`Referring to FIG. 11, a first metal layer 36 may be formed
`on the entire surface of the substrate 10. The first metal layer 5
`36 may comprise a titanium nitride layer that is formed by a
`chemical vapor deposition (CYD) or an atomic layer deposi(cid:173)
`tion (ALD). The first metal layer 36 may be formed of the
`same thickness on the bottom surface and the sidewall of the
`mold insulating layer 32 as well as a top surface of the mold 10
`insulating layer 32. If the first metal layer 36 is buried in the
`first trench 35, the first metal layer 36 in the first trench 35
`may comprise a void formed by overhang of the first metal
`layer 36. The void may be caused by losing conductive reli(cid:173)
`ability of the first metal layer 36. Therefore, the first metal 15
`layer 36 may be formed of uniform thickness on the bottom
`and the sidewall of the first trench 35.
`Referring to FIG. 12, a dummy filler layer 38 may be
`stacked on the first metal layer 36. The dummy filler layer 38
`may be formed of the same material as the dummy gate 20
`electrode 22. The dummy filler layer 38 may comprise poly
`silicon. The dummy filler 38 may be completely fill the first
`trench 35 on the first active region 14. The poly silicon may be
`formed by a chemical vapor deposition method. The dummy
`filler layer 38 may comprise a void in the first trench 35.
`Referring to FIG. 13, the dummy filler layer 38 may be
`planarized to expose the first metal layer 36. The planariza(cid:173)
`tion of the dummy filler layer 38 may be performed by a
`chemical mechanical polishing (CMP) or an etch-back. The
`dummy filler layer 38 may remain in the first trench 35.
`Referring to FIG. 14, the first metal layer 36 on the mold
`insulating layer 32 is removed. And, an upper portion of the
`first metal layer 36 disposed between the mold insulating
`layer 32 and the dummy filler layer 38 becomes recessed. The
`removing process of the first metal layer 3 6 may be performed 35
`in a dry or wet etching method in which etching selectivity to
`the firstmetallayer 36 is two or more times greater than to the
`dummy filler layer 38 and the mold insulating layer 32. The
`first metal layer 36 may remain on the bottom surface and a
`lower sidewall of the first trench 35. The first metal layer 36 40
`may be formed symmetrically on both sidewall of the first
`trench 35. Therefore, the first metal layer 36 may be remained
`in the first trench 35 to form a first metal pattern with a 'U'
`shaped section.
`Referring to FIG. 15, the dummy filler layer 38 on the first 45
`active region 14 and the dummy gate electrode 22 on the
`second active region 15 may be removed to form a second
`trench 40 on the first active region 14 and a third trench 43 on
`the second active region. The dummy gate electrode 22 and
`the dummy filler layer 38 may be removed simultaneously in 50
`an etching process because the dummy gate electrode 22 and
`the dummy filler layer 38 are formed of poly silicon. Thus, the
`method for manufacturing aMOS transistor according to first
`embodiment can improve or maximize the productivity.
`The first metal layer 36 may be exposed in the second 55
`trench 40 on the first active region 14, and the buffer gate
`electrode 20 may be exposed in the third trench 43 on the
`second active region 16. The second trench 40 may be shal(cid:173)
`lowerthan the third trench 43. The first metal layer 36 may be
`disposed on the bottom surface and the lower sidewall of the 60
`second trench 40. The second trench 40 and the third trench
`43 may be different from each other in thickness.
`Referring to FIG. 16, a second metal layer 42 may be
`formed on the entire surface of the substrate 10. The second
`metal layer 42 may fill the second trench 40 and the third
`trench 43. The second metal layer 42 may comprise at least
`one of aluminum, tungsten, titanium and tantalum that is
`
`6
`formed by a method such as PYD or CYD. The second metal
`layer 42 may be formed without a void in the second trench 40
`on the first active region 14.
`Referring to FIG. 17, the second metal layer 42 is pla(cid:173)
`narized to expose the mold insulating layer 32. A first gate
`electrode 46 and a second gate electrode 48 may be formed on
`the first active region 14 and the second active region, respec(cid:173)
`tively. The first gate electrode 46 and the second gate elec(cid:173)
`trode 48 may be extended in a vertical direction to the direc-
`tion of the source/drain regions 30 arrangement. The second
`metal layer 42 may be planarized by a method such as CMP
`or etch-back. The second metal layer 42 may be planarized to
`separate the first gate electrode 46 and the second gate elec(cid:173)
`trode 48. The first gate electrode 46 and the second gate
`electrode 48 may be formed to have top surfaces of substan(cid:173)
`tially equal level. The first gate electrode 46 may comprise the
`buffer gate electrode 20, the first metal layer 36 and the
`second metal layer 42. The first gate electrode 46 may com(cid:173)
`pose a p-MOS transistor on the first active region 14. The
`second gate electrode 48 may comprise the buffer gate elec(cid:173)
`trode 20 and the second metal layer 42. The second gate
`electrode 48 may compose ann-M OS transistor on the second
`active region 16.
`In general, the operating voltage of the n-MOS transistor
`25 and the p-MOS transistor may be different from each other.
`Current of the n-MOS transistor may be adjusted in accor(cid:173)
`dance with a switching voltage. Thus, the second gate elec(cid:173)
`trode 48 may comprise less than two metal layers in order to
`simplifY the estimation of an electric resistance or a work
`30 function according to combination of the metal layers. The
`p-MOS transistor may be different from then-MOS transistor
`in operating voltage. The first gate electrode 46 may comprise
`at least two metal layers because the p-MOS transistor per-
`forms a simple switching operation. For example, the oper(cid:173)
`ating voltage may be lower to thep-MOS transistor than to the
`n-MOS transistor. If a void is formed in the first gate electrode
`46, operation characteristic of the p-MOS transistor may be
`deteriorated. According to the first embodiment, the first gate
`electrode 46 does not have a void to thereby prevent the
`operation characteristic of the p-MOS transistor from dete(cid:173)
`rioration.
`Not shown in drawings, the mold insulating layer 32 on the
`source/drain region 30 may be removed to form a contact
`hole, and a source/drain electrode may be formed in the
`contact hole.
`FIGS. 18 through 37 are cross-sectional views illustrating
`a method for manufacturing a MOS transistor according to a
`second embodiment of the inventive concept. Referring to
`FIG. 18, a first well and a second well may be formed in a first
`active region 14 and a second active region 16 that are defined
`by a device isolation layer 12 on a substrate 10. The first well
`may be formed by injecting impurities of a first conductivity
`type. The impurities of the first conductivity type may com(cid:173)
`prise donor ions such as phosphorus or arsenic ions. The
`impurities of the first conductivity type may be injected in the
`first well at an energy of about 100 KeY-300 KeY and a
`concentration of about lxl013 ea/cm3 -lxl0 16 ea/cm3
`. The
`second well may be formed by injecting impurities of a sec(cid:173)
`ond conductivity type opposite to the first conductivity type.
`The impurities of the second conductivity type may be
`injected in the second well at an energy of about 70 KeY -200
`KeY and a concentration of about lxl0 13 ea/cm3 -lx10 16
`ea/cm3
`. The device isolation layer 12 may be formed after
`forming the first a