Page 1 of 19
`
`SAMSUNG EXHIBIT 2002
`NVIDIA V. SAMSUNG
`TRIAL IPR2016-00134
`
`

`
`US8,53(1,6I)1)B2
`Page 2
`
`(161
`
` GEfi
`
`US. p2AH:E_N:f D9CU1;4E_N$S
`
`2008/0099851 A1*
`2008/0173947 A1
`
`5/2008 Hsu etal.
`7/2008 Hou et al.
`
`257/369
`
`8/2008 Hsu et al.
`2008/0188044 A1
`2/2009 Yang et al.
`2009/0039433 A1
`6/2009 Chudzik et a1_
`2009/0152636 A1 '1‘
`OTHER AUUN3
`
`............. .. 257/359
`
`lateslfita, Y., et al,, High-Pertormance and Low-Power CMUS
`Device Technolooies Featuring Metal/High-k Gate Stacks with
`Um'am'a Sum-ned Si]-can Channels an (1009 and (1109 a>
`I_E_EE
`
`
`
`. .- .666 , 4-pages
`.
`Hou, Y. T., et a1., “High Performance Tantalum Carbide Meta1"GaIe
`btacks or nN_1'ObFJ:1 Application, FEE]: international Jzlectron
`Devices Meeting, IEDM Technical Digest, Dec, 2005, Ep. 31-34,
`Washington, D.C., United States.
`Hm) LflL“Mv wmHgh%
`
`Digest of Technical Papers, 2006, pp. LL-12,
`I-1aWa'ri,United—States.
`
`I-EFF, Hanelulu,
`
`' c1ted‘by examiner
`
`............... .. 438/244
`
`
`
`8/2007 Egp_ic11eta1.
`7,253,053 B2*
`10/2008 Doris et al
`7 432 567 B2
`6/2002
`2002/0079548 A1*
`3/2003
`2003/0057499 A1
`7/2003
`2003/0123334 A1
`4/2004
`2004/0066535 A1
`12/2004
`2004/0245578 A1
`12/2004
`2004/0256679 A1
`5 ZQQS
`2005 QU2875 fill
`7 700;
`700; m;7]»;R A]
`1 1/2QQ§
`2095 ( Al
`6 20115
`20116 (LLLL578 A_1
`7 vong r~ I.I.I_gt_a1,
`200610166474 A_1
`12007 H-emg-el 31.
`................. .. 257337
`2007 00-1-8244 &—1*
`4 200" .
`200" 00753-51 A-1
`5 2067 Naitaj-irm
`2007 0105317 A1
`6 200 Bvhr
`200 0138559 K1
`200770772975 AT2 1'1 Z007 Schaefief 61 31.
`
`........... .. Z57/377
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`

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`AWL
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`5 , twarmetal s haVi'rrg‘dill"erein‘wo‘r'k func-
`
`US 8,536,660 B7
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`dUPe‘d50E11'Ce7dTH‘IiII(.4
`704, filed Oct. 25, 2006, entitled “Semiconductor Devices
`with Dual—Metal Gate Structures and Fabrication Methods lo C1Cle5: and CODWCT etch 5T0P layers are then 101‘m‘3Cl< U115
`he1;eof”mh1eh patent app ]ca];]Qn 15 ]ncQ};pQ];a];ed herem by
`process is relativelv simple and the resulting contact etch
`reference.
`step lastersaate
`stresses. Hovvevei,
`formation and the activation of'ED‘D regions and source. drain
`
`TEC FTELD
`
`
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`I
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`ductor tlVI'OS) devices and manufacturing methods for form-
`ing the same.
`
`::v“: -‘-‘uv “"‘u“n‘
`g
`-
`layer may be released under the thermal budgets, and cause
`mterfacial layer re-growth. further, patterning metal layers
`
`"2
`
`Metal-oxihde-semiconductor (T) devices are basic
`building elements in integrated circuits.Aconventional MOS
`devi .5--e-.--ea .,e-
`
`the steps oI‘To1-ming dummv gates forbolh PMOS and NMOS
`d_e;LL(‘_es__T
`1 )r_egiQns gate spacers soiirceldrain regions and
`-
`-
`.
`-
`-
`.
`
`v
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`Plwfis deViCe, adjusting The W01'k fi1nC1i0n Cl0Se ‘[0 the
`Valence band. Adiusting The WOIK f11I1CIi0I1 Oflhe p0lVSi1iCOI1
`
`
`the forrntion and activation0 regions and source. drain
`regions. However the process is complex. ln addition in the
`
`gaw-
`titties.
`M63 d'eViCe'5'WiTh 13UlY5i1iC©"1’1 @313 e'le'CT1’0'd'e'5 - 33 often not satisfactory. Besfdes, Iorming High-K dielectrics on
`F131‘ deP1eT1011 eflecta Wh1Ch15 3150 1‘eleffed T0 35 3 P013’ del3le-
`sidewalls of the openings will adversely increase the fringing
`fimefleQUEmlydeflflbn€EedmflH< bawewtmgam@dmarbyEmums,
`sueh_as
`electiiealfields‘
`‘'
`"“
`,
`'
`'
`afidee-11-facts.
`Accordingly, what is needed in the art is a semiconductor
`silicon layer, the depletionlayer includes ionized non—mobile 40 structure and respective formation methods that may moor-
`donor sites whereas inap—doped polvsilicon laver the deple—
`Porate dna meta gates thereof to 13; e adjganlaggl o_f_th_e hen-
`
`e- -e:.:=..::e .:. --
`depiertoncffearesuirsmau‘
`'
`‘
`ieTrcieso‘f‘tlEpri"or'ai't.
`dielectric tlfickness, mal?ing it more difiicult for an inversion
`layer to be created at the surface of the semiconductor.
`The use of
`d.ie.leet.i:ies—tends to—mal»;e the caizitier
`
`tion layer in the polysilicon gate becomes more significant in
`semiconductor structure includes a first MOS device includ-
`thickness when compared to the thickness of the thin gate
`ing a first gate, and a second MOS device including a second
`
`
`trodes limits device scalabilitybyimposingaloweround on
`IWI high-k dielectric; a ifit metal ayer over the second
`how much the effective gate dielectric thickness can be
`high-k dielectric wherein the first metal layer dominates a
`reduced.
`wor_k-fii.iJ_et.i_o.iJ_oftlJ.e first MOS '‘
`55 l-a-yeroverthe—firstmet-al
`tlnrdhrgh-kdielectricovertliesenncoiiductorsubstrate,
`wherein the lirst and the llZTlI'(‘l—l‘Tlgh-l< dielectrics are formed of
`same m.aI.er_ia_ls,_a_nd heme substantially a same thj_ekness;_a
`
`45
`
`SUMMARY OF THE INVENTION
`
`iirg“riietalgateelectrodesoTmetals'ilrcidegateelectrUdes,
`wherein the metallic gates used in NNIUS devices an(lT’lVlOS
`deg/ices also pi:e.fetablyha3Leham1:ed.gework_fi.Ln_etj_(1ns_(‘ur-
`rently,
`for forrriiag gate
`NMOS devices, suclras TaC,
`materials, and have substantially a same tliickness; and a
`PMOS devices, even though metallic materials having band-
`fourth metal laver over the third metal laver.
`edge work fimctions have been found these materials have
`
`
`these metallic materials SlTlTI, for example, toward the mfd-
`65 mg a lirst gate, and a second'lVIOS device including a second
`gap level. The performance of the resulting PMOS devices is
`gate. The first gate includes a first high—k dielectric over a
`
`Page 14 of 19
`
`

`
`
`
`4
`3
`fi'Ibl.'l1'l'g'l'l-lx d'ielect'ric, whereiIrthe'fi1staI1'd‘tlie s -L and the first and the second gate blfatlxb;pafi
`dielectrics are formed ofdifierent materials; a hrst metal'layer
`narization and exposing a top surlace of tlie polysiTicoi1 layer;
`over the second high—l< dielectric wherein the first metal laver
`etehmg the geegnd (I313 stag], mm] at ]ea5t an upper pgfijgn gt
`
`-,-.;
`-__.-:..-ea; -5 -_-
`e es--e,--; ' -.-,e-
`
`.—--- i—--’ ’ 3 ’
`
`
`
`Of flT€‘fi1‘ST M95 Cl€V1C€§ 3‘Sef01Td fifit
`the first gate stack until at least an upper portion of the poly-
`n1elanaYe1'~ Wher9111 the first and The Second melanayers are
`silicon laver is removed to form a second opening wherein
`formed of different materials; and a third metal laver over the
`t_he_fiFS{_mem_ 183,3]: in Q9 3 fig; gag Sea 3}: ~}S_H6{_e$Ched. btaflket
`- III n-
`-
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`-
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`.n '
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`3
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`Ili‘ I“I'
`IivJ““ ii ii '
`‘I‘ ""‘ii
`
`gale
`second openinvs‘ forming a third metal layer to fill remaining
`includes the first high-k dielectric over the semiconductor
`.
`substrate; the second metal layer over the first high-k dielec-
`Parr
`.
`.
`T
`.
`.
`
`bottom sttiefaee lower than a bottom surfaeerof t-he seeonel
`v_
`__ v_r
`-‘_‘v.v_M.i'_‘ "_,"___
`
`secondmetallayer.
`In asscrdam Cemiflg get amflflm: aspml DfflGB1m:BSBm]~m,B]D_
`w
`'
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`V
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`s"ub‘s:trate;afirs1high-kdielectricovertl1es'errriconduc1o‘r
`12961. Wllelel” tllelllqfilld me §§C73l‘dl‘1gh'k_d15l'e_CTfi? iayeis
`substrate; a second high-l< dielectric over the first high-l{
`dje eehje g'hgr_ejn the first and the segehd hjgh-k dje eehgjes 29 are formed of different materials’ forming a first metal laver
` ; a—fi-r-st—rnetal ayer—over—t-he
`oxlerthe-second
`
`metanayers Over the ED’
`
`
`‘u.
`.a.--
`- U "H
`- i'u'
`‘i—"‘ i
`3 i
`i
`15 mm’
`‘H i
`providing a semiconductor substrate; forming a first High—l<
`dielectric laver over the semiconductor substrate‘ forming a
`
`US 8,436,660 B7
`
`
`5
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`W01‘k fi1I1Ct1OI1; a p01ys1T1c0n layer OVGI‘ ‘E116 first metal'1ayer;
`and a second metal layer over the first metal layer.
`
`
`
`
`
`
`function of a respective MUS device; forming a polysilicon
`layer over the first metal
`t_h_e first and the
`° wemdmghi$eke&klaym;$&&fi
`polysilicon layer to form a gate stack; forming a gate spacer
`-
`3
`on a sidewall ofthe gate stack; forming an inter-laver dielec-
`Pr0Y17fi{1g 3 S§3m1C0nd11Cl0r Subslralel fQ1Tn1ng 3 first M03
`device including a first gate. and forming a second MOS
`me g_L
`V 1.
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`Steele;
`‘
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`'r——— '''''r
`iI“i
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`.u-
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`
`gate ifiel “files fefmiifig 3 flies‘ h‘igh‘k dielegefiie 9731 the. Semi.‘ 3” polysilicon layer; etching the gate stack to form an opening;
`conductor substrate; forming a second'high-k dielectric over
`mm] at least an upper Pemen of the pelyslheen layer 15
`the first high-k dielectric. wherein the first and the second
`remmzed and mherejn the firs; mela] ]a¥eIj5 Del remeyed by
`i .I-- i
`.- II ‘II . --
`.-. ‘
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`fin‘ 13331 13731 has 3 rhlcklfiss great 31155311 fm dfiiififimlig 53
`The hybrd method oft 1e present invention provides band-
`a work-function otThe hrst MOS device; and forming a sec- edgeW MQ&deV,'ees Ihe
`'
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`-last approachin
`
`
`STEP GI f0mTiTTg the >"eV0T1d gale mcludeb fWTTTiTTg 4 third
`FMUS devices. ln ad'd'iTion, the threshold voltages of both
`high—l< dielectric over the semiconductor substrate; wherein 40 NmS deV~Lee5 . I 2 13 Mb I rm L. H]
`the first and the third high—k dielectrics include same materi-
`
`
`
`.11.]
`.5]
`].l.l_ll.]
`H
`metal'layer and the second metal'layer include same inateri-
`For a more complete uhderstahdmg of the present mveh-
`als and have substantially a same thickness‘ and forming a 45 q mmmadem the
`
`
`’=*u""=; iv‘i“"‘i‘i!“’ ”;=;
`_ 5,
`
`In accordance with yet another aspect offhe present inven-
`1-IGS. 1 through 1] are CfQss-geC[1011a] Vlews 01 1me1»me_
`tion. amethod for foriningasemiconductor structure includes
`diale stages in the [na1]]]fag]]]fino Q1 an emhgdjmeht Q1 the
`,.
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`<0
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`l‘)4.TAll,l:,l‘)‘l‘)FS(',RTP TUN (‘IF l'l,l,IJ’S'l‘R75i‘l“T‘\/4,
`
`substrate‘ blanket forming a second high-k dielectric layer
`over th_e fi_rstJJ_igh-lg die eclizic ayer, mlJei;e'iJ tJe first and I16
`
`
`lI(5Hll'l1‘e
`Illellts ciledlscflbed lll detall helUW.
`Slfiljlld be apfltecilated;
`. -k ele‘CtHC layel
`Second .
`llals, Ielllivlllg
`second V US device region; blanket forming a hrst metal
`however; that the present invention provides many applicable
`lay_ero\Lerth_efirst_a.n_d_the seeo_n_d high-k dielectric layers
`
`EMBODIMENTS
`
`oo II1'€I€l'ylll'IIlb['l'2l'l‘lVCU'fbp'€Cl'fi'C'WayblU makeaIid‘use'tlre‘inven-
`;
`'
` mhg a worlx-fuI1'ct'ion of a respective MGS
`tion; and do not limit the scope of the invention.
`forming a polysilicon layer over the hrst metal'layer; pattem-
`ing the first and the second high-k dielectric lavers the first
`Ainethod for forming hvbrid complementary metal-oxide-
`
`
` r,aHd&e -.
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`='i"v‘6 i“‘ii iIii"'iiii"i"I
`vided.TlIemethodcon'rbinesgate=firsta11dga-te=last
`'
`second MUS device region; forming gate spacers on si?1e-
`65 approaches to achieve better effects. The intermediate stages
`of manufacturing a preferred embodiment of the present
`
`.---e-,- ,_
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`the\la.11LE ''
`
`Page 15 of 19
`
`

`
`US 8,436,660 B7
`
`6
`5
`Poly srliconlayei 3'4‘nIay haveca lIl1'l'ClC[1'Cbs ofbetweeiraboixt
`i'l'lustrat"rve enrbodinieirts o‘l"tlIe‘prese1it iirveirtion, l'ike‘refei-
`30 nm and about TOT) nm. The functions of polysilicon layer
`ence numbers are used to designate like elements.
`34 include preventing contamination of metal layer 32 and
`Referring to FIG. 1 substrate 20 is provided which may be
`
`
`-
`=-
`2-’ ——-v
`;-
`sti‘uct=c1i'essucliasbu-l-ksi-lieon,s"
`~
`ask layer 3'6 is
`sil‘icon-germanium (STGC), emb dded'SiGe LeSiGe). germa-
`erably pre-doped with an n-type impunty.
`nium. and the like. Shallow trench isolation regions 18 are
`preferably fomied of dielectric materials. such as silicon
`
`
`
`
`
`
`
`
`
`200. l t-he—l-i-ke.
`deyiee-region
`layer 22 is formed on substrate 20. lnterfaciarlayer Z2‘helps
`10
`FTG. 3 illustrates the patterning of fhe previously formed
`buffer substrate 20 and the overlying high-k dielectric layer.
`stacked layers. forminggate stack 138 in NMOS region 100.
`m Gale-star.k_l38
` - -~-- -- ' -- - ---~----- -- =- e- - '1—24and1—2-6,n&etall-ajyerl-32,
`
`
`
`
`
`
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`
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`ni'rr0'genatUmicra‘tioo‘finrerfacia1layer22isless“tlr2rnabo‘trt
`polysilicori
`I321, md B6. Ga‘tes'tack238
`15
`15 atomic percent.
`includes high-k dielectric 224 metal layer 232 polysilicon
`A m<im@— 1mfmm layer 234, and mask laver 23.6.
`l.n.te.1:faLja.l laver 22 is also
`' 22. ,$e&%‘t '
`'
`* "
`‘
`'
`‘ l and 222. For a+lear‘ view,i "
`
`v.I‘I !_4l"a"'-l'a'IOI ire ‘M’
`N" “.'I“‘."'I 'O"'
`Ii ‘II" rm";
`Io-."‘.o I‘
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`a silicate of H'f,Al, Ar. combinations thereof, and multi-layers
`MG. 4 illustrates the formation of source drain extension
`mmmi'HeM&m$ hvuJim\'®mmgomM2amMLmacasM3mMLwnme/mm
`-
`.—
`-.
`...—.
`betweeiideeutlnrnandaboutl-0—niii.€|ne '
`-.--
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`H -- H.-.e.:.- -.--..e-.. A---- A-
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`the specification are merely examples, and will change with
`device 202, respectively. Contact etch stop layer (CESL) M0,
`the down—scaling of the formation technology.
`preferably having a tensile stress
`is formed over NMOS
`
`
`
`
`Va I’-’
`II III!
`I
`
`i
`u—
`—
`—aiv=
`
`
`device 202 may further include stressors 248
`ayer . The second'lTigh-k dielectric layer 2'6 may include
`202.
`metals such as La. Mg. Ba. Ti. Pb. Zr. and inav be in the fonn
`(preferably formed of silicon germanium) overlapping por-
`In_g
`-n
`I
`-o In,
`A1
`n- In;
`gIn- I!I_ II
`g
`
`ofi:n.eta1oxides,m.eta1alloyedox.ides,and ans:
`an
` materials ineluelc Mgex, Ba-TiX9y, Ba 3U --:
`Sr;
`i),(;)Z, PbTi,,(;)y, Pb7.rN iV(‘)Z, and the like. Although high-k
`dielectric layer 26 is referred to as a dielectric layer. it may
`actually he fanned of pure
`
`
`
`
`
`
`
`
`
`tion of depriviirg substrate2
`relea sed'by the l'lI'SllT1gh-k dielectric layer 271 and or interl
`
`
`
`'"ti9hs,26—lHa§. beturneeluietal
`
`'1"
`I I-
`u nu 'u-vv-
`.
`'-
`.v
`
`
`about 073 nm and about 3 nm. The formation methods of 40 of metal layer 232, which is preformed by applying and
`dielectric layers 24 and 26 include molecular—beam deposi—
`patterning photo resist 156 to cover NMOS region 100. The
`tion—(M-BD),at6rniclayer—deposi-ti6néALD),physicalvapor
`remevalofpelysi-lic9h1a§"er234n;aybeperf6rmedusi-ng
` ' \PSVB),aTICll‘lTEl'l'kE.l‘lE1‘i‘l,p'lTU'l'DrES‘lSl2‘8l'S
`
`erther' diyorvvetctcl-rIrrg'. ,' ,
`formed and patterned, exposing FMUS region 2170. The
`process gas may include CF4, CH'F3,N'F3, SF6, Brz, H'Br, C12,
`exposed portion ofhigh—kdielectric layer 26 is thenremoved 45 or combinations thereof.Diluting gases such as N’) O’) orAr
`
` '' ' ' ' '
`
`
`
`L00
`mayopt.ionallybeusedln—thecasewet—etchi.ngisused,Lhe
`a
`‘E iv:
`.
`
`
`—
`~ ~
`.
`,
`—
`491-ltl-l2F)2.~l-I26)-(ArPl’v‘B,N-ll2()ll,
`34, and'hard mask layer 36 are sequentia
`ly formed. Through-
`KOFI, H'NO3:NH4F:H2O,
`ethylenediamine:C6H4(OH)2:
`out the description. the term “metal layer(s)” refers to con-
`H70. HF:NH4r :H,O. HF:LNO3:H,O. KCl:H,O. KOH:H,O:
`
`2,,
`.- -..o,.,.. - ,.
`-
`
`
`led-ine Etehfl-Iae, Na},
`1
`l, H-T.H-N93, H-T.H-NO5.H2G,
`and or the like. The removal of metal‘layer 232 may also be
`perfomied using either dry or wet etching. In the case dry
`is used,_3 Qhlnriile
`gas IJJ.lX_1l].l”_E: su_c.h_as
`
`
`
`
`
`andvalence bands ofsilicon), for examp e, between about4.l
`eV and about 5.2 eV. Alternatively metal layer 32 may have
`a_c_on_d11c.t.i_m1_ha_ud-edgew smm t.l1e_cou_d11c-
`
`tlIeetchaIIlg'as.Inrliecasewe1etclmIg' i'su'sed,rhewe1
`
` '' " " '
`
`
`etclfing chemicals may include H2SU4:H2O2: Fl2O(SPTVl),
`such as TaC, Ta_N, TIN, TaAlN, TaSIN, and comlinations
`H_Q:HE;H\I.O_:,, H Q;H3'_H 0
`RCA-
`x °o Rr ;e_th;fl
`thereof ”“m<mm—
`5
`
`
`
`.
`
`
`
`v,'-1 1 ' ' V, . . ' . v' y. . - 1 5 0 Z
`
`
`
`
`
`
`
`
`
`
`
`
`
`H'F‘.‘I=I262rLN63,
` s l'h‘C'VVUTlx fI:II1‘C1'loI1 U‘f‘l.'l’1'€T€>lIl'lTl'I1'g
`oo HT.'H'N63.J26, C66 iC66H‘:h28,
`NMOS device, and hence has a tlfickness greater than the
`FFTHZO, 2O, FlCl, °o (UH, °o NaO'H, HZSC4,
`CCl3COOC.H5 HCOOH HBPO4, HF or the like.
`-
`-2 e
`:
`-_--.9 1955931‘ , metal layer 23-2 is fie}-l-ly
`- . " " '-xd"relect‘riclayer22'4.If,
`
`
`
`
`65 however, the selectivity of the etclfing is not lfigh enough, a
`formation methods of metal layer 32 include KED, PVT),
`n1etal—organic chemical vapor deposition (MOCVD). and the
`thin metal layer 232 may be left un—etched to protect the
`
`Pag6L60f‘T9
`
`Nv94441c4;oo4c434J_
`
`Page 16 of 19
`
`

`
`US 8,436,660 B7
`
`8
`7
`nrixed, resulting lira charging effecfto pcrll dUwl1—tlie—woik
`ness U‘f‘tl1e rema'i'n'i'lIg metal layei 2'32‘is preferabl) less than
`function ofmetal'layer I32 to the conduction band of silicon.
`2 nm, for example, between about 0.5 nm and about 2 nm, so
`The work function of PMOS device 202 is mainly deter-
`that it will not substantially affect the work function ofPMOS
`
`
`
` deVice202.A.ftert-hee.tc.hing—ofthedu-mni .
`
`-,— 2: e
`5 2.
`
`
`"
`,
`1-56-'rsremoved.Iil
`—
`.
`.
`~
`;
`i
`of etclfing between polysilicon layer 1'34 and the underlying
`example, at about 500 C. to 600 C., which armeallng may be
`high-k dielectric layer 224 is high, photo resist 156 is not
`siinultaneouslv performed with the formation ofre-flow layer
`
`
`
`
`n1etal}ayer26(-)—a-lene.Asa—i-esu-1-t,t~he
`..--r
`a
`.--
`--a.--.--
`a
`.-
`:--
`.-
`.
`in NIVITTS region 1111? including at least an upper portio of 10 work function of PIVITJS device 202 is also close to the
`polvsilicoii layer 134, which is preformed by applying and
`valence band of silicon. FIG. 11 schematically illustrates the
`mp
`
` ',po-1-ysil-ieonlayerl-34-is—fu-l-l=y'_ :‘:-:=~=---: -= a . a-: ~s-=---
`
`
`
`
`memal ,mmhymtWflm2fi
`the sidewalls and thicker at the bottom. Accordingly there
`
`ever the selectivity of the etching 1S not high enough, a thin 15
`
`
`
`
`
`
`4
`I‘ "“'a'lII
`i'I"aI'I"I"'l" "4'!
`a'a'lII
`
`bxperiment results have revealed that the embodiments of
`nm and about 5 nm, and even more preferably between about
`m Bheto
`'
`is then_rem.0vw In 20 the presenLinV '
`Ve improved band-edge W -
`-:-. --.
`:-
`5-.
`: :::
`e:-..
`--.-.-
`--.
`e
`altenati-Ve
`-.---;:-.-
`
`
`potysilicon layer
`tU'a'bU'EIT4.l e’\,
`High, photo resist 256 is not needed.
`and the work function ofPlVI‘OS devices are about 5.1 eV.
`he
`Referring to FIG. 8 thin metal layer 60 is blanket formed.
`flat band voltages of the NMOS devices shift toward the
`mBre_erably,nieta1lasyer60isfoi:ined—oaniateria1selected°
`
`
`vi;=_=‘ =iv;. sh,me aHoWs
`"“i”““°_iv‘
`'=
`e=
`i . ,
`
`
`NIVIOS devices to undergo High thermal'budget, resulting in
`which material may be a mfd-gap material, or a material
`the intennixing of high-k dielectric layers 124 and 126. On
`having a work function close to the conduction band of sili-
`th.eo1herhand,thega1e—lasIapproachi.nEl¥LQSdesLic.es"
`
`
`'' " —
` mEC,EN,T$,Tm¥N,ESW,wd 3U fibWs$e%mbmdof
`combinations thereof.
`he thickness of metal
`layer 611 is
`valence band edge. (‘)verall, the span of‘fiat‘band voltages of
`preferably less than about 2 nm. More preferably. metal layer
`PMOS and NMOS devices is enlarged to about 900 mV or
`
`Nem,memHfi%Qfi epe& lovwasabetitlr4.2Ato—abeutl-4.513;.
`iirgs, as stmwnin FIG. 9. The iinmPMGS devices
`tiingsten-containing materials such as tungsten and tungsten
`causes the increase in the compressive stresses applied on the
`nitride, icutheniunn-containing mateija s such as nitheniiim
`ehannel Legions of PIVLQS deyiees Simii ation i:esu_hs haye
`
`
`
`
`
`
`
`
`binations th reof. fhe preferred work tunction of metal'layer 40 increase is observed even if_C'l:SL 2T0 (F IG. 4) applies no
`62 is higher than about 5.0 eV and more preferably close to
`compressive and tensile stresses.
`
`
`
`'" , ' '
`
`‘.7eV r
`
`'
`
`changes, substitutions anc alterations can be made herein
`Optionally, metal layer 62 may include three layers, layer
`62. for determining the work function ofthe resulting PMOS 45 without departing from the spirit and scope ofthe invention as
`device.,—1ayer62
`caims
`
`
`l'a‘yel‘.I,ay‘er-621may
`==': "’ tfihe1m-
`‘
`‘
`.
`’a v
`'=:"='i_'
`ticular embodiments of tie process, machine, manufacture,
`work function material as discussed in the preceding para-
`graph. Barrier layer 62, may include TiN, TaN. Ti, la, and the
`and composition of mat er, means, methods and steps
`
`
`invention, processes, machines, manufacture, compositions
`aluminum, tungsten, and the ltke, and has a low melting
`ofmatter means methods or steps presently existing or later
`temperatue so that it can be re-flowed to improve the gap-
`fil.l.i.ng a.h.i
`The fo.rina.tj_on methods of r_e-Flow layer 627, mhedev
`ineluele\eD,P¥D,MQCV1D,andt+heli«ke.In
`-
`-
`-
`-
`-
`-
`
`S1.'€‘p‘S,I'e-HOW 3 is‘re-flowed.
`the present invention. Accordingly, the appended claims are
`FIG. 10 illustrates the removal of excess metal—layers 60
` wJNWmomssor intended to inehide within their seo.pe sueh processes
`
` ''. " '
`
`D54
`',
`'efmatter,riieans,
`aiereiiroved,ms as 1'6fi'aIi'd260, a'n'd‘meta'l
`ou methods, or steps.
`layers 1'62 and'2'62, respectively. The gateso and
`What is claimed‘is:
`PMOS 202 are thus formed. FIG. 11 illustrates a structure
`1. A semiconductor structure comprising:
`a£terthefor£nat—i9nofILD10—ai4dcontacts7-2.
`asemiconductorsubst-rate;
`Tlteeworkfuiict-ion-of-N-M(' )Sdev"rce1'02-ismai1Ilydeter-
` ,Wmmmthefim
`mined'by metal'layer 132. In the front-end-of-processes, ther-
`gate comprises:
`mal budgets (such as a source/drain activation) are applied.
`a first high-k dielectric over the semiconductor sub-
`A,s_a result, high-k dielectizic
`1.24_a.nd 1.26_a.i:e inter-
`stizateg
`
`65
`
`Pag6T70fT9
`
`Iw94441c4;oo4o4343_
`
`Page 17 of 19
`
`

`
`US 8,436,660 B7
`
`
`
`5
`
`i
`ast5CU1id‘l1'ig'li-ls
`wherein the irst and the second h—igl1-k dlelectrics
`strate;
`
`a&fimeml ,
`whereinthefirsta-ndt-lieseeendhig-l1—l\d-ieleetrie
`wherein the irst metal layer has a thickness great
`comprise different materials;
`enough for dominating a work-function of the first
`a first metal laver over the second high-k dielectric
`M-QS—deV-ie;anel
`W-laereinthefirstmetallayerhasathieknessgreat
`
`
`‘V-' v-"-
`_ "-,
`‘V-'
`-'
`In.’
`'. "','=,v'v|' i '-Vv
`the first and tie second metal layers comprise differ-
`device and wherein the first metal layer has amid-gap
`l0
`.
`1
`.
`1
`“Lgrkfi
`.
`.
`amhsfiwrlm«ahem
`second iiietaflayer; and
`a tlTlI"Cl nietaflaver over the second nietaflaver, wherein
`
`
`and wherein the second gate comprises:
`i
`a PMUS device comprising a second gate, wherein the
`a third high-k dielectric over the semiconductor sub-
`second gate comprises:
`mam,wheemmet
`same
`’..
`.
`’
`-
`’
`’
`the second high-k dielectric and have substantially a 29
`
`didRmemHTmmmi
`the other of the first high-k dielectric and the second
`
`h.i,g.h-e-,-,,-,_,__=e_-,-
`en -2.,
`_ ,_,f
`aflnmmmmawamednmmgh-k -kfiekmh,
`Whereln the tlfird metatlayer and the first meta1'1ayer
`wherein the second iiietaflayer in the second gate has
`comprise same materials wherein a combined thick-
`-.;
`...
`--.-=_;-
` -,-.e-en:-.
`‘
`'
`‘ " “
`" ‘
`‘
`‘
`‘
`‘
`‘ i
`"' ’ “ "
`thethirdmetal layer overthe secondmetal’layer;
`lined thickness Of ‘fielectrlc 13Ye’5 belVVeen me ms‘
`wherein the third metal laver further comprises a fourth
`metal laver and the semiconductor substrate; and
`meal Layer 13 a,,~m g 8t fer dam;
`HafiUgfidW0TkfuTETi.0.n0flheSeCOndM6Sd.eViCe,a U b ~ 1 , h f h 1 1 , d 1
`
`
`
`
`
`
`
`
`
`ent materials, and’the mm meta layer Wther c0m-
`Fjfflner 1:::r}_ 0‘er ih: bzlflermleta
`av]er’ Lb: metal
`prises a sixth metal layer having a thickness great
`‘.
`'
`‘
`‘
`.
`.
`.
`re—lhrw- .
` second
`M98
`.
`.
`.
`.
`9. The semiconductor structure of clami 8, wherein the
`i
`deviee, ,
`.
`,
`
`
`mmainerdm-flowlayawerfimbahierlaymsssmmldgalefilfijmrammffiseéml add.i.ti.o.na.l layer
`I
`a
`g
`5
`wherein the metal re-flow layer 1S conhgured to be
`,
`r_e_flOWa_b_]_e_
`wherein the additional metal'layer is formed of a same mate-
`E gm, ‘gm; f; qajm J, W13 gem 143 g gm
`2.1:}, E ‘gm; 6,3361“ it
`rial as and has a thickness less than the first metal laver.
`
`
` '' ' 5 ' . ' lam—8, wherein the
`
`
`is a l’lVfOS device.
`40 my gate fmTh'eT CUITIPTTSES 3 P_5lY3fliC0_n 1357375€m
`3. The semiconductor structure of claim 1 wherein the first
`firSt and the SeCOI1d metal 1aVe1‘S and Whefeifl the SeC0I1d gate
`
`
`
`s'tn:ret1:rre of claim 8, wherein the
`nrst metal'layer and the second metal'layer are flat layers, and
`of silicon.
`4. The semiconductor structure of claim 2 wherein the 45 wherein the third metal layer comprises sub—layers compris-
`.-,,e-e -.L-
`»
`e
`-, -,, -, --,
`-, - ,5--2-.2. _: :-e . --,
`-,
`-
`.-- sale" 25- 5-.
`;-e . 92.:
`25- 5-. h.i-glliert-ha-nt-he
`
`prising La.
`I2. he semiconductor structure of c aim 8, wherein the
`5. The semiconductor structure of claim 1. wherein the
`first and the third metal lavers have thicknesses ofgreater than
`
`
`
`
`he semicondmor sfiture of c aim 8, wherein the
`T3.
`metal’layer has a thickness less than a thickness required‘f0r
`second high-k dielectric comprises La and has a thickness of
`dominating a work function of the second MOS device and
`heJv\Leenah_0JJIO_’%iuJJaJ1da]1oiJI’%mJJ,ai1dml1eteJJJflJe
`wheLe_int]Jefi;Et]J_andt]JefirstuJetaJlayersc.om_pi;isesan1e
`55 =_:-==-
`: =-;;-:-~e--:--
`' =--a--=_
` .
`
`La.
`m structure of claim 1, wherein the
`14. The semiconductor structure of claim 8, wherein the
`second and the tl‘TlI'(l metaflavers have tlficknesses less than a
`fi.rst_meIa]_laver_co.m,p.i:i ses a_mater_ials
` s of_the first
`
`7.T‘lrese1InCoIrd'Lic1orstr'u'Cture 0‘fC‘la'l'I1il, wheI'ei'iitli'ei'i'rst UU biiiations tliereof.
`gate further comprises a seventh metal'layer over the second
`1'5. The semiconductor structure of claim 8, wherein the
`metal laver and wherein the seventh metal laver comprises
`third metal laver comprises a metal selected from the group
`same materials—as—the
`essentially of W, Ru, Mo, and wmMm
`
`
`a semiconductor substrate;
`an Nl\/IOS device comprising a first gate. wherein the first
`
`65
`
`thereof.
`1'6. A semiconductor structure comprising:
`a semiconductor substrate;
`
`
`
`
`
`.' ' ' .
`
`Pag6I80fT9
`
`Nv94441c4;oo4o4349_
`
`Page 18 of 19
`
`

`
`US 8,436,660 B7
`
`L]
`a s -Ldi ,
`Wl1ere1n the nrst and the second'h‘1gh-k dielectrics com-
`prise different materials‘
`
` ' fune-
`non;
`a polvsilicon 1aVer over the first metal 1aVer;
`E, Secmgd mm] ]a¥e,1g,,emge1Qg1§.S hm; layer and
`a-t-hirdmetalerver-t-he-
`layer furfher comprising a fourfh metal'layer with a work 10
`function close to a Valence band of silicon. a barrier layer
`
`5
`
` .
`17. The semiconductor structure of claim 16 wherein the 15
`firsLme1aJ1averisfla1,_andWhetejn_these.c(md_meta]1a;Ler
`1
`.1111]
`11 I 1.11
`'1.‘
`
`
`*
`
`=5
`
`PageI9ofT9
`
`.*
`
`*
`
`*
`
`Page 19 of 19