UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`MICRON TECHNOLOGY, INC.
`Petitioner
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC
`Patent Owner
`
`________________________
`
`Case IPR. No. Unassigned
`U.S. Patent No. 6,233,181
`Title: SEMICONDUCTOR MEMORY DEVICE
`WITH IMPROVED FLEXIBLE REDUNDANCY SCHEME
`________________________
`
`
`
`Petition For Inter Partes Review of U.S. Patent No. 6,233,181 Under
`35 U.S.C §§ 311-319 and 37 C.F.R. §§ 42.1-.80, 42.100-.123
`
`
`
`
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
`
`TABLE OF CONTENTS
`
`Page
`
`INTRODUCTION ........................................................................................... 1
`
`REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW ........ 1
`
`2.1. Grounds for Standing (37 C.F.R. § 42.104(a)) ..................................... 1
`
`2.2. Notice of Lead and Backup Counsel and Service Information ............. 1
`
`2.3. Notice of Real-Parties-in-Interest (37 C.F.R. § 42.8(b)(1)) .................. 2
`
`2.4. Notice of Related Matters (37 C.F.R. § 42.8(b)(2)) .............................. 2
`
`2.5. Fee for Inter Partes Review .................................................................. 4
`
`2.6. Proof of Service ..................................................................................... 4
`
`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`(§ 42.104(B)) ................................................................................................... 4
`
`OVERVIEW OF THE 181 PATENT .............................................................. 6
`
`181 PATENT PROSECUTION HISTORY .................................................... 9
`
`CLAIM CONSTRUCTION .......................................................................... 11
`
`6.1. Applicable Law ................................................................................... 11
`
`6.2. Construction of Claim Terms .............................................................. 12
`
`6.2.1. “word lines” (claims 1-7) ..........................................................12
`6.2.2. “spare memory cells” (claims 1-7) ...........................................13
`6.2.3. “sense amplifier bands” (claims 3 and 5) .................................14
`PERSON HAVING ORDINARY SKILL IN THE ART ............................. 15
`
`DESCRIPTION OF THE PRIOR ART ........................................................ 16
`
`8.1. U.S. Patent No. 5,487,040 (“Sukegawa”) ........................................... 16
`
`8.2. U.S. Patent No. 4,967,397 (“Walck”) ................................................. 19
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`
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`1.
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`2.
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`3.
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`4.
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`5.
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`6.
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`7.
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`8.
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`8.3. Betty Prince, Semiconductor Memories (2d ed. 1992) ....................... 20
`
`8.4. U.S. Patent No. 5,355,339 (“Oh”) ....................................................... 20
`
`9.
`
`GROUND #1: CLAIMS 1-2 AND 6 OF THE 181 PATENT ARE
`UNPATENTABLE AS OBVIOUS OVER SUKEGAWA ........................... 21
`
`9.1. Claim 1 is obvious over Sukegawa ..................................................... 21
`
`9.1.1. [1.P] A semiconductor memory device, comprising: ...............22
`9.1.2. [1.1a] a plurality of first memory blocks ..................................22
`9.1.3. [1.1b] each having a plurality of first normal memory
`cells arranged in a matrix of rows and columns, ......................24
`9.1.4. [1.1c] each of said plurality of first memory blocks
`including word lines provided corresponding to said
`rows, respectively,.....................................................................28
`9.1.5. [1.1d] and the first memory blocks aligned in the column
`direction; and .............................................................................28
`9.1.6. [1.2a] a plurality of first spare memory cells arranged in a
`matrix of rows and columns in a particular one of said
`plurality of first memory blocks, ..............................................30
`9.1.7. [1.2b] each row of said plurality of first spare memory
`cells being capable of replacing a defective row including
`a defective first normal memory cell in said plurality of
`first memory blocks. .................................................................31
`9.2. Claim 2 is obvious over Sukegawa ..................................................... 32
`
`9.2.1. [2.P] The semiconductor memory device as recited in
`claim 1, further comprising: ......................................................32
`9.2.2. [2.1a] a plurality of second memory blocks arranged
`alternatively with said plurality of first memory blocks
`along the column direction, .......................................................32
`9.2.3. [2.1b] the second memory blocks each having a plurality
`of second normal memory cells arranged in a matrix of
`rows and columns; and ..............................................................33
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`9.2.4. [2.2a] a plurality of second spare memory cells arranged
`in a matrix of rows and columns in a particular one of
`said plurality of second memory blocks, ..................................34
`9.2.5. [2.2b] each row of said plurality of second spare memory
`cells being capable of replacing a defective row including
`a defective second normal memory cell in said plurality
`of second memory blocks. ........................................................35
`9.3. Claim 6 is obvious over Sukegawa ..................................................... 36
`
`9.3.1. [6.P] The semiconductor memory device as recited in
`claim 1, wherein ........................................................................36
`9.3.2. [6.1] the first normal memory cells and the first spare
`memory cells are arranged alignedly in the column
`direction. ...................................................................................36
`10. GROUND #2: CLAIM 3 OF THE 181 PATENT IS
`UNPATENTABLE AS OBVIOUS OVER SUKEGAWA IN VIEW
`OF PRINCE ................................................................................................... 39
`
`10.1. [3.P] The semiconductor memory device as recited in claim 2,
`further comprising ............................................................................... 39
`
`10.1. [3.1] a plurality of sense amplifier bands provided between each
`of said plurality of first memory blocks and each of said second
`memory blocks, ................................................................................... 39
`
`10.2. [3.2] and shared by adjacent memory blocks in the column
`direction for sensing and amplifying data in each column of the
`adjacent memory block including a selected memory cell when
`activated. .............................................................................................. 42
`
`10.3. Motivation to Combine Prince and Sukegawa .................................... 43
`
`11. GROUND #3: CLAIM 4 OF THE 181 PATENT IS
`UNPATENTABLE AS OBVIOUS OVER SUKEGAWA IN VIEW
`OF PRINCE ................................................................................................... 44
`
`11.1. [4.P] The semiconductor memory device as recited in claim 2,
`wherein ................................................................................................ 44
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`11.2. [4.1] the first memory blocks and the second memory blocks
`share a circuit related to a memory cell selection operation. .............. 44
`
`11.3. Motivation to Combine Prince and Sukegawa .................................... 46
`
`12. GROUND #4: CLAIM 5 OF THE 181 PATENT IS
`UNPATENTABLE AS OBVIOUS OVER SUKEGAWA IN VIEW
`OF WALCK ................................................................................................... 47
`
`12.1. [5.P] The semiconductor memory device as recited in claim 3,
`wherein ................................................................................................ 47
`
`12.2. [5.1] said plurality of first memory blocks, said plurality of
`second memory blocks and said plurality of sense amplifier
`bands form a first memory array, and ................................................. 47
`
`12.3. [5.2] said semiconductor memory device further comprises: a
`second memory array having a same arrangement as the first
`memory array; and............................................................................... 48
`
`12.4. [5.3a] control circuitry for driving one memory block from the
`first and second memory arrays into a selected state in a normal
`operation mode, ................................................................................... 49
`
`12.5. [5.3b] and for simultaneously driving a prescribed number of
`memory blocks from each of said first and second memory
`arrays into a selected state in a particular operation mode. ................ 50
`
`12.6. Motivation to Combine Sukegawa and Walck ................................... 51
`
`13. GROUND #5: CLAIM 7 OF THE 181 PATENT IS
`UNPATENTABLE AS OBVIOUS OVER SUKEGAWA IN VIEW
`OF OH............................................................................................................ 52
`
`13.1. [7.P] The semiconductor memory device as recited in claim 1,
`wherein ................................................................................................ 53
`
`13.2. [7.1] the first memory blocks other than said particular one has
`no first spare memory cells. ................................................................ 53
`
`13.3. Motivation to Combine Sukegawa and Oh ......................................... 56
`
`14. CONCLUSION .............................................................................................. 56
`
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`Exhibit List
`
`Description
`
`U.S. Patent No. 6,233,181 (“the 181 Patent”)
`
`File History for U.S. Patent No. 6,233,181
`
`U.S. Patent No. 5,761,138 (“Lee”)
`
`U.S. Patent No. 5,892,718 (“Yamada”)
`
`U.S. Patent No. 5,487,040 (“Sukegawa”)
`
`U.S. Patent No. 4,967,397 (“Walck”)
`
`Declaration of Dr. R. Jacob Baker (“Baker Decl.”)
`
`Curriculum Vitae of Dr. R. Jacob Baker
`
`Excerpts from Betty Prince, Semiconductor Memories (2d ed.
`1992) (“Prince”)
`
`U.S. Patent No. 5,355,339 (“Oh”)
`
`Micron
`Exhibit #
`
`MICRON-
`1001
`
`MICRON-
`1002
`
`MICRON-
`1003
`
`MICRON-
`1004
`
`MICRON-
`1005
`
`MICRON-
`1006
`
`MICRON-
`1007
`
`MICRON-
`1008
`
`MICRON-
`1009
`
`MICRON-
`1010
`
`
`
`
`
`-v-
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
`
`1. INTRODUCTION
`Pursuant to 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42.100, Micron
`
`Technology, Inc. (“Petitioner”) hereby petitions the Patent Trial and Appeal Board
`
`to institute an inter partes review of claims 1-7 of U.S Patent No. 6,233,181, titled
`
`“Semiconductor Memory Device With Improved Flexible Redundancy Scheme”
`
`(MICRON-1001, “the 181 Patent”), and cancel those claims as unpatentable.
`
`2. REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW
`2.1. Grounds for Standing (37 C.F.R. § 42.104(a))
`Petitioner certifies that the 181 Patent is available for inter partes review and
`
`that Petitioner is not barred or estopped from requesting inter partes review of the
`
`challenged claims of the 181 Patent on the grounds identified herein.
`
`2.2. Notice of Lead and Backup Counsel and Service Information
`Pursuant to 37 C.F.R. §§ 42.8(b)(3), 42.8(b)(4), and 42.10(a), Petitioner
`
`provides the following designation of Lead and Back-Up counsel.
`
`Lead Counsel
`Jeremy Jason Lang (Reg. No. 73604)
`(jason.lang@weil.com)
`
`Postal & Hand-Delivery Address:
`Weil, Gotshal & Manges LLP
`201 Redwood Shores Parkway
`Redwood Shores, CA 94065
`T: 650-802-3237; F: 650-802-3100
`
`Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney for the Petitioner is
`
`Back-Up Counsel
`Justin L. Constant (Reg. No. 66883)
`(justin.constant@weil.com)
`
`Postal & Hand-Delivery Address:
`Weil, Gotshal & Manges LLP
`700 Louisiana, Suite 1700
`Houston, TX 77002
`T: 713-546-5217; F: 713-224-9511
`
`attached.
`
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`2.3. Notice of Real-Parties-in-Interest (37 C.F.R. § 42.8(b)(1))
`Petitioner, Micron Technology, Inc., is the real-party-in-interest. No other
`
`parties exercised or could have exercised control over this petition; no other parties
`
`funded or directed this petition. See Office Patent Trial Practice Guide, 77 Fed.
`
`Reg. 48759-60.
`
`2.4. Notice of Related Matters (37 C.F.R. § 42.8(b)(2))
`Limestone has asserted the 181 Patent and U.S. Patent Nos. 5,805,504 (“the
`
`504 Patent”), 5,894,441 (“the 441 Patent”), 5,943,260 (“the 260 Patent”), and
`
`6,697,296 (“the 296 Patent”) (collectively, “the asserted patents”) against Micron
`
`in a co-pending litigation, Limestone Memory Sys. LLC v. Micron Tech. Inc., 8:15-
`
`cv-00278 (C.D. Cal.) (“Co-Pending Litigation”). Limestone has also asserted one
`
`or more of the asserted patents in the following actions: Limestone Memory Sys.
`
`LLC v. OCZ Storage Solutions, Inc., 8:15-cv-00658 (C.D. Cal.) (the 504, 441, 181
`
`and 296 Patents); Limestone Memory Sys. LLC v. PNY Techs., Inc., 8:15-cv-00656
`
`(C.D. Cal.) (the 260 Patent); Limestone Memory Sys. LLC v. Lenovo (US) Inc.,
`
`8:15-cv-00650 (C.D. Cal.) (the 504, 441, 260, 181, and 296 Patents); Limestone
`
`Memory Sys. LLC v. Kingston Tech. Co. Inc., 8:15-cv-00654 (C.D. Cal.) (the 504,
`
`441, 260, 181, and 296 Patents); Limestone Memory Sys. LLC v. Transcend Info.,
`
`Inc. (California), 8:15-cv-00657 (C.D. Cal.) (the 260 Patent); Limestone Memory
`
`Sys. LLC v. Acer America Corp., 8:15-cv-00653 (C.D. Cal.) (the 504, 441, 260,
`
`-2-
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`181, and 296 Patents); Limestone Memory Sys. LLC v. Dell Inc., 8:15-cv-00648
`
`(C.D. Cal.) (the 504, 441, 260, 181, and 296 Patents); Limestone Memory Sys. LLC
`
`v. Hewlett-Packard Co., 8:15-cv-00652 (C.D. Cal.) (the 504, 441, 260, 181, and
`
`296 Patents); and Limestone Memory Sys. LLC v. Apple Inc., 8:15-cv-01274 (C.D.
`
`Cal.) (the 504, 441, 181, and 296 Patents).
`
`In addition to this Petition, Petitioner is filing petitions for inter partes
`
`review of each asserted patent in the Co-Pending Litigation: Petition for Inter
`
`Partes Review of U.S. Patent No. 5,805,504, IPR2015-Unassigned (to be filed
`
`concurrently); Petition for Inter Partes Review of U.S. Patent No. 5,894,441,
`
`IPR2015-Unassigned (to be filed concurrently); Petition for Inter Partes Review of
`
`U.S. Patent No. 5,943,260, IPR2015-Unassigned (to be filed concurrently); and
`
`Petition for Inter Partes Review of U.S. Patent No. 6,697,296, IPR2015-
`
`Unassigned (to be filed concurrently).
`
`The 181 Patent claims priority to foreign patent applications JP-10-160466
`
`and JP-10-293421. The 181 Patent does not claim priority to any other U.S. patent
`
`applications. According to USPTO records, and to the best of Petitioner’s
`
`knowledge, the following U.S applications and patents claim priority to the
`
`application that led to the issuance of the 181 Patent: U.S. Patent App. No.
`
`09/798,944, filed on March 06, 2001, now U.S. Patent No. 6,449,199 (expired due
`
`to non-payment of maintenance fees); U.S. Patent App. No. 10/229,001, filed on
`
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`August 28, 2002, now U.S. Patent No. 6,545,931; and U.S. Patent App. No.
`
`10/387,573, filed on March 14, 2003, now U.S. Patent No. 6,678,195. To the best
`
`of Petitioner’s knowledge, the U.S. patents that claim priority to the 181 Patent
`
`have not been asserted in litigation and are not the subject of any co-pending
`
`USPTO proceedings.
`
`2.5. Fee for Inter Partes Review
`The Director is authorized to charge the fee specified by 37 C.F.R. §
`
`42.15(a), and any other required fees, to Deposit Account No. 506499.
`
`2.6. Proof of Service
`Proof of service of this petition on the patent owner at the correspondence
`
`address of record for the 181 Patent is attached.
`
`3. IDENTIFICATION OF CLAIMS BEING CHALLENGED (§ 42.104(B))
`Ground #1: Claims 1-2 and 6 of the 181 Patent are invalid under (pre-AIA)
`
`35 U.S.C. § 103(a) on the ground that they are obvious over U.S. Patent No.
`
`5,487,040, to Sukegawa et al. (“Sukegawa”), entitled “Semiconductor Memory
`
`Device and Defective Memory Cell Repair Circuit,” issued on January 23, 1996.
`
`Sukegawa is attached as MICRON-1005. This ground is explained below and is
`
`supported by the Declaration of Dr. R. Jacob Baker (MICRON-1007, “Baker
`
`Decl.”).
`
`Ground #2: Claim 3 of the 181 Patent is invalid under (pre-AIA) 35 U.S.C.
`
`§ 103(a) on the ground that it is obvious over Sukegawa in view of Betty Prince,
`
`-4-
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`Semiconductor Memories (2d ed. 1992) (“Prince”). The excerpts produced at
`
`MICRON-1009 are from a copy of the Prince textbook that was stamped by the
`
`Library of Congress on March 26, 1992. This ground is explained below and is
`
`supported by the Baker Decl.
`
`Ground # 3: Claim 4 of the 181 Patent is invalid under (pre-AIA) 35 U.S.C.
`
`§ 103(a) on the ground that it is obvious over Sukegawa in view of Prince. This
`
`ground is explained below and is supported by the Baker Decl.
`
`Ground # 4: Claim 5 of the 181 Patent is invalid under (pre-AIA) 35 U.S.C.
`
`§ 103(a) on the ground that it is obvious over Sukegawa in view of U.S. Patent No.
`
`4,967,397, to Walck (“Walck”), entitled “Dynamic RAM Controller,” filed with
`
`the USPTO on May 15, 1989, issued October 30, 1990. Walck is attached as
`
`MICRON-1006. This ground is explained below and is supported by the Baker
`
`Decl.
`
`Ground #5: Claim 7 of the 181 Patent is invalid under (pre-AIA) 35 U.S.C.
`
`§ 103(a) on the ground that it is obvious over Sukegawa in view of U.S. Patent No.
`
`5,355,339, to Oh et al. (“Oh”), entitled “Row Redundancy Circuit of a
`
`Semiconductor Memory Device,” filed with the USPTO on July 13, 1993, issued
`
`October 11, 1994. Oh is attached as MICRON-1010. This ground is explained
`
`below and is supported by the Baker Decl.
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`4. OVERVIEW OF THE 181 PATENT
`The 181 Patent was filed on February 17, 1999, and claims priority to two
`
`Japanese patent applications, the earliest of which was filed on June 9, 1998. The
`
`181 Patent issued on May 15, 2001. The 181 Patent relates generally to a
`
`semiconductor memory device having memory arrays that are further subdivided
`
`into a plurality of memory blocks, which themselves consist of a matrix of rows
`
`and columns of memory cells. MICRON-1001, 181 Patent at 1:7-9; MICRON-
`
`1007, Baker Decl. ¶¶ 33-41. More particularly, the 181 Patent concerns the
`
`replacement of defective memory cells in a memory block with spare memory
`
`cells. As was known in the art, when a memory cell becomes defective, the
`
`memory cell can be replaced with redundant—or spare—memory cells. See, e.g.,
`
`MICRON-1001, 181 Patent at 1:15-18 (describing the background of the art and
`
`stating that “a defective memory cell is replaced with a spare memory cell in order
`
`to equivalently repair the defective memory cell to raise the yield of the products”).
`
`The 181 Patent alleges, however, that prior art techniques provided spare
`
`word lines (extra rows of spare memory cells) or spare column/bit lines (extra
`
`columns of spare memory cells) in each memory block. MICRON-1001, 181
`
`Patent at 1:28-38, 3:18-26; MICRON-1007, Baker Decl. ¶¶ 33-34. According to
`
`the 181 Patent, providing spare memory cells in each memory block resulted in
`
`inefficient use of the spare cells. MICRON-1001, 181 Patent at 3:58-67; id. at 4:1-
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`8. The 181 Patent purports to solve this alleged problem by disclosing a
`
`semiconductor device that has the ability to use spare memory cells in one memory
`
`block to replace defective memory cells in other blocks. MICRON-1001, 181
`
`Patent at Abstract (“A spare memory array having spare memory cells common to
`
`a plurality of normal sub-arrays having a plurality of normal memory cells is
`
`provided. A spare line in the spare array can replace a defective line in the
`
`plurality of normal sub-array. The defective line is efficiently repaired by
`
`replacement in an array divided into blocks or sub-arrays.”). See also MICRON-
`
`1007, Baker Decl. ¶ 35.
`
`The claims are directed to an embodiment of the alleged invention that
`
`concerns repairing defective memory cells in a particular memory block within a
`
`group of memory blocks aligned in the column (vertical) direction. This is the
`
`third embodiment described in the 181 Patent, which is depicted in Figure 9 and
`
`described at 16:12-17:25. Figure 9 is reproduced below:
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`MICRON-1001, 181 Patent at Figure 9 (annotated).
`
`
`
`The memory array in Figure 9 consists of row blocks RBX#0 to RBX#m,
`
`
`
`which are aligned in the column (vertical) direction. MICRON-1001, 181 Patent at
`
`16:14-16. The row blocks RBX#1 to RBX#m are formed by “normal memory
`
`sub-arrays MA#1 to MA#m,” which consist of normal memory cells arranged in a
`
`matrix of rows and columns. Id. at 16:16-19.
`
`Row block RBX#0 includes a normal memory sub-array MA#0 with
`
`memory cells arranged in a matrix of columns and a spare array SPX# having
`
`spare memory cells arranged in a plurality of rows and sharing the columns with
`
`normal memory sub-array MA#0. Id. at 16:19-24. The “plurality of spare rows
`
`(spare word lines) included in spare array SPX# can replace defective normal word
`
`lines included in normal memory sub-arrays MA#0 to MA#m.” Id. at 16:24-27;
`
`see also id. at 16:31-33 (“In the configuration shown in FIG. 9, spare array SPX#
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`is provided in common to normal memory sub-arrays MA#0 to MA#m.”). The
`
`181 Patent alleges that allowing the spare rows in SPX# to replace the memory
`
`cells in MA#0 to MA#m improves the efficiency with which the spare lines are
`
`used and simplifies the control operations when replacing defective memory cells.
`
`See, e.g., id. at 16:33-39, 17:2-14.
`
`5. 181 PATENT PROSECUTION HISTORY
`The application that led to the issuance of the 181 Patent was originally filed
`
`with 20 claims. MICRON-1002, 181 Patent File History, 2-17-1999 Original
`
`Claims at .140-.147. Subsequently, following a restriction requirement, the
`
`Applicant elected the species of Figure 9, which corresponded to original claims 4-
`
`6. Id., 2-10-2000 Response to Election Requirement at .452.
`
`The Examiner subsequently issued a non-final rejection finding claims 1-3
`
`anticipated by the disclosure of two prior art references: (1) Figures 3A and 3B of
`
`U.S. Patent No. 5,761,138 (“Lee”) (MICRON-1003); and (2) Figure 3 of U.S.
`
`Patent No. 5,892,718 (“Yamada”) (MICRON-1004). Id., 4-12-2000 Non-Final
`
`Rejection at .456.
`
`In a 10-11-2000 Amendment, the Applicant made several amendments to the
`
`claims. Notably, the Applicant amended claim 1 to require that the plurality of
`
`first memory blocks were aligned in the column direction. See id., 10-11-2000
`
`Amendment at .460-.461. The Applicant also added dependent claims 21-24. For
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`-9-
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
`
`reference, the following is a table listing the original claim numbers and issued
`
`claim numbers:
`
`Original Claim Issued Claim
`4
`1
`5
`2
`6
`3
`21
`6
`22
`7
`23
`4
`24
`5
`
`For ease of reference, this Petition refers to the claims by their issued claim
`
`
`
`number. In the remarks, the Applicant asserted that claim 1 “recites that (a) the
`
`first memory blocks are aligned in the column direction, and (b) each row of the
`
`plurality of first spare memory cells are [sic] capable of replacing a defective row
`
`including a defective normal memory cell in the plurality of first memory blocks.”
`
`Id. at .464 (underline in original). The Applicant further stated that these features
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`are shown in Figure 9. Id. With respect to Lee (MICRON-1003), the Applicant
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`argued that Figures 3A and 3B disclosed a redundant memory cell array that could
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`replace memory cells in a plurality of arrays aligned in the row direction, but did
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`not disclose redundant memory cells that could replace memory cells in a plurality
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`of arrays aligned in the column direction. Id. at .464-.465. With respect to
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`Yamada (MICRON-1004), the Applicant argued that claim 1 requires “‘a plurality
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`of first spare memory cells arranged in a matrix of rows and columns in a
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`particular one of said plurality of first memory blocks,’” explaining that Figure 9
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`“shows spare array SPX# arranged in a particular one (normal memory sub-array
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`MA#0) of the first memory blocks (MA#1-MA#m).” Id. at .465. The Applicant
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`further argued that Yamada did not teach an array of spare memory cells within a
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`particular one of the first memory blocks and further did not teach memory blocks
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`aligned in the column direction. Id. at .465-.467. Subsequently, the Examiner
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`allowed claims 1-7. Id., 1-16-2011 Notice of Allowability at .473.
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`6. CLAIM CONSTRUCTION1
`6.1. Applicable Law
`A claim subject to inter partes review is given the “broadest reasonable
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`construction in light of the specification of the patent in which it appears.”2 37
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`1 Petitioner expressly reserves the right to challenge in district court litigation one
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`or more claims (and claim terms) of the 181 Patent for failure to satisfy the
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`requirements of 35 U.S.C § 112, which cannot be raised in these proceedings. See
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`35 U.S.C. § 311(b). Nothing in this Petition, or the constructions provided herein,
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`shall be construed as a waiver of such challenge, or agreement that the
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`requirements of 35 U.S.C. § 112 are met for any claim of the 181 Patent.
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`2 The district court, in contrast, affords a claim term its “ordinary and customary
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`meaning . . . to a person of ordinary skill in the art in question at the time of the
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`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
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`C.F.R. § 42.100(b).
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` Any ambiguity regarding the “broadest reasonable
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`construction” of a claim term is resolved in favor of the broader construction
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`absent amendment by the patent owner. Final Rule, 77 Fed. Reg. 48680, 48699
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`(Aug. 14, 2012).
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`6.2. Construction of Claim Terms
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`All claim terms not specifically addressed in this Section have been
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`accorded their broadest reasonable interpretation as understood by a person of
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`ordinary skill in the art and consistent with the specification of the 181 Patent.
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`Petitioner respectfully submits that the following terms shall be construed for this
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`IPR:
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`6.2.1. “word lines” (claims 1-7)
` The term “word lines” is a limitation of claim 1 of the 181 Patent, and
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`thus is also a limitation of dependent claims 2-7. Specifically, claim 1 requires “a
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`plurality of first memory blocks each having a plurality of first normal memory
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`cells arranged in a matrix of rows and columns, each of said plurality of first
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`memory blocks including word lines provided corresponding to said rows.”
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`invention.” Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005).
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`Petitioner expressly reserves the right to argue different or additional claim
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`construction positions under this standard in district court.
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`MICRON-1001, 181 Patent at Claim 1. As Dr. Baker opines, in the semiconductor
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`industry, the terms “row line” and “word line” were interchangeable and were well
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`understood to refer to conductive materials that run horizontally through a memory
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`device and connects multiple memory cells into a physical row. See MICRON-
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`1007, Baker Decl. ¶ 55 (citing MICRON-1009, Prince3 at .024, .029).
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`Thus, a person of ordinary skill in the art would have understood the plain
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`and ordinary meaning of this term in the context of the 181 Patent to mean a
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`“conductive materials that run horizontally through a memory device that
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`connect memory cells in a physical row. Id. at ¶ 56.
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`6.2.2. “spare memory cells” (claims 1-7)
`The term “spare memory cells” is a limitation of independent claim 1 of the
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`181 Patent, and thus is also a limitation of dependent claims 2-7. Specifically,
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`claim 1 requires “a plurality of first spare memory cells arranged in a matrix of
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`rows and columns in a particular one of said plurality of first memory blocks.”
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`3 As Dr. Baker explains, the Prince textbook was a well-known resource in the
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`field of semiconductor memory devices. See MICRON-1007, Baker Decl. ¶ 23.
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`The excerpts produced at MICRON-1009 are from a copy of the textbook that was
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`stamped by the Library of Congress on March 26, 1992. See MICRON-1009,
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`Prince at .005.
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`MICRON-1001, 181 Patent at Claim 1. The 181 Patent describes spare memory
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`cells as memory cells that are capable of replacing defective normal memory cells:
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`Row block RBX0 includes a normal memory sub-array MA#0 having
`normal memory cells arranged in a matrix of rows and columns, and a
`spare array SPX# having spare memory cells arranged in a plurality of
`rows and sharing the columns with normal memory sub-array MA#0.
`The plurality of spare rows (spare word lines) included in spare array
`SPX# can replace defective normal word lines included in normal
`memory sub-arrays MA#0 to MA#m.
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`MICRON-1001, 181 Patent at 16:19-27. Thus, a person of ordinary skill in the art
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`would have understood the plain and ordinary meaning of this term in the context
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`of the 181 Patent to mean “memory cells capable of replacing defective memory
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`cells.” MICRON-1007, Baker Decl. ¶¶ 57-58.
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`6.2.3. “sense amplifier bands” (claims 3 and 5)
`The term “sense amplifier band(s)” is a limitation of dependent claim 3 of
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`the 181 Patent, and thus is also a limitation of dependent 5 (which depends from
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`claim 3). Specifically, claim 3 requires “a plurality of sense amplifier bands
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`provided between each of said plurality of first memory blocks and each of said
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`second memory blocks, and shared by adjacent memory blocks in the column
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`direction for sensing and amplifying data in each column of the adjacent memory
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`block including a selected memory cell when activated.” MICRON-1001, 181
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`Patent at Claim 3. When describing the embodiment of Figure 9 of the 181 Patent,
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`the 181 Patent specification discusses sense amplifiers but does not expressly
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`define the term “sense amplifier band.” See id. at 17:10-14.
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`The specification does make clear, however, that “band” refers to a plurality
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`of sense amplifiers along the horizontal direction of a block (either on one end of
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`the block, top or bottom, or in between two blocks). See, e.g., MICRON-1001,
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`181 Patent at Figures 11, 14, 15, 20, 17:42-48. They are in the horizontal direction
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`because they reside along the termination points of bit lines (which run orthogonal
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`to the horizontal direction) to sense and restore contents of memory cells. See
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`MICRON-1007, Baker Decl. ¶¶ 59-60.
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`As Dr. Baker opines, the term “sense amplifier” was understood to a person
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`of ordinary skill in the art to mean an amplifier that senses the contents of memory
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`cells and restores (amplifies) them to full levels. See MICRON-1007, Baker Decl.
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`¶ 60 (citing MICRON-1009, Prince at .037). Thus, a person of ordinary skill in the
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`art would have understood the plain and ordinary meaning of this term in the
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`context of the 181 Patent to mean “amplifiers along the horizontal direction that
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`sense the contents of memory cells and restore (amplify) them to full levels.”
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`Id. at ¶ 61.
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`7. PERSON HAVING ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art with respect to the technology described
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`in the 181 Patent would be a person with a Bachelor of Science degree in electrical
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`Petition for Inter Partes R