United States Patent [19J
`Yamada
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`US005892718A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,892,718
`Apr. 6, 1999
`
`[54] SEMICONDUCTOR MEMORY DEVICE
`HAVING A REDUNDANCY FUNCTION
`
`3-59895
`7-65595
`
`3/1991
`3/1995
`
`Japan .
`Japan .
`
`[75]
`
`Inventor: Yukinori Yamada, Tokyo, Japan
`
`[73] Assignee: NEC Corporation, Tokyo, Japan
`
`[21] Appl. No.: 934,539
`
`[22]
`
`Filed:
`
`Sep. 22, 1997
`
`[30]
`
`Foreign Application Priority Data
`
`Sep. 20, 1996
`
`[JP]
`
`Japan .................................... 8-250245
`
`Int. Cl.6
`....................................................... GllC 7/00
`[51]
`[52] U.S. Cl. .................. 365/200; 365/230.03; 365/225.7
`[58] Field of Search ............................... 365/200, 230.03,
`365/225.7, 230.06
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,661,689
`
`8/1997 Shinkai ................................... 365/200
`
`FOREIGN PATENT DOCUMENTS
`
`3-58398
`
`3/1991
`
`Japan .
`
`Primary Examiner-Vu A Le
`Attorney, Agent, or Firm-Foley & Lardner
`
`[57]
`
`ABSTRACT
`
`A semiconductor memory device comprises memory cell
`blocks Ml-Mn disposed for respective 1/0 pads and a
`redundant memory cell block MR, a programmable circuit
`programmable based on a failed information for controlling
`transfer switches Tl and T2 to couple each of the 1/0 pads
`with corresponding memory cell block or with adjacent
`memory cell block by excepting a failed memory cell block
`and including the redundant memory cell block based on the
`failed information. In a roll call test mode, the 1/0 pads
`coupled with adjacent memory cell blocks output a fixed
`value regardless of data stored in the memory cell blocks to
`notify a failed memory cell block for facilitating failure
`analysis.
`
`7 Claims, 5 Drawing Sheets
`
`M1
`
`M2
`
`Mn
`
`MR
`
`1/02
`1/01
`MEMORY MEMORY
`CELL
`CELL
`BLOCK
`BLOCK
`
`I/On.
`MEMORY
`CELL
`BLOCK
`
`REDUNDANT
`MEMORY
`CELL
`BLOCK
`
`T2 (n-1)
`
`T2n
`
`20
`
`FUSE
`~H--+-+-<.Ju>-+--+-+-oV)--~~~>--<:r-0--+-+-+~~------iCONTROL
`BLOCK
`
`MICRON-1004.001
`
`

`
`U.S. Patent
`
`Apr. 6, 1999
`
`Sheet 1 of 5
`
`5,892,718
`
`FIG. 1
`PRIOR ART
`
`15 CLAMP CIRCUIT
`___ C_ ______________ ,
`
`'
`
`'
`
`TB
`
`D01
`
`1/0
`
`REDUN- RDS ROLL
`DANCY
`CALL
`i !
`DECODER
`DECODER
`YRD.__--;--.~~ --~~;- -y---~~~~--~~~-~~~
`
`N04
`
`;
`
`.
`
`RCE
`
`x(cid:173)
`DECODER
`
`ATD
`CIRCUIT
`
`ADDO
`
`16 READ CIRCUIT
`
`18
`
`19
`
`FIG. 2
`PRIOR ART
`
`14
`
`RDS
`
`TM "-'----+--+II
`
`YRD
`
`T9
`
`TlO
`
`17
`
`18
`
`MICRON-1004.002
`
`

`
`FIG. 3
`
`/10
`
`M1
`
`M2
`
`Mn
`
`MR
`
`1/02
`1/01
`MEMORY MEMORY
`CELL
`CELL
`BLOCK
`BLOCK
`
`REDUNDANT
`I/On
`MEMORY MEMORY
`CELL
`CELL
`BLOCK
`BLOCK
`
`T2 (n-1)
`
`T2n
`
`20
`
`~) I
`I •
`
`()'\.{)
`
`I CNJ
`
`I
`
`I •
`
`FUSE
`I CONTROL
`BLOCK
`~ --------~-----
`11 PROGRAMMABLE
`....L.---· Sin
`R1n
`CIRCUIT
`R2n j
`- - ----~~n )2 ROLL CALL CIRCUIT
`
`TM<}-~~~~--+-+-++~~~~~~-+-+-h
`
`Nn
`
`R22
`---~;~JWj-~~1-F\"~~~ ~~~~~-~-~~-- ---
`A2
`
`SE
`
`d •
`\JJ.
`•
`~
`~ ......
`~ = ......
`
`>
`"Cl
`!"'l
`~~
`'"""'
`\C
`\C
`\C
`
`'Jl =(cid:173)~
`~ .....
`N
`0 .....,
`Ul
`
`Ul
`....
`00
`\C
`N
`....
`......::.
`~
`00
`
`MICRON-1004.003
`
`

`
`U.S. Patent
`
`Apr. 6, 1999
`
`Sheet 3 of 5
`
`5,892,718
`
`FIG. 4
`
`20
`
`Sn
`
`FIG. 5
`
`21
`
`Rl R2 NAl
`
`NA2
`
`T3
`
`SENSE
`AMP.
`
`MICRON-1004.004
`
`

`
`FIG. 6
`
`WR1 WR2
`
`WR3
`
`WRn WRR
`
`Sl
`
`F2
`(
`)
`
`Nl
`
`I I!
`
`:TM=l
`
`---------------
`
`OE
`
`~ Sil
`
`Fn
`~ I ~Sn I FUSE
`S2 ~ CONTORL
`BLOCK
`I 11 ~N-----------·
`/N2
`R1n! n
`512
`------- -- --- - -------------------------- ----- - ---~~~~ 12ROLL
`: Sin
`R22
`1/01
`1/02 - - _ _ _ _
`CALL
`Dout
`Dout
`BLOCK 001
`CIRCUIT
`001
`o1 ncv
`
`I I!
`
`I/On
`
`1/01
`
`1/02 - - - - - - Y n,u~~'/t--1/0n
`
`011
`
`012
`
`Din
`
`d •
`\JJ.
`•
`~
`~ ......
`~ = ......
`
`>
`"Cl
`!"'l
`~~
`'"""'
`\C
`\C
`\C
`
`'Jl =(cid:173)~
`~ .....
`
`.i;;..
`0 .....,
`Ul
`
`Ul
`....
`00
`\C
`N
`....
`.....::.
`~
`00
`
`MICRON-1004.005
`
`

`
`U.S. Patent
`
`Apr. 6, 1999
`
`Sheet 5 of 5
`
`5,892,718
`
`FIG. 7
`
`22 Rl R2 NA4
`
`NA5
`
`T6
`
`DATA
`AMP.
`
`MICRON-1004.006
`
`

`
`5,892,718
`
`1
`SEMICONDUCTOR MEMORY DEVICE
`HAVING A REDUNDANCY FUNCTION
`
`BACKGROUND OF THE INVENTION
`
`35
`
`(a) Field of the Invention
`The present invention generally relates to a semiconduc(cid:173)
`tor memory device having a redundancy function and, more
`specifically, to a discriminating circuit provided in the
`semiconductor memory device for judging whether or not a
`redundancy function has been used to substitute for a failed
`memory block.
`(b) Description of the Related Art
`Recently, a semiconductor memory device is generally
`designed to include redundant memory cells for a redun(cid:173)
`dancy function to replace failed memory cells by the redun(cid:173)
`dant memory cells, thereby enhancing the product yield of
`the memory device with an increased storage capacity. Such
`a semiconductor memory device is often provided with a roll
`call circuit for discriminating whether or not the redundant 20
`memory cells have been used, for the purpose of failure
`analysis or product evaluation.
`FIG. 1 shows an example of a conventional roll call
`circuit, proposed in Patent Publication NO. JP-A-7(1995)-
`65595. The disclosed roll call circuit comprises a data output 25
`block DOl, a first read circuit 13 for reading data from a
`sense amplifier block, and a second read circuit 16 for
`reading the result of a roll call test. The data output block
`DOl amplifies data on a write/read bus line pair WRBT/
`WREN and outputs the amplified data through 1/0 pads. The 30
`first read circuit 13 receives data from the sense amplifier
`block (not illustrated) and outputs the data through the bus
`line pair WRBT/WRBN. The second read circuit 16 outputs
`the result of the roll call test to the bus line pair WRBT/
`WREN.
`The proposed roll call circuit further comprises a redun(cid:173)
`dancy decoder 17, an X-decoder 18 and a roll call decoder
`14. The redundancy decoder 17 receives through external
`pins Al-An (not-illustrated) address signals ADDl-ADDn,
`which are "High" or "Low" depending on "1" or "O" given
`to the external pins Al-An. The X-decoder 18 receives an
`address signal ADDO which is "High" or "Low" depending
`on the signal given to an external pin AO, the address signals
`ADDl-ADDn and a signal RDS output from the redun-
`dancy decoder 17. The roll call decoder 14 receives the
`signal RDS from the redundancy decoder 17, a signal YRD
`from an address transition detector ("ATD") 19 and a test
`mode signal TM for allowing the memory device enter into
`a test mode.
`The first read circuit 13 comprises a pair of N-channel
`transistors T20 and T21 and a NOR gate N04. The pair of
`n-channel transistors T20 and T21 function as transfer gates
`between a data line pair RBT/RBN from the sense amplifier
`block and the bus line pair WRBT/WRBN. The NOR gate
`N04 receives a signal RCE from the second read circuit 16
`and a signal BSLB at the inputs thereof, and supplies an
`output signal to the gate of the transistors T20 and T21.
`The second read circuit 16 comprises a NOR gate N03
`and a pair of N-channel transistors Tl8 and Tl9. The NOR
`gate N03 receives a signal RCSB from the roll call decoder
`14 and a test mode signal TM at the inputs thereof. The
`transistor Tl8 receives the signal RCE at the gate electrode
`thereof from the NOR gate N03 and functions as a transfer
`gate between the ground ("GND") and the bus line WREN.
`The transistor Tl9 functions as the transfer gate between the
`source line and the bus line WRBT.
`
`2
`The bus line pair WRBT/WRBN are clamped to the
`power source level by a clamp circuit 15 comprising gate(cid:173)
`grounded pair of P-channel transistors T7 and TS having a
`relatively small capacity for supplying a small charging
`5 current.
`In a normal read operation mode of the proposed roll call
`circuit, the test mode signal TM is "High" since it is "Low"
`only during a roll call test, and therefore, the signal RCE is
`"Low". It follows that the N-channel transistors T20 and T21
`10 are "ON" for a period while the input signal BSLB is "Low",
`and data supplied from the sense amplifier block through the
`data line pair RBT/RBN are fed to the 1/0 pads through the
`bus line pair WRBT/WRBN and the data output block DOl.
`In this case, no data are delivered to the bus line pair
`WRBT/WRBN from the second read circuit 16, because the
`15 signal RCE is "Low" and accordingly the transistors Tl8
`and Tl9 are "OFF".
`In operation for a roll call test mode, since the test mode
`signal TM is "Low" during the roll call test, data on the bus
`line pair WRBT/WRBN are determined in accordance with
`the level of the signal RCSB. If the signal RCSB is "Low",
`then the signal RCE is "High", causing the transistors Tl8
`and Tl9 to be "ON", and the transistors T20 and T21 to be
`"OFF", thereby maintaining WRBT at "High" and WREN at
`"Low". These data on the bus line pair WRBT/WRBN are
`delivered to the 1/0 pads through the data output block DOl.
`On the contrary, if the signal RCSB is "High", then the
`transistors Tl8 and Tl9 are "OFF" and the transistors T20
`and T21 are "ON" for a period while the signal BSLB is
`"Low". The data from the sense amplifier block are,
`therefore, delivered to the 1/0 pads through the bus line pair
`WRBT/WRBN and the data output block DOl.
`The X-decoder 18 decides which digit line is to be
`selected, in accordance with the address signals ADDO and
`ADD1-ADD9. The redundancy decoder 17 decides whether
`or not a redundancy digit line is to be selected. The address
`transition detector 19 generates a one-shot pre-charging
`signal YRD for a dynamic circuit in the roll call decoder 14.
`In the roll call test mode, the roll call decoder 14 generates
`the output signal RCSB depending on the result of the roll
`40 call test. Accordingly, if data have been written into memory
`cells beforehand so that the data line RBT from the sense
`amplifier block is made "Low" and the data line REN
`"High", the signal delivered to the 1/0 pads can be altered
`depending on "High" or "Low" of the signal RCSB. It
`follows that if the roll call test as described above is
`conducted while the combination of "High" and "Low" of
`the address signals ADD1-ADD9 is altered, it is possible to
`decide which redundant digit line has been used by deter(cid:173)
`mining the signals appearing on the 1/0 pads.
`Referring to FIG. 2, the roll call decoder 14 shown in FIG.
`1 comprises inverters I6-I8, a P-channel transistor T9, and
`N- channel transistors T22 and T23. The inverter I6 receives
`the one-shot pre-charging signal YRD, and the P-channel
`transistor T9 receives the test mode signal TM. The
`55 P-channel transistor TlO is connected in series with the
`transistor T9 between the source line and a pre-charge node,
`and receives an output signal from the inverter I6 at the gate
`thereof. The N-channel transistor T22, interposed between
`the pre-charge node and the GND, receives the test mode
`60 signal TM at the gate thereof. The N-channel transistor T23,
`connected in parallel with the transistor T22, receives the
`signal RDS from the redundancy decoder 7 at the gate
`thereof. The cascaded inverters I7 and IS receiving an input
`signal from the pre-charge node raises the amplitude of the
`65 pre-charge node to thereby generate the output signal RCSB.
`In operation of the roll call decoder 14 during a roll call
`test, since the test mode signal TM is "Low", the pre-charge
`
`45
`
`50
`
`MICRON-1004.007
`
`

`
`5,892,718
`
`3
`node is pre-charged to the power source level during a high
`level of a one-shot signal YRD. However, if the signal RDS
`is "High", the level of the pre-charge node is determined by
`the resistance divisional ratio of the transistors T9, TlO and
`T23. The output signal RCSB is obtained by the inverter 17
`having a ratio that makes the output "High" for that level of
`the pre-charge node, in association with the inverter 18.
`Since the test mode signal TM is "High" for the periods
`other than the roll call test, the pre-charge node is fixed at the
`GND level.
`The signal RDS from the redundancy decoder 17 is
`"High" if the redundancy memory cells have been used, and
`"Low" if not. Accordingly, it is possible to judge whether or
`not the redundancy function has been used, by detecting the
`output signal of the redundancy decoder 17.
`However, in a conventional semiconductor memory
`device of a type in which failed memory cells are replaced
`by redundant memory cells on a block-by-block basis, there
`exists no signal showing uniquely which memory cell block
`has been replaced because of the failure thereof. In this case,
`analysis of the cause of the failure is difficult.
`
`SUMMARY OF THE INVENTION
`It is therefore an object of the present invention to
`improve a semiconductor memory device of a type having a
`redundancy function, wherein failed memory cells are
`replaced on an l/O-by-1/0 basis, which is capable of detec(cid:173)
`tion whether or not and to which memory cells the redun(cid:173)
`dancy function has been used.
`The semiconductor memory device according to the
`present invention comprises: a plurality of memory cell
`blocks consecutively disposed in order and including a
`plurality of normal memory cell blocks and a redundant
`memory cell block successive to the normal memory cell
`blocks; an 1/0 block including a plurality of 1/0 pads each
`corresponding to one of the normal memory cell blocks; a
`programmable circuit programmable for storing data of a
`failed memory cell block among the normal memory cell
`block to output redundancy control data; a switching section
`for coupling the 1/0 pads with the respective memory cell
`blocks based on the redundancy control data while excepting
`the failed memory cell block and including the redundant
`memory cell block; a data read section for reading data
`through the 1/0 pads; and a roll call circuit for controlling
`the data read section while controlling the data for specified
`1/0 pads coupled with the failed memory cell blocks and
`succeeding memory cell blocks at a specified value.
`In accordance with the present invention, the failed
`memory cell block can be identified by the output from the
`1/0 pads after fabrication of the semiconductor memory
`device, which facilitates evaluation or analysis of the failure
`in the failed memory device.
`The above and other objects, features and advantages of
`the present invention will be more apparent from the fol(cid:173)
`lowing description, referring to the accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWING
`FIG. 1 is a circuit diagram of a conventional semicon(cid:173)
`ductor memory device;
`FIG. 2 is a circuit diagram of the roll call decoder shown
`in FIG. l;
`FIG. 3 is a circuit diagram of a semiconductor memory
`device according to a first embodiment of the present
`invention;
`FIG. 4 is a circuit diagram of the fuse control block shown
`in FIG. 3;
`
`4
`FIG. 5 is a circuit diagram of the sense amplifier block
`shown in FIG. 3;
`FIG. 6 is a circuit diagram of a semiconductor memory
`device according to a second embodiment of the present
`invention; and
`FIG. 7 is a circuit diagram of the data output block shown
`in FIG. 6.
`
`5
`
`10
`
`15
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`Now, the present invention is more specifically described
`with reference to accompanying drawings, wherein similar
`constituent elements are designated by the same or similar
`reference numerals.
`Referring to FIG. 3 showing a semiconductor memory
`device according to a first embodiment of the present
`invention, the memory device generally designated by
`numeral 10 comprises a plurality of memory sections,
`although one of the memory sections is shown in the figure.
`20 Each of the memory sections has a plurality of memory cell
`blocks Ml-Mn corresponding to respective IO pads 1/01-
`1/0n (not shown specifically in the figure) and a single
`redundant memory cell block MR. The memory section
`further comprises a programmable circuit 11, a plurality of
`25 pairs of first P-channel transistors Tll-Tln, a plurality of
`pairs of second P-channel transistors T21-T2n.
`The pairs of transistors Tll-Tln act as transfer gates for
`coupling the memory cell blocks Ml-Mn with respective
`30 data bus line pairs DBl-DBn, whereas the pairs of transis(cid:173)
`tors T 21-T 2 cn-l) act as transfer gates for coupling the
`memory cell blocks M2-Mn to respective preceding data
`bus line pairs DBcDBn-l and the pair of transistors T2n act
`as tranfer gates for coupling the redundant memory cell
`35 block MR to the data bud line pair Mn.
`The programmable circuit 11 comprises a fuse control
`block 20, a plurality of fuse elements Fl-Fn of low resis(cid:173)
`tance connected in series between a source line and the
`output node Sn of the fuse control section 20 and a plurality
`40 of inverters 131-13n, disposed in association with the respec(cid:173)
`tive fuse elements Fl-Fn, for controlling the use of the
`redundant memory cell block based on whether or not the
`fuse elements Fl-Fn have been cut.
`The memory section of the memory device further com-
`45 prises sense amplifier blocks Al-An for amplifying data
`supplied through the respective data bus line pairs
`DBl-DBn and transferring the amplified data to the data
`output blocks (not illustrated), and a roll call circuit 12
`having NOR gates Nl-Nn for receiving the output signals of
`50 the programmable circuit 11 from nodes Sl-Sn and a test
`mode signal TM supplied from outside the memory device,
`inverters Sil-Sin for receiving respective output signals
`through nodes Rll-Rln from the NOR gates Nl-Nn. Out(cid:173)
`put signals from the NOR gates Nl-Nn through nodes
`55 Rll-Rln and output signals from the inverters Sil-Sin
`through nodes R21-R2n are supplied to the respective sense
`amplifier blocks Al-An.
`Referring to FIG. 4, the fuse control block 20 comprises
`a serial branch of a fuse element FEl of low resistance and
`60 an N-channel transistor T31 connected between a source line
`and the GND line, a first inverter 12 having an input
`connected to a node connecting the fuse element FEl and
`N-channel transistor T31, and a second inverter ll having an
`input connected to the output of the first inverter 12. The gate
`65 electrode of the transistor T31 is connected to the output of
`the first inverter 12. The transistor T31 has a relatively small
`capacity.
`
`MICRON-1004.008
`
`

`
`5,892,718
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`15
`
`20
`
`5
`Referring to FIG. 5, each of the sense amplifier blocks
`Al-An shown in FIG. 3 comprises a sense amplifier 21,
`NAND gates NA1-NA3, a NOR gate NOl, an inverter 14,
`a P-channel transistor T3, and an N-channel transistor T32.
`The NAND gate NAl receives an output from the sense 5
`amplifier 21 and an output signal from the roll call circuit 12
`through the node R2 as a gate signal. The NOR gate NOl
`receives another output signal from the sense amplifier 21
`and an output signal from the roll call circuit 12 through the
`node Rl as a gate signal. The NAND gate NA2 receives an
`output from the NAND gate NAl and a signal SE as a gate 10
`signal that assumes "High" during a read operation. The
`NAND gate NA3 receives an output from the NOR gate
`NOl and the SE signal. The P-channel transistor T3 receiv(cid:173)
`ing at the gate thereof an output from the NAND gate NA2
`and the N-channel transistor T32 receiving at the gate
`thereof an output from the NAND gate NA3 through the
`inverter 14 are connected in series between the source line
`and the GND line, supplying an output signal at a node
`connecting the transistors T3 and T32 to a read bus line RB.
`In a normal operation mode of the memory device of FIG.
`3, where the fuse element FEl in the fuse control block 20
`has not yet been cut and accordingly the redundancy func(cid:173)
`tion has not been used, the input potential of the first inverter
`12 in the fuse control block 20 is determined depending on 25
`the resistance divisional ratio between the fuse element FEl
`and the N-channel transistor T31. Since the transistor T31
`has a relatively high resistance, the input of the inverter 12
`is "High", which is output through the inverters 12 and 11 to
`node Sn. In this case, the potentials of the nodes Sl-Sn are 30
`"High" since any of the fuse elements Fl-Fn has not yet
`been cut.
`Accordingly, in the normal operation mode, pairs of
`second transistors T21-T2n having gate electrodes con(cid:173)
`nected to respective nodes Sl-Sn are "Off", the outputs of
`the inverters 131-13n having inputs connected to the respec(cid:173)
`tive nodes Sl-Sn are "Low", and pairs of first transistors
`Tll-Tln having gate electrodes connected to the outputs of
`the respective inverters 131-13n are "ON". Accordingly, the
`memory cell blocks Ml-Mn are coupled with the respective
`data bus line pairs DBl-DBn, and data from selected
`memory cells are transferred to the respective sense ampli(cid:173)
`fier blocks Al-An through the respective data bus line pairs
`DBl-DBn.
`Further, in the normal operation mode, since the test mode 45
`signal TM is "High", the NOR gates Nl-Nn in the roll call
`circuit 12 output "Low" at respective nodes Rll-Rln and
`output "High" at respective nodes R21-R2n through the
`inverter Sil-Sin, regardless of the potentials of the nodes
`Sl-Sn in the programmable circuit 11. The NAND gates
`NAl and the NOR gates NOl in the respective sense
`amplifier blocks Al-An then transfer the data from the sense
`amplifier 21 through the read bus lines RBl-RBn.
`Assume that the redundant memory block MR is to be
`used to substitute for the last memory cell block Mn which
`has failed. In this case, the fuse element FEl in the fuse
`control block 20 of the programmable circuit 11 and the fuse
`element Fn are cut by a laser beam and the like, which
`causes the drain potential of the transistor T31 to be "Low"
`in FIG. 4. Therefore, the fuse control block 20 in the
`programmable circuit 11 outputs "Low" to the node Sn
`through the inverters 12 and 11. The nodes S 1-Sn_ 1 , other
`than the node Sn, is maintained "High" by the source
`potential, similarly to the case where no redundancy has
`been used.
`The output signal of the inverter 13n receiving "Low"
`signal through the node Sn is "High", and causes the pair of
`
`6
`first transistors Tln connected between the failed memory
`cell block Mn and the data bus line pair DBn, with the gate
`electrode thereof connected to the output of the inverter 13n,
`to be "OFF". This causes the failed memory cell block Mn
`to be electrically separated from the data bus line pair DBn.
`At the same time, the pair of second transistors T2n con(cid:173)
`nected between the redundant memory cell block MR and
`the data bus line pair DBn, with the gate electrode thereof
`connected to the node Sn, turn "ON", which causes the
`redundant memory cell block MR to be electrically con(cid:173)
`nected to the data bus line pair DBn, in stead of the memory
`cell block Mn.
`Since the memory cell blocks McMn-l for IO pads
`1/01-1/0n-l are coupled, similarly to the case wherein the
`redundancy is not used, with the respective data bus line
`pairs DB 1-DBn_ 1 , the data stored in the selected memory
`cells are transferred to a corresponding one of the sense
`amplifier blocks A1-~_1 through the data bus line pairs.
`The data stored in the redundant memory cell block MR are
`transferred to the sense amplifier block An through the data
`bus line pair DBn. Besides, in the normal operation mode,
`since the test mode signal TM is "High", the NOR gates
`Nl-Nn in the roll call circuit 12 output "Low" to the
`respective nodes Rll-Rln, regardless of the potentials of
`the nodes Sl-Sn in the programmable circuit 11. The NAND
`gates NAl and the NOR gates NOl in the respective sense
`amplifier blocks Al-An receive the "Low" through the
`respective nodes Rll-Rln, and transfer the data from the
`sense amplifier 21 to the read bus lines RBl-RBn through
`the respective inverters 14.
`It is to be noted that if a p-th memory cell block Mp is
`failed instead, the fuses FEl and Fp are cut to turn the pairs
`of second transistors T2 (p+l)-T2n "On" and pairs of first
`transistors T lp -T ln "Off". In this case, memory blocks
`McM(p-l) are coupled with respective data bus line pairs
`DBcDB(p-l)' memory cell blocks M(p+l)-Mn located
`behind the failed memory cell block Mp are coupled to the
`respective preceding data bus line pairs DBP-DB(n-l),and
`the redundant memory cell block MR is coupled with the last
`40 data bus line pair DBn.
`In a roll call test mode of the circuit shown in FIG. 3,
`assume that the memory cell block Mn for IO pad I/On has
`a failure and replaced by the redundant memory block MR.
`Transfer of data from the memory cell blocks Ml-Mn
`through respective sense amplifier blocks Al-An are
`effected in a manner similar to the described normal opera(cid:173)
`tion mode wherein the redundancy is used. In the roll call
`test, since the test mode signal TM assumes "Low", the
`50 output signals of the roll call circuit 12 are controlled based
`on the potentials of the respective nodes Sl-Sn in the
`programmable circuit 11. In this case, since the potentials of
`the nodes ScSn-l are "High", the signals at nodes
`Rl 1-Rln-l and at nodes R2cR2n_ 1 , to be supplied to the
`55 NAND gates NAl and NOR gates NOl in the respective
`sense amplifier blocks A1-~_1 , assume "Low", which
`allows the data from the respective sense amplifier 21 to be
`transferred to the respective read bus lines RB 1-RBn_ 1 .
`Since the potential of the node Sn is "Low", the potential
`60 at node Sn and the test mode signal TM provide "High" at
`the output of the NOR gate Nn in the roll call circuit 12. The
`output of the NOR gate Nn is inverted by the inverter Sin to
`make the node R2n "Low". The NAND gate NAl receiving
`the signal through the node R2n then outputs "High" regard-
`65 less of the data supplied from the sense amplifier 21.
`The NAND gate NA2 in the sense amplifier block An
`outputs "Low" by receiving an output from the NAND gate
`
`35
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`MICRON-1004.009
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`5,892,718
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`7
`NAl and the signal SE which is "High", to thereby turn on
`the P-channel transistor T3 receiving an output from the
`NAND gate NA2. The NAND gate NA3 outputs "High" by
`receiving an output from the NOR gate NOl as a gate signal,
`which turns off the N-channel transistor Tl2 through the 5
`inverter 14. As a result, the sense amplifier block An transfers
`"High" to the read bus line RBn, regardless of the data given
`by the memory cells.
`If all the memory cells in all the memory sections are
`written with "Low" data in the case as described above, the
`sense amplifier blocks A 1-A,,_ 1 in the normal memory
`sections output "Low" to the respective read bus lines
`RBcRBn_ 1 . On the other hand, in the failed memory section
`in which the redundant memory cell block has been used, the
`sense amplifier block An outputs "High" to the read bus line
`RBn. Thus, it is possible to judge whether or not and to
`which 1/0 pad the redundancy has been used.
`In summary, if the redundancy function has been used,
`sense amplifier blocks Al-An are so controlled by the roll
`call circuit 12 that those 1/0 pads including a 1/0 pad 20
`corresponding to the failed memory block (referred to as a
`failed 1/0 pad hereinafter) and the 1/0 pads located behind
`the failed 1/0 pad, as viewed along the order of the num(cid:173)
`bering or arrangement of the memory blocks, supply fixed
`data regardless of the data supplied from the memory cell 25
`blocks, if the test mode signal TM is in the active level.
`The fixed data supplied from the failed 1/0 pad or 1/0
`pads located behind the failed 1/0 pad, wherein the redun(cid:173)
`dancy function has been used, can be discriminated, regard(cid:173)
`less of the data supplied from the memory cell blocks. This 30
`enables to detect which 1/0 has been failed, or to which 1/0
`the redundancy has been used.
`Referring to FIG. 6, a semiconductor memory device
`according to a second embodiment of the present invention
`comprises a plurality of (four, for example) memory sections
`each having n memory blocks, although the memory blocks
`and memory sections are not specifically depicted. The first
`memory blocks, for example, as well as other memory
`blocks, in all the memory sections are connected together
`across the memory sections to a corresponding write/read
`bus line WRl for transferring output signals from those
`memory blocks through the write/read bus line.
`In this embodiment, a single redundant memory block is
`provided in each of the memory sections. If a p-th memory
`block in any one of the memory sections is failed, then all
`the p-th memory blocks are replaced by the respective
`redundant memory blocks in the respective memory
`sections, and the following memory blocks located behind
`the failed 1/0 pad in each memory section are replaced by 50
`the respective memory blocks located successive to the
`following memory blocks. The redundant memory blocks
`are also connected together to a write/read bus line WRR for
`transferring output signals for the redundant memory cell
`blocks through the sense amplifier block not shown.
`The semiconductor memory device has a common fuse
`control block 20, and a common programmable circuit 11.
`The programmable circuit 11 comprises a plurality of fuse
`elements Fl-Fn of low resistance and inverters 13 in asso(cid:173)
`ciation therewith, and controls the use of the redundancy
`function. There are further provided with P-channel transis(cid:173)
`tors T4 and TS, N-channel transistors TlS and Tl6, data
`output blocks DOl-DOn, data input blocks Dll-Dln and a
`roll call circuit 12.
`A pair of transistors T4 and TlS function as transfer gates 65
`for coupling the data output blocks DOl-DOn or data input
`blocks Dll-Dln with the respective write/read bus lines
`
`8
`WRl-WRn. A pair of transistors Tl6 and TS function as
`transfer gates for coupling the data output blocks DOl-DOn
`or data input blocks Dll-Dln with the respective succeeding
`write/read bus lines WR2-WRn and WRR.
`When the redundancy function is not used, data on the
`write/read bus lines WRl-WRn are output by the data
`output blocks DOl-DOn through respective 1/0 pads
`1/01-1/0n. Data input through the 1/0 pads 1/01-1/0n are
`transferred by the data input blocks Dll-Dln to the respec-
`10 tive write/read bus lines WRl-WRn. The roll call circuit 12
`has NOR gates Nl-Nn and inverters Sil-Sin. The NOR
`gates Nl-Nn receive a test mode signal TM and respective
`output signals from the programmable circuit 11. The invert(cid:173)
`ers Sil-Sin receive output signals from the respective
`15 inverters Nl-Nn. The output signals of the NOR gates
`Nl-Nn and inverters Sil-Sin are input to NAND gates NA4
`and NOR gates N02 (see FIG.7) in the respective data
`output blocks DOl-DOn.
`The fuse control block 20 has a configuration shown in
`FIG. 4. FIG. 7 shows one of the data output blocks shown
`in FIG. 6, which comprises data amplifier 22, NAND gates
`NA4-NA6, a NOR gate N02, a P-channel transistor T6, an
`N-channel transistor Tl7 and an inverter IS. The NAND gate
`NA4 receives an output from the data amplifier 22 and a
`signal through the node R2 from the roll call circuit 12 as a
`gate signal. The NAND gate NAS receives an output from
`the NAND gate NA4 and a signal OE that becomes "High"
`in a read operation mode as a gate signal. The NOR gate
`N02 receives an output from the data amplifier 12 and an
`output signal through the node Rl from the roll call circuit
`12 as a gate signal. The NAND gate NA6 receives an output
`from the NOR gate N02 and the signal OE as a gate signal.
`The transistor T6 receiving a gate input from the NAND gate
`NA6 and the transistor Tl 7 receiving a gate input from the
`35 NAND gate through an inverter IS are connected in series
`between the source line and the GND line. A node connect(cid:173)
`ing the transistors T6 and Tl 7 constitutes the output of the
`data output block.
`In a normal operation mode of the circuit shown in FIG.
`40 6, the programmable circuit 11 operates similarly to the
`programmable circuit shown in FIG. 3, when the redun(cid:173)
`dancy function has not yet been used, to maintain the
`potentials of the nodes Sl-Sn "High". This causes the
`transistors TS to be "OFF", the transistors TlS to be "ON",
`45 and output signals of the inverters 13 to be "Low", because
`these elements have respective inputs commonly connected
`with the respective nodes Sl-Sn. Further, the P-channel
`transistors T4 are "ON" and the N-channel transistors Tl6
`are "OFF", because these transistors receive the outputs
`from the respective inverters 13. Accordingly, all the write/
`read bus lines WRl-WRn are coupled with the data output
`blocks DOl-DOn or data input blocks Dll-Dln