FILE HISTORY
`US 6,233,181
`
`6,233,181
`PATENT:
`INVENTORS: Hidaka, Hideto
`
`TITLE:
`
`Semiconductor memory device with
`improved flexible redundancy scheme
`
`APPLICATION
`NO:
`FILED:
`ISSUED:
`
`US1999251352A
`
`17 FEB 1999
`15 MAY 2001
`
`COMPILED:
`
`19 MAR 2015
`
`MICRON-1002.001
`
`

`
`PATENT NUMBER
`
`6233181
`
`S6233181
`
`FILED WITH:
`
`] DISK (CRF) U FICHE
`(Attached in pocket on right inside flap)
`
`PREPARED AbD APPROVED FOR ISSUE
`
`.-
`
`)1
`
`:
`
`Form' PTO-436A
`(Rev. 6/98)
`
`(LABEL ARE4
`
`(FACE)
`
`MICRON-1002.002
`
`

`
`6,233,181
`
`SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED FLEXIBLE
`REDUNDANCY SCHEME
`
`Transaction History
`
`Transaction Description
`Date
`2/17/1999 Workflow - Drawings Finished
`2/17/1999 Workflow - Drawings Matched with File at Contractor
`2/17/1999 Workflow - Drawings Received at Contractor
`2/17/1999 Request for Foreign Priority (Priority Papers May Be Included)
`2/17/1999 Information Disclosure Statement (IDS) Filed
`2/17/1999 Information Disclosure Statement (IDS) Filed
`2/23/1999 Initial Exam Team nn
`3/8/1999 IFW Scan & PACR Auto Security Review
`3/16/1999 Application Dispatched from OIPE
`3/24/1999 Case Docketed to Examiner in GAU
`10/8/1999 Case Docketed to Examiner in GAU
`1/10/2000 Mail Restriction Requirement
`1/10/2000 Restriction/Election Requirement
`2/10/2000 Response to Election / Restriction Filed
`2/15/2000 Date Forwarded to Examiner
`4/10/2000 Non-Final Rejection
`4/12/2000 Mail Non-Final Rejection
`10/11/2000 Response after Non-Final Action
`10/11/2000 Request for Extension of Time - Granted
`10/20/2000 Date Forwarded to Examiner
`1/16/2001 Mail Notice of Allowance
`1/16/2001 Notice of Allowance Data Verification Completed
`2/21/2001 Workflow - File Sent to Contractor
`3/26/2001 Issue Fee Payment Verified
`4/14/2001 Workflow - Complete WF Records for Drawings
`4/18/2001 Application Is Considered Ready for Issue
`4/27/2001 Issue Notification Mailed
`5/15/2001 Recordation of Patent Grant Mailed
`
`
`
`MICRON-1002.003
`
`

`
`PATENT APPLICATION
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`09251352
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`If more than 150 claims or 10 actions
`staple additional sheet here
`
`(LEFT INSIDE)
`
`MICRON-1002.005
`
`

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`(RIGHT OUTS'IDE)
`(RGTOTSD)I
`
`MICRON-1002.006
`
`

`
`(12) United States Patent
`Hidaka
`
`
`iiui iuu uiii um uuumi
`IIII ui iiui
`
`
`uuuuuuiii u 11111 111 111 11
`
`US006233181B1
`US 6,233,181 B1
`May 15, 2001
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) SEMICONDUCTOR MEMORY DEVICE
`WITH IMPROVED FLEXIBLE
`REDUNDANCY SCHEME
`
`(75)
`
`Inventor: Hideto Hidaka, Hyogo (JP)
`
`(73) Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo (JP)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/251,352
`
`(22) Filed:
`
`Feb. 17, 1999
`
`(30)
`
`Foreign Application Priority Data
`
`5,892,718 * 4/1999 Yamada ............................. 366/200
`
`FOREIGN PATENT DOCUMENTS
`
`6-232348
`6-237164
`
`H01L/27/04
`8/1994 (JP) ............................
`8/1994 (JP) ....................... H03K/19/0948
`
`OTHER PUBLICATIONS
`
`for High-Density
`"A Flexible Redundancy Technique
`DRAM's", by Horiguchi, et al., IEEE Journal of Solid State
`Circuits, vol. 26, No. 1, Jan. 1991, pp. 12-17.
`
`"Ultra LSI Memory", Kiyoo ITO, Advanced Electronics
`Series I-9, published by Baifukan, pp. 350-371, Nov. 5,
`1994.
`
`* cited by examiner
`
`(JP) .............................................. 10-160466
`
`Jun. 9, 1998
`Primary Examiner-Andrew Q. Tran
`Oct. 15, 1998
`(JP) .............................................. 10-293421
`(74) Attorney, Agent, or Firm-MlcDermott, Will & Emery
`..................... .
`Int. C l. 7 .............................
`. G 11C 7/00
`(51)
`(52) U.S. Cl
`................ 365/200; 365/230.03; 365/190;
`365/225.7
`(58) Field of Search ........................... 365/200, 230.03,
`365/190, 208, 225.7
`
`ABSTRACT
`
`A spare memory array having spare memory cells common
`to a plurality of normal sub-arrays having a plurality of
`normal memory cells is provided. A spare line in the spare
`array can replace a defective line in the plurality of normal
`sub-array. The defective line is efficiently repaired by
`replacement in an array divided into blocks or sub-arrays.
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,761,138 * 6/1998 Lee et al .......................... 365/200
`
`7 Claims, 31 Drawing Sheets
`
`XO
`
`NORMAL MEMORY SUB-ARRAY
`
`SPDX
`
`SPARE ARRAY
`
`MA#0 1} RBX#O
`
`SPX#
`
`X1
`
`NORMAL MEMORY SUB-ARRAY
`
`MA#1; RBX#1
`
`SPDX
`
`X2
`
`NORMAL MEMORY SUB-ARRAY
`
`MA#2; RBX#2
`
`Xm
`
`NORMAL MEMORY SUB-ARRAY
`
`MA#m; RBX#m
`
`MICRON-1002.007
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 1 of 31
`
`US 6,233,181 B1
`
`0 C
`
`0 z
`
`z,
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`00 C
`
`D
`
`MICRON-1002.008
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 2 of 31
`
`US 6,233,181 B1
`
`FIG. 2A
`
`MB#On
`
`SP# Q n,
`
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`
`MICRON-1002.009
`
`

`
`U. S. Patent
`
`May 15, 2001
`
`Sheet 3 of 31
`
`US 6,233,181 B1
`
`FIG. 3A
`
`SCSL1
`
`SCSL3
`
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`
`MICRON-1002.010
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 4 of 31
`
`US 6,233,181 B1
`
`FI G. 4
`
`NG 00
`
`NGI01
`
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`FIG. 24
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`
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`
`(0A2, QA3)
`
`MICRON-1002.011
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 5 of 31
`
`US 6,233,181 B1
`
`r
`
`MICRON-1002.012
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`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 6 of 31
`
`US 6,233,181 B1
`
`FIG. 6
`
`L
`
`FIG. 7
`
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`
`MICRON-1002.013
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`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 7 of 31
`
`US 6,233,181 B1
`
`FIG.
`
`Irr~
`
`1 ,
`
`FIG.
`
`XO
`
`NORMAL MEMORY SUB-ARRAY
`
`SPDX
`
`X1
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`
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`
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`
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`
`MA#2; RBX#2
`
`Xm
`
`NORMAL MEMORY SUB-ARRAY
`
`MA#m; RBX#m
`
`MICRON-1002.014
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 8 of 31
`
`US 6,233,181 B1
`
`FIG. 10
`
`SPDX
`
`RBX
`#0
`
`FIG. 11
`
`REPLACEABLE WITH ROW IN
`NORMAL MEMORY SUB-ARRAY
`IN MA#O-
`
`SENSE AMPLIFIER BAND
`
`.--SABO
`
`NORMAL MEMORY SUB-ARRAY
`
`(SWL)
`SPARE ARRAY
`SENSE AMPLIFIER BAND
`
`-
`
`MA#O-O0
`SPX#O RBX#O
`-SAB1
`
`NORMAL MEMORY SUB-ARRAY
`
`---MA#1-0
`
`SENSE AMPLIFIER BAND
`
`---SAB2
`
`NORMAL MEMORY SUB-ARRAY
`
`-MA#O-1
`
`SENSE AMPLIFIER BAND
`
`SAB3
`
`REPLACEABLE WITH
`ROW IN NORMAL
`MEMORY SUB-ARRAY
`IN MA#1-
`
`--
`
`SENSE AMPLIFIER BAND
`
`NORMAL MEMORY SUB-ARRAY
`
`SENSE AMPLIFIER BAND
`SPARE ARRAY (SWL)
`
`NORMAL MEMORY SUB-ARRAY
`
`SENSE AMPLIFIER BAND
`
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`
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`
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`M#1
`MA#1-N
`
`SABm+1
`
`RBX#1
`
`MICRON-1002.015
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 9 of 31
`
`US 6,233,181 B1
`
`FIG.
`
`1 2
`
`/(ksp
`
`461
`
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`
`4)
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`
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`FIG.
`
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`
`L------------------------------
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`
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`
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`BLIJ
`
`MICRON-1002.016
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 10 of 31
`
`US 6,233,181 B1
`
`FIG.
`
`15
`
`SENSE AMPLIFIER BAND
`MA#O-O
`SPX#O
`SPARE ARRAY
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`
`FIG.
`
`16
`
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`
`MICRON-1002.017
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 11 of 31
`
`US 6,233,181 B1
`
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`MICRON-1002.018
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 12 of 31
`
`US 6,233,181 B1
`
`FIG. 18A
`
`IN NORMAL MODE;
`
`RAO
`
`RAh
`
`TO ADDRESS ONE NORMAL
`MEMORY SUB-ARRAY IN
`EACH MEMORY BLOCK GROUP
`
`RAi ---- TO ADDRESS MEMORY MAT
`
`RAj --- TO ADDRESS MEMORY BLOCK
`
`ONE SUB-ARRAY
`IS ADDRESSED
`
`FIG. 18B
`IN TEST MODE;
`
`RA0
`
`RAh
`
`TO ADDRESS ONE NORMAL
`MEMORY SUB-ARRAY IN
`EACH MEMORY BLOCK GROUP
`
`RAi -
`
`TO ADDRESS MEMORY MAT
`
`RAj -
`
`TO DEGENERATE
`
`SUB ARRAY IS
`ADDRESSED FROM
`EACH OF TWO
`BLOCK GROUPS
`IN ONE MAT
`(SENS AMPLIFIER
`BAND IS NOT SHARED)
`
`F IG.
`
`19
`
`RAj
`
`MICRON-1002.019
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 13 of 31
`
`US 6,233,181 B1
`
`II
`r ¢
`
`iIm
`
`I I
`
`it
`
`WI
`
`-
`
`W
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`,
`
`MICRON-1002.020
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 14 of 31
`
`US 6,233,181 B1
`
`FIG.
`Vr
`9
`
`21A
`
`1/
`I
`
`_
`
`O Bb
`
`SW
`
`4b
`
`5a
`
`4a
`
`3a----
`
`ROW-RELATED ROW-RELATED
`PERIPHERAL CKT PERIPHERAL CKT
`
`MEMORY ARRAY MEMORY ARRAY
`BLOCK
`BLOCK
`
`Bn
`
`SW4n
`
`5n
`
`ROW-RELATED
`PERIPHERAL CKT
`
`MEMORY ARRAY
`BLOCK
`
`2a
`
`4Ba
`
`2b
`
`Bn
`
`SR
`
`POWER SUPPLY
`BLOCK DECODER
`
`6
`
`AD
`
`FIG. 21B
`
`MICRON-1002.021
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 15 of 31
`
`US 6,233,181 B1
`
`FIG. 22
`
`(RA2, RA3) :
`
`(1, 1)
`
`(0,1)
`
`(1, 0)
`
`(0, 0)
`
`RAl=1
`
`SW5
`
`RA1=O
`
`MEMORY
`BLOCK
`MAB5
`(q B5)
`POWER SUPPLY
`SWITCH
`SW1
`
`MAB1
`
`(k B1l)
`
`MAB6
`(q B6)
`SW6
`
`SW2
`
`MAB2
`
`MAB7
`(0 B7)
`SW7
`
`SW3
`
`MAB3
`
`MAB8
`(4 B8)
`SW8
`
`SW4
`
`MAB4
`
`(0 B2)
`
`(0 B3)
`
`( B4)
`
`GAB1
`
`GABO
`
`FIG. 23A
`NORMAL MODE
`GABO
`MAB1
`
`MAR9
`
`t U
`
`GAB1
`MAB5
`
`FIG.
`
`23B
`
`(1, 1)
`
`_
`
`RA1
`
`DEFINED
`
`WL
`WL
`
`S2 SW6
`
`MAB6
`
`(0,1)
`
`qB1-4
`
`MAB3
`
`SWSW7
`
`MAB7
`
`(1,0)
`
`RA1-3
`
`DEFINED
`
`MAB4 SW SW8
`
`MAB8
`
`(0, 0)
`
`q B2
`
`- ROW-RELATED
`CKT OPERATION
`
`RA1:
`
`0
`
`1
`
`/fn
`
`(RA2, RA3)
`
`HIGH SPEED OPERATION
`
`VOLTAGE
`STABILIZED
`
`MICRON-1002.022
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 16 of 31
`
`US 6,233,181 B1
`
`FIG. 25
`
`CM
`
`POWER SUPPLY
`ICK DECODER
`
`TO ROW-RELATED CKT IN
`EACH MEMORY BLOCK
`
`MICRON-1002.023
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 17 of 31
`
`US 6,233,181 B1
`
`FIG.
`
`26
`
`R
`
`(QACT)
`SR
`
`QA1-3
`/QA1-3
`
`FIG. 27
`
`/RA1
`6a
`
`(QACT'
`SR
`
`/QA1
`/QA2
`QA2
`
`FIG. 28
`
`bBi
`i =1-88
`
`6e
`
`6
`
`q B2
`
`STO
`
`POWER SUPPLY
`DECODE CKT
`
`OW-RELATED
`PHERAL CKT
`
`MICRON-1002.024
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 18 of 31
`
`US 6,233,181 B1
`
`33a
`
`q WL
`
`33
`
`ACTIVE
`
`POWER SUPPLY
`BLOCK SELECTED.
`I ZED
`
`J
`I
`
`,
`,,
`
`II
`
`
`I
`I
`
`NORMAL MODE
`
`SELF-REFRESH MODE
`
`FIG.
`
`29
`
`QACT
`
`RACT
`
`FIG. 30
`
`RACT
`
`QACT
`
`q RX
`
`SWL
`
`WL
`
`MICRON-1002.025
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 19 of 31
`
`US 6,233,181 B1
`
`FIG. 31
`
`(Vpp *- Vss)
`SoX
`
`"L"
`
`41
`
`42
`
`#Bi
`
`KUnW UUUUC U nI
`
`IIURU LI IC
`DRIVE CKT
`
`FIG. 32A
`GABO
`
`GAB1
`
`FIG. 32B
`GABO
`
`GAB1
`
`MAB1
`
`SWl SW5
`
`MAB5
`
`(1, 1)
`
`MAB1 SI SW5
`
`MAB5
`
`MAB2--S
`WL
`
`SW2 SW6
`
`MAB6
`
`(0,1)
`MAB2
`
`WL
`SW2 S6
`/ MAB6
`
`WL
`
`MAB3
`
`SW3 SW7
`
`MAB7
`
`(1, 0)
`
`MAB3
`
`SW3 SW7
`
`MAB7
`
`MAB4
`
`SW4 SU
`
`MAB8
`
`:NORMAL MODE
`
`(0, 0)
`
`(QA2, 3)
`
`MAB4
`
`SW4 S18
`
`MAB8
`
`:REFRESH MODE
`
`MICRON-1002.026
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 20 of 31
`
`US 6,233,181 B1
`
`FIG. 33
`
`R
`
`(QACT)
`SR
`
`QA2, 3
`/QA2, 3
`
`FIG. 34
`
`RA1
`6a
`
`(QACT)
`SR
`
`/QA;
`QA:
`
`5Bi
`i =1 ^-
`
`6e
`
`6
`
`4 B2
`
`FIG. 35
`
`Vr
`
`SW
`
`n
`
`0Bi
`
`rn A
`
`4WLI
`
`Ad ---
`
`ROW-RELATED
`SELECTING CKT
`
`.
`
`WJ
`
`MICRON-1002.027
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 21 of 31
`
`US 6,233,181 B1
`
`FIG.
`
`36
`
`CUP
`
`----
`
`----
`60
`POWER SUPPLY
`BLOCK DECODE
`CKT
`
`61
`
`I. .....
`
`I
`
`I 1
`
`CUP
`
`QACT
`
`SR
`
`ITCH CKT
`
`TO ROW-RELATED PERIPHERAL CKT
`
`FIG. 37
`
`REFRESH
`
`QACT
`
`CUP
`
`LATCH 61
`
`LATCH 62
`
`SB1-8
`
`4 CUP
`
`QA
`
`WL
`
`FOR STABILIZATION OF
`POWER SUPPLY
`
`MICRON-1002.028
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 22 of 31
`
`US 6,233,181 B1
`
`FIG. 38
`
`QAi
`/QAi
`
`CUP
`
`/QACT
`
`QACT
`
`oBi
`
`------
`
`v------
`
`-----------
`
`61
`
`6
`
`62
`
`FIG. 39
`
`FROM
`REFRESH
`ADDRESS
`COUNTER
`
`A N IP
`
`QACT
`
`65b
`
`65e
`
`65c
`
`FIG.
`
`40
`
`67
`
`68
`
`QACT
`
`DELAY CKT
`
`>UP5 GENERATING CKT
`
`69
`
`70
`/
`ONE-SHOT PULSE
`GENERATING GKT 1-4
`
`MICRON-1002.029
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 23 of 31
`
`US 6,233,181 B1
`
`FIG. 41
`
`MAB5
`/
`
`NORMAL
`MEMORY
`BLOCK
`
`NMAB5
`
`SW5
`
`SW1
`
`MAB6/
`
`NORMAL
`MEMORY
`BLOCK
`
`NMAB6
`
`SW6
`
`SW2
`
`NORMAL I
`MEMORY '
`BLOCK iS PB
`
`NORMAL
`MEMORY
`BLOCK
`
`MAB7
`/
`
`NORMAL
`MEMORY
`BLOCK
`
`NMAB7
`
`SW7
`
`SW3
`
`NORMAL
`MEMORY
`BLOCK
`
`MAB8/
`
`NORMAL
`MEMORY
`BLOCK
`
`NMAB8
`
`SW8
`
`SW4
`
`NORMAL
`MEMORY
`BLOCK
`
`NMAB1
`
`I
`
`NMAB4
`NMAB3
`NMAB2
`__________________________________
`
`__________________________________ __________________________________
`
`MAB1
`(RBX#)
`
`MAB2
`
`MAB3
`
`MAB4
`
`FIG. 42
`
`RA1
`
`MAB1
`
`MAB2
`
`SW
`
`MAB5
`
`(1, 1)
`
`SW
`
`SW6
`
`MAB6
`
`(0, 1)
`
`SPARE BLOCK
`
`NWL
`
`MAB3
`
`SW3 SW7
`
`MAB7
`
`(1,0)
`
`MAB4
`
`SW4 SW8
`
`MAB8
`
`(0, 0)
`
`:NORMAL MODE
`
`(RA2, RA3)
`
`MICRON-1002.030
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 24 of 31
`
`US 6,233,181 B1
`
`FIG. 43
`
`RACT
`
`RA
`
`SB1
`
`SPARE HIT
`
`q B2-8
`
`NWL
`
`SWL
`
`FIG. 44
`
`QA1
`
`:
`
`0
`
`SPARE DETERMINATION
`TIME CAN BE HIDDEN
`
`MAB1
`
`SPB'
`
`MAB2
`
`SWL
`
`SW1 SW5
`
`MAB5
`
`(1, 1)
`
`SW2 SW6
`
`MAB6
`
`(0,1)
`
`NWL
`
`MAB3
`
`SW3 SW7
`
`MAB7
`
`(1, 0)
`
`MAB4
`
`SW4 SW8
`
`MAB8
`
`(0, 0)
`
`:REFRESH MODE
`SPARE DETERMINATION - SW SELECTION
`
`(QA2, QA3)
`
`MICRON-1002.031
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 25 of 31
`
`US 6,233,181 B1
`
`F I G. 4
`
`.5
`
`QACT
`
`QA
`
`SPARE HIT
`
`4 B1-4'B8
`
`NWL
`
`SWL
`
`FIG.
`
`46A
`
`/RACT
`
`/QA1
`0A2
`0A3
`
`4 B1
`
`FIG. 46B
`
`/RACT
`
`QACT
`
`QA
`
`q
`
`OUTPUT OF
`NAND71
`
`/B1
`
`/HI
`
`NORMAL MODE
`
`-
`
`REFRESH MODE
`
`I
`I
`
`i
`
`II
`
`(I
`
`I
`I
`
`-
`
`I
`I
`
`IIII
`
`MICRON-1002.032
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 26 of 31
`
`US 6,233,181 B1
`
`q Bj
`
`j= 2 -8
`
`NORMAL MODE ---
`
`SELF-REFRESH MODE
`
`FIG.
`
`47A
`
`QA1, /QA
`
`QA2, /QA
`
`QA3
`
`/QA
`
`FI G. 47B
`
`/RACT
`
`QACT
`
`RA
`
`QA
`
`HIT
`
`q5Bj
`
`FIG. 48
`
`0 RX.
`
`WORD LINE DRIVE
`TIMING CONTROL
`
`SWL
`
`MICRON-1002.033
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 27 of 31
`
`US 6,233,181 B1
`
`i
`I I
`
`-o
`
`I
`
`=
`
`MICRON-1002.034
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 28 of 31
`
`US 6,233,181 B1
`
`SW1 SW5
`
`MAB5
`
`(1, 1)
`
`S S2 SW6
`
`MAB6
`
`(0, 1)
`
`FIG. 50A
`
`0 S
`
`WL
`
`NWL
`
`Al
`
`MAB1
`
`SPB
`
`MAB2
`
`MAB3
`
`S13 SW7
`
`MAB7
`
`(1, 0)
`
`MAB4
`
`SW4 SW8
`
`MAB8
`
`(0, 0)
`
`:BEFORE SPARE DETERMINATION DEFINED
`NORMAL MODE
`
`(A2, A3)
`
`FIG.
`
`50B
`
`RA1
`
`:
`
`0
`
`MABi
`
`SPB
`
`MAB2
`
`SWL
`
`SW1 SW5
`
`MAB5
`
`(1, 1)
`
`SW2 SW6
`
`MAB6
`
`(0, 1)
`
`NWL
`
`MAB3
`
`SW3 SW7
`
`MAB7
`
`(1, 0)
`
`MAB4
`
`SW4 SW8
`
`MAB8
`
`(0, 0)
`
`(RA2, RA3)
`:AFTER SPARE DETERMINATION DEFINED
`NORMAL MODE
`
`MICRON-1002.035
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 29 of 31
`
`US 6,233,181 B1
`
`FIG. 51A
`,-----------, .90
`
`(B1
`
`"L" IN STAND-BY STATE
`
`LE OR PREVIOUS CYCLE)
`
`FIG. 51B
`
`/RACT
`
`QA
`
`/HIT
`
`0B1
`
`FI G.
`
`52
`
`4 Bj
`
`j=2-8
`
`QA1, /QA
`
`QA2, /QA
`
`QA3 /QA
`,.. /QA
`
`(PRESENT CYCLE OR PREVIOUS CYCLE)
`
`MICRON-1002.036
`
`

`
`U.S. Patent
`
`May 15, 2001
`
`Sheet 30 of 31
`
`US 6,233,181 B1
`
`FIG.
`
`5 3
`
`PRIOR ART
`
`MAn
`
`SWO1
`
`1I
`
`i
`
`X3
`
`at
`an-
`
`FIG.
`
`5 4
`
`PRIOR ART
`
`DEFECTIVE
`SENSE AMPLIFIER
`I
`
`MBi+1
`/
`
`----- X------
`
`DEFECT IVE
`YS LINE
`
`BL
`
`/BL
`
`G YS
`
`IL
`
`I
`
`I I
`
`r--
`I
`
`X
`
`SSA
`
`SI/O
`
`SPARE COLUMN
`
`IOG
`
`_L-
`
`I
`
`r I II I
`
`_
`
`MBi
`
`BL
`
`ILG -
`
`--
`
`I I
`
`/BL
`
`T
`
`I-__
`
`DEFECTIVE
`BIT LINE
`SPARE COLUMN
`SPARE COLUMN
`
`MICRON-1002.037
`
`

`
`U. S. Patent
`
`May 15, 2001
`
`Sheet 31 of 31
`
`US 6,233,181 B1
`
`FIG.
`
`55
`
`PRIOR ART
`
`LOW-Vth
`
`FIG. 56
`
`PRIOR ART
`
`I
`
`5 ACT
`
`904
`
`906
`
`--------------
`
`---------- Vc
`
`-
`
`, Vss
`
`STAND-BY CYCLE
`
`ACTIVE CYCLE : STAND-BY CYCLE
`
`MICRON-1002.038
`
`

`
`US 6,233,181 B1
`
`1
`SEMICONDUCTOR MEMORY DEVICE
`WITH IMPROVED FLEXIBLE
`REDUNDANCY SCHEME
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates generally to semiconductor
`memory devices, and more particularly, to a semiconductor
`memory device having a memory array divided into a
`plurality of memory blocks. More specifically, the present
`invention relates to a redundancy circuit for repairing a
`defective memory cell in a semiconductor memory device
`having such an array-divided arrangement and a power
`supply circuit provided corresponding to each block.
`2. Description of the Background Art
`In the semiconductor memory device, a defective memory
`cell is replaced with a spare memory cell in order to
`equivalently repair the defective memory cell to raise the
`yield of the products. A flexible redundancy scheme has
`been proposed in order to improve the use efficiencies of
`spare lines (word lines or bit lines) and spare decoders for
`selecting spare lines in a redundancy circuit configuration
`including spare memory cells (spare word lines and bit lines)
`for repairing such defective memory cells (see, for example,
`"A Flexible Redundancy Technique for High-Density
`DRAM's", Horiguchi et al., IEEE Journal of Solid-State
`Circuits, Vol. 26, No. 1, January 1991, pp. 12 to 17).
`FIG. 53 is a schematic diagram of the general configu-
`ration of a semiconductor memory device having a conven-
`tional flexible redundancy scheme. In FIG. 53, the semicon-
`ductor memory device includes four memory arrays MAO to
`MA3. In each of memory arrays MAO to MA3, a spare word
`line to repair a defective memory cell row is provided. In
`memory array MAO, spare word lines SWOO and SWO1 are
`provided, and in memory array MA1, spare word lines
`SW11 and SW11 are provided. In memory array MA2, spare
`word line SW20 and SW21 are provided, and in memory
`array MA3, spare word lines SW30 and SW31 are provided.
`Row decoders XO to X3 each for decoding an address
`signal to drive a normal word line provided corresponding to
`an addressed row into a selected state are provided corre-
`sponding to memory arrays MAO to MA3. A column
`decoder YO is provided between memory arrays MAO and
`MA1 to decode a column address signal to select an
`addressed column, and also a column decoder Y1 is pro-
`vided between memory arrays MA2 and MA3.
`The semiconductor memory device further includes spare
`decoders SDO to SD3 to store a row address at which a
`defective memory cell is present, maintain a word line
`(defective normal word line) corresponding to this defective
`row address in a non-selected state when the defective row
`is addressed and drive a corresponding spare word line into
`a selected state, an OR circuit GO to receive output signals
`from spare decoders SDO and SD1, and an OR circuit G1 to
`receive output signals from spare decoders SD2 and SD3.
`The output signals of OR circuits GO and G1 are provided
`in common to spare word line driving circuits included in
`row decoders XO to X3. Spare decoders SDO to SD3 are
`commonly provided with array address signal bits an-2 and
`an-1 to address one of memory arrays MAO to MA3 and
`with intra-array address signals bits a0 to an-3 to address a
`row in the memory array. Row decoders XO to X3 are
`provided with array address signal bits an-2 and an-1, and a
`row decoder is activated when a corresponding memory
`array is addressed. OR circuits GO and G1 each correspond
`to two spare word lines provided for each of memory arrays
`MAO to MA3.
`
`10
`
`Let us assume that normal word lines WO and Wl are
`defective in memory array MAO, that a normal word line W2
`in memory array MA1 is defective, and that a normal word
`line W3 in memory array MA2 is defective. In this state, the
`5 address of word line WO is programmed in spare decoder
`SDO, while the address of word line Wl is programmed in
`spare decoder SD2. The address of normal word line W2 is
`programmed in spare decoder SD3, and the address of
`normal word line W3 is programmed in spare decoder SD1.
`OR circuit GO selects one of spare word lines SW00,
`SW10, SW20 and SW30, and the output signal of OR circuit
`G1 selects one of spare word lines SW01, SW1l, SW21 and
`SW31.
`When normal word line WO is addressed, the output
`15 signal of spare decoder SDO is driven into a selected state,
`and the output of OR circuit GO is activated. In this state,
`array address signal bits an-2 and an-1 activate row decoder
`XO, and the remaining row decoders X1 to X3 are main-
`tained in a non-active state. Thus, a word line driving circuit
`20 included in row decoder XO drives spare word line SWOO
`into a selected state in response to the output signal of OR
`circuit GO. At this time, in row decoder XO, a decode circuit
`provided corresponding to normal word line WO is main-
`tained in a non-active state. As a result, defective normal
`25 word line WO is replaced with spare word line SW00.
`If defective normal word line Wl is addressed, the output
`signal of spare decoder SD2 attains an H level in a selected
`state, the output signal of OR circuit G1 attains an H level,
`30 and spare word line SWO1 is selected. If defective normal
`word line W2 is addressed,
`the output signal of spare
`decoder SD3 attains an H level in a selected state, the output
`signal of OR circuit G1 attains an H level, and spare word
`line SW11 is selected. If defective normal word line W3 is
`35 addressed, the output signal of spare decoder SD1 attains an
`H level in a selected state, and spare word line SW20 is
`selected by OR circuit GO accordingly. More specifically,
`defective normal word lines WO, Wl, W2 and W3 are
`replaced with spare word lines SWOO, SW01, SW11 and
`40 SW20, respectively.
`In this flexible redundancy scheme shown in FIG. 53, a
`single spare word line can be activated by any of a plurality
`of spare decoders. For example, spare word line SW20 can
`be driven into a selected state by spare decoder SDO or SD1.
`45 A single spare decoder can drive any of a plurality of spare
`word line into a selected state. For example, spare decoder
`SDO can drive any of spare word lines SWOO, SW10, SW20
`and SW30 into a selected state. Thus, the spare word line and
`spare decoders do not correspond in one-to-one relation, and
`50 therefore the spare word lines and spare decoders can be
`more efficiently utilized. The number of spare word lines
`and the number of spare row decoders in a single memory
`array may be selected independently from each other as long
`as the numbers satisfy the following relation:
`L<R<M-L/m
`
`wherein M is the number of physical memory arrays, m the
`number of memory arrays whose defective normal word
`lines are replaced with spare word lines simultaneously, R
`60 the number of spare row decoders, and L the number of
`spare word lines in a single memory array. More specifically,
`M/m is the number of memory arrays which are logically
`independent from one another. As a result, M.L/m represents
`the number of spare word lines which are logically inde-
`65 pendent from one another for the entire memory. Herein, the
`logically independent spare word lines are spare word lines
`selected by different row addresses. For example, in FIG. 53,
`
`MICRON-1002.039
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`

`
`US 6,233,181 B1
`
`if a normal word line is simultaneously selected in memory
`arrays MAO and MA2, memory arrays MAO and MA2 are
`not logically independent from each other. In the arrange-
`ment shown in FIG. 53, L=2, R=4, M=4 and m=1.
`By providing a spare row decoder common to memory
`arrays, a spare decoder does not have to be provided for each
`of spare word lines, which can restrain the chip area from
`increasing.
`The flexible redundancy scheme shown in FIG. 53 may be
`employed for repairing a defective column as well. In
`repairing a defective column, the previously mentioned prior
`art document describes a method of repairing a defective
`column where a memory array is divided into a plurality of
`sub-arrays. The document particularly describes the way of
`repairing a defective column in multi-divided bit lines in a
`shared-sense amplifier arrangement and in a shared I/O
`scheme.
`FIG. 54 is a schematic diagram of the configuration of an
`array portion in a semiconductor memory device according
`to a conventional flexible redundancy scheme. In FIG. 54,
`two memory blocks MBi and MBi+1 are shown. Memory
`blocks MBi and MBi+1 each include a normal bit line pair
`BL and /BL provided corresponding to each memory cell
`column and a spare bit line (spare column) for repairing a
`defective column. In FIG. 54, the spare bit line included in
`the spare column is not clearly shown.
`Normal bit lines BL and /BL at the same column address
`in memory blocks MBi and MBi+1 share a sense amplifier
`SA. A bit line isolation gate ILG is provided between sense
`amplifier SA and memory blocks MBi and MBi+1. Sense
`amplifier SA is connected to an internal data line pair I/O
`through an IO gate IOG which conducts in response to a
`column selecting signal YS from column decoder Y. A
`memory block including a selected memory cell (MBi, for
`example) is connected to sense amplifier SA and data is read
`out therefrom. In this case, a non-selected memory block
`(MBi+1) is disconnected from sense amplifier SA.
`In
`the above-described shared-sense amplifier
`arrangement, a defective column address must be pro-
`grammed for each of defects in normal bit lines, in a single
`memory block column selecting lines (YS lines) and sense
`amplifiers SA. For a normal bit line defect, the defective
`column address is programmed on a memory block basis.
`For a sense amplifier defect, the defective column address is
`so programmed as to use a spare column for each of memory
`blocks MBi and MBi+1 which share this defective sense
`amplifier. For a column selecting line (YS line) defect, the
`defective column address is programmed for each of the
`memory blocks connected to this column selecting line (YS
`line).
`At the time of programming, in order to use a single spare
`column decoder for a normal bit line defect, a sense ampli-
`fier defect and a column selecting line (YS line) defect,
`"Don't care" is programmed at the time of programming a
`defective column address, an address to specify a memory
`block is invalidated, and spare columns are replaced simul-
`taneously in a plurality of memory blocks.
`In the previously mentioned document, a defective row is
`repaired by replacing the defective row with a spare word
`line provided within a memory array including that defective
`row. Thus, a spare word line must be provided for each of
`memory arrays, and the spare word lines are not efficiently
`utilized. If a defective normal word line in one memory
`array is replaced with a spare word line in another memory
`array, the control of the memory array related circuits will be
`complicated, and therefore such arrangement must be
`avoided and is not considered at all.
`
`In repairing a defective column, a spare column is pro-
`vided for each of memory blocks, and spare columns are
`similarly not efficiently used. Although the shared I/O
`scheme has been considered for internal data line
`5 arrangement, the way to repair a defective column in a
`memory array having a local/global hierarchical data line
`arrangement used in a recent block-divided arrangement has
`never been considered.
`Meanwhile, in a conventional CMOS (Complimentary
`to MOS) type semiconductor device, the size of components
`(MOS transistor: insulated gate type field effect transistor) is
`reduced to increase the integration density. In order to secure
`the reliability of the components thus miniaturized and to
`reduce the current consumed by the entire device, the power
`15 supply voltage is reduced. In order to allow the components
`to operate at a high speed, the threshold voltage of the MOS
`transistor must be lowered depending upon the power supply
`voltage. This is because if the ratio of the threshold voltage
`to the power supply voltage is large, the transition timing of
`20 the MOS transistor to the on state is delayed. If, however, the
`absolute value of the threshold voltage is lowered, sub-
`threshold leakage current to flow through the source-drain
`region when the MOS transistor is turned off increases. This
`is for the following reason. The threshold voltage is defined
`25 as the gate-source voltage to allow a prescribed drain current
`to flow. In an n-channel MOS transistor, if the threshold
`voltage is lowered, the drain current-gate voltage character-
`istic curve shifts toward the negative direction. The sub-
`threshold current is represented by the current value when
`30 gate voltage Vgs in the characteristic curve is OV, and
`therefore the sub-threshold current increases as the threshold
`voltage is lowered.
`When the semiconductor device operates, the ambient
`temperature increases, and the absolute value of the thresh-
`35 old voltage of the MOS transistor is lowered, resulting in
`more serious sub-threshold current leakage. When this sub-
`threshold leakage current increases, the DC current of the
`entire large scale integrated circuit increases, and particu-
`larly in a dynamic type semiconductor memory device, the
`40 stand-by current (current consumed in a stand-by state)
`increases.
`In order to reduce the sub-threshold leakage current, a
`multi-threshold-voltage CMOS arrangement is employed.
`FIG. 55 is a diagram showing a conventional multi-
`45 threshold-voltage CMOS arrangement by way of illustra-
`tion. In FIG. 55, there are provided a main power supply line
`902 transmitting a power supply voltage Vcc, a sub-power
`supply line 904 coupled to main power supply line 902
`through a p-channel MOS transistor 903, a main ground line
`5o 906 transmitting a ground voltage Vss, and a sub-ground
`line 908 coupled to main ground line 906 through an
`n-channel MOS transistor 907. MOS transistor 903 conducts
`when an activation signal /ACT is at an L level, while MOS
`transistor 907 conducts when an activation signal pACT is
`55 at an H level. MOS transistors 903 and 907 each have a
`relatively high threshold voltage (high-Vth). The internal
`circuit operates, with a voltage from one of power supply
`lines 902 and 904 and a voltage from one of ground lines 906
`and 908 used as both operation power supply voltages. In
`60o FIG. 55, as the internal circuit, three-stage, cascaded inverter
`circuits 914a, 914b and 914c are shown. Inverter circuit
`914a includes a p-channel MOS transistor PQ having a
`source coupled to main power supply line 902, and an
`n-channel MOS transistor NQ having a source coupled to
`65 ground line 908. An input signal IN is provided in common
`to the gates of MOS transistors PQ and NQ. Input signal IN
`is set to an L level in a stand-by cycle.
`
`MICRON-1002.040
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`

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`US 6,233,181 B1
`
`Inverter circuit 914b operates using voltages on sub-
`power supply line 904 and main ground line 906 as both
`operation power supply voltages. Inverter circuit 914c oper-
`ates with voltages on main power supply line 902 and
`sub-ground line 908 as both operation power supply volt-
`ages. MOS transist