UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`MICRON TECHNOLOGY, INC.
`
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC
`
`Patent Owner
`
`
`
`Patent No. 6,233,181
`Issue Date: May 15, 2001
`Filed: Feb. 17, 1999
`Inventor: Hideto Hidaka
`Title: SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED FLEXIBLE
`REDUNDANCY SCHEME
`
`Inter Partes Review No. IPR2016-00096
`
`____________________________________________________________
`
`
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`
`
`
`
`

`
`IPR2016-00096: Patent Owner’s Preliminary Response
`
`Table of Contents
`
`Page
`
`I. 
`
`II. 
`
`INTRODUCTION ........................................................................................... 1 
`
`SUMMARY OF THE ‘181 PATENT ............................................................. 2 
`
`A. 
`
`B. 
`
`The Inventions Disclosed in the ‘181 Patent ..................................... 2 
`
`Level of Ordinary Skill in the Art ..................................................... 5 
`
`C.  Claim Interpretation ........................................................................... 6 
`
`1. 
`
`2. 
`
`3. 
`
`“word lines” ................................................................................ 7 
`
`“spare memory cells” .................................................................. 9 
`
`“sense amplifier bands” ............................................................ 10 
`
`III.  THE PETITION FAILS TO ESTABLISH A REASONABLE
`LIKELIHOOD THAT MICRON WILL PREVAIL AS TO THE
`GROUNDS ASSERTED CLAIMS 3 AND 5 ............................................... 12 
`
`A. 
`
`B. 
`
`Legal Standard .................................................................................. 13 
`
`The Petition Fails To Establish That Claim 3 Is Obvious
`Over Sukegawa In View Of Prince Because It Does Not
`Show That Every Element Of The Claim Is Present In the
`Combined References ....................................................................... 14 
`
`1. 
`
`2. 
`
`Neither Sukegawa Nor Prince Discloses Sense Amplifier
`Bands Located Between Memory Blocks ................................. 15 
`
`Neither Sukegawa Nor Prince Discloses Sharing Sense
`Amplifier Bands By Adjacent Memory Blocks In The
`Column Direction ...................................................................... 29 
`
`IV.  THE PETITION FAILS TO PROVIDE REASONED ANALYSIS OF
`FACTS THAT WOULD SATISFY THE PROPOSED CLAIM
`CONSTRUCTIONS ...................................................................................... 31 
`
`V. 
`
`CONCLUSION .............................................................................................. 33 
`
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`Table of Authorities
`
`Page
`
`Cases
`Am. Acad. of Sci. Tech. Ctr., In re,
`367 F.3d 1359 (Fed. Cir. 2004) .............................................................................. 6
`Bass, In re,
`314 F.3d 575 (Fed. Cir. 2002) ................................................................................ 6
`CCS Fitness, Inc. v. Brunswick Corp.,
`288 F.3d 1359 (Fed. Cir. 2002) .............................................................................. 6
`Cuozzo Speed Techs., LLC, In re,
`778 F.3d 1271 (Fed. Cir. 2015) ....................................................................... 6, 12
`Digital-Vending Servs. Int’l LLC v. Univ. of Phoenix, Inc.,
`672 F.3d 1270 (Fed. Cir. 2015) ....................................................................... 9, 12
`Graham v. John Deere Co.,
`383 U.S. 1 (1966) ................................................................................................. 13
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ............................................................................................. 13
`NTP, Inc., In re,
`654 F.3d 1279 (Fed. Cir. 2011) ..................................................................... 14, 31
`Rambus, Inc., In re,
`753 F.3d 1253 (Fed. Cir. 2014) .............................................................................. 6
`Star Scientific, Inc. v. R.J. Reynolds Tobacco Co.,
`655 F.3d 1364 (Fed. Cir. 2011) ............................................................................ 13
`Translogic Tech., Inc., In re,
`504 F.3d 1249 (Fed. Cir. 2007) .............................................................................. 6
`Travelocity.com L.P. et al. v. Cronos Technologies, LLC,
`CBM2014-00082 paper 12 (Oct. 16, 2014) ......................................................... 13
`Vivid Techs. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795 (Fed. Cir. 1999) ..................................................................... 6, 7, 10
`Statutes
`35 U.S.C. § 103 ........................................................................................................ 13
`35 U.S.C. § 313 .......................................................................................................... 1
`Regulations
`37 C.F.R. § 42.100 ..................................................................................................... 6
`37 C.F.R. § 42.107 ..................................................................................................... 1
`37 C.F.R. § 42.108 .................................................................................. 2, 13, 30, 31
`Constitutional Provisions
`
`
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`ii
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`Office Trial Practice Guide,
`77 Fed. Reg. 48,756 (Aug. 14, 2012) ..................................................................... 6
`
`
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`iii
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`I.
`
`INTRODUCTION
`
`Patent Owner Limestone Memory Systems LLC (“LMS”) respectfully
`
`submits this Preliminary Response in accord with 35 U.S.C. § 313 and 37 C.F.R.
`
`§ 42.107, responding to the Petition for Inter Partes Review (the “Petition”) filed
`
`by Micron Technology, Inc. (“Micron” or “Petitioner”) regarding claims of United
`
`States Patent No. 6,233,181 (“the ‘181 patent”)1. Because the Petition incorrectly
`
`characterizes the disclosures of the prior art, it does not demonstrate a reasonable
`
`likelihood that claim 3 of the ‘181 patent is unpatentable. Claim 5 depends from
`
`claim 3 and is therefore not invalid for all of the same reasons as discussed below
`
`
`1 Micron has also filed four other petitions for inter partes review of four other
`
`patents (5,805,504; 5,894,441; 5,943,260; and 6,697,296) at issue in the co-
`
`pending litigation between the parties, Limestone Memory Sys. LLC v. Micron
`
`Tech. Inc., 8:15-cv-00278 (C.D. Cal.) (“the co-pending litigation”). See IPR2016-
`
`00093–IPR2016-00097. The co-pending litigation, as well as 9 other consolidated
`
`suits against other defendants asserting one or more of the patents at issue in the
`
`co-pending litigation, have been stayed pending the outcome of the Board’s
`
`decisions on institution in these IPRs. See Limestone Memory Sys. LLC v. Micron
`
`Tech. Inc. et al., 8:15-cv-00278 (C.D. Cal.), Doc. 69, January 12, 2016 (Order
`
`Granting Motions to Stay Cases Pending Inter Partes Review).
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`for claim 3. Accordingly, at least as to claims 3 and 5, Micron has not met the high
`
`standard required for institution of an inter partes review. 37 C.F.R. § 42.108(c).
`
`II.
`
`SUMMARY OF THE ‘181 PATENT
`
`A. The Inventions Disclosed in the ‘181 Patent
`
`The ‘181 patent discloses a scheme for providing redundancy circuits within
`
`semiconductor memory devices in which the memory array is divided into a
`
`plurality of memory blocks. (Ex. 1001 at 1:6–13.) The ‘181 patent discloses a
`
`number of features, which, when arranged together reduce the overall number of
`
`circuits on the chip. For example, the embodiment of figure 9 discloses shared row
`
`decoders, which reduces the overall number of such row decoders.
`
`In the configuration shown in FIG. 9, spare array SPX# is provided in
`common to normal memory sub-arrays MA#0 to MA#m. As a result,
`if defective rows concentrate in one normal memory sub-array, spare
`word lines included in spare array SPX# can be used for repairing by
`replacement, and therefore the yields of the products can be improved.
`A spare row decoder is shared among a plurality of normal memory
`sub-arrays (row blocks) and therefore the number of spare decoders
`can be reduced.
`
`(Id. at 16:31–39.)
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`
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`(Id. at FIG. 9.) According to the ‘181 patent, the advantage in this arrangement lies
`
`in the increased efficiency of using spare word lines because they are shared
`
`among all of the normal memory blocks. (Id. at 16:65–17:4.)
`
`In another example of a feature that adds to the efficient use of chip space,
`
`the ‘181 patent discloses the use of shared sense amplifier bands.
`
`Sense amplifier bands SAB1 to SABm are provided between memory
`sub-arrays adjacent to one another in the column direction. A sense
`amplifier band SAB0 is provided outside normal memory sub-array
`MA#0-0, and a sense amplifier band SABm+l is provided adjacent to
`normal memory sub-array MA#l-N.
`
`These sense amplifier bands SAB0 to SABm+l have an alternate
`shared sense amplifier arrangement. When one normal memory sub-
`
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`array or row block is selected, the sense amplifiers included in the
`sense amplifier bands provided on both sides are used for sensing
`operation.
`
`(Id. at 17:43–53.) Sense amplifier bands include multiple sense amplifiers for
`
`sensing the information stored in the memory cells of the respective blocks. (Id. at
`
`17:51–53.) By positioning the sense amplifier bands between the memory blocks,
`
`two memory blocks can be read by a single sense amplifier band. (Id. at 18:7–10.)
`
`An additional embodiment is illustrated in figure 15, which illustrates yet
`
`another benefit of the shared sense amplifier architecture.
`
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`4
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`(Id. at FIG. 15.) In this arrangement, defective memory cells are never replaced
`
`using memory cells that share the same sense amplifier band. The written
`
`description explains that erroneous operation of the respective memory blocks is
`
`therefore reduced because access conflicts are prevented in this configuration. (Id.
`
`at 19:50–63.) These architectural features and others are recited in the claims of the
`
`‘181 patent, as discussed further below.
`
`B.
`
`Level of Ordinary Skill in the Art
`
`Petitioner attempts to define the level of ordinary skill in the art (Pet. at 15-
`
`16), but neither the Petition nor the supporting Baker declaration offers any basis
`
`for arriving at any particular level of skill. At most, the Petition is supported by the
`
`conclusory statements of Dr. Baker. (See Pet. at 15-16; see Ex. 1007 at ¶ 17.)
`
`Further, although Dr. Baker apparently has (and had) substantially more
`
`experience than the person of ordinary skill at the time of the invention, neither the
`
`Petition nor the supporting declaration offers any analysis of how the hypothetical
`
`person’s skill would differ from Dr. Baker’s own knowledge and skill. By 1998,
`
`the priority date of the ‘181 patent, Dr. Baker was already an assistant professor at
`
`the University of Idaho with at least seven years of academic and thirteen years of
`
`industry experience. (See Ex. 1008 at .002–.004.)
`
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`C. Claim Interpretation
`
`In an inter partes review, the Board construes claim terms in an unexpired
`
`patent using their broadest reasonable construction in light of the specification of
`
`the patent in which they appear. 37 C.F.R. § 42.100(b); Office Trial Practice
`
`Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012); In re Cuozzo Speed Techs.,
`
`LLC, 778 F.3d 1271, 1282-83 (Fed. Cir. 2015), cert. granted, 577 U.S. ___ (Jan.
`
`15, 2016) (No. 15-446). Only those terms that are in controversy need to be
`
`construed, and only to the extent necessary to resolve the controversy. Vivid Techs.
`
`v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). If interpretation is
`
`necessary, the claim language should be read in light of the specification as it
`
`would be interpreted by one of ordinary skill in the art. In re Rambus, Inc., 753
`
`F.3d 1253, 1255 (Fed. Cir. 2014); In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d
`
`1359, 1364 (Fed. Cir. 2004) (citing In re Bass, 314 F.3d 575, 577 (Fed. Cir.
`
`2002)). There is a “heavy presumption” that a claim term carries its ordinary and
`
`customary meaning. CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366
`
`(Fed. Cir. 2002). The “ordinary and customary meaning” is that which the term
`
`would have to a person of ordinary skill in the art in question in the context of the
`
`entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`
`2007).
`
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`LMS reserves the right to raise other claim construction issues or additional
`
`arguments if trial is instituted, but offers the preliminary analysis below in
`
`response to the constructions proposed in the Petition.
`
`1. “word lines”
` The phrase “word lines” is an element of independent claim 1 and is
`
`therefore also incorporated in dependent claims 2–7. Claim 1 recites, in part, “first
`
`memory blocks including word lines provided corresponding to said rows.”
`
`No construction of word lines should be necessary in deciding this matter.
`
`See Vivid Techs., 200 F.3d at 803. The Petition does not identify any grounds that
`
`turn on the specific construction of this term. (See, e.g., Pet. at 28.) Further, the
`
`Baker declaration offers no analysis of how Sukegawa satisfies the elements of the
`
`proposed claim construction, despite reciting the construction in its claim charts.
`
`(Ex. 1007 at .059 (A-14) (for example, never once identifying the allegedly
`
`necessary “conductive materials that run horizontally”).)
`
`If the Board concludes that the phrase needs construction, a “word line” is a
`
`“connection shared among multiple memory cells.” This proposed construction
`
`relates the memory cells recited in the claims to the word lines, consistent with the
`
`specification.
`
`The Board should not adopt the construction proposed in the Petition
`
`because the proposed construction is imprecise, duplicates existing claim language,
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`and is unduly narrow. The Petition proposes the construction “conductive materials
`
`that run horizontally through a memory device that connect memory cells in a
`
`physical row.” Both the Petition and the supporting Baker declaration conjure this
`
`proposed construction from thin air, with alleged support from two pages in Prince.
`
`Neither of the pages from Prince, however, offer any definition. Prince simply
`
`illustrates general use of the phrase “word line” and does not include any of the
`
`language in the proposed construction.
`
`The Petition provides no reason for requiring the construction to include
`
`“conductive materials that run horizontally through a memory device.” Several
`
`reasons exist for omitting this language. First, in the context of a semiconductor
`
`memory device, a “connection” already encompasses “conductive materials.” Both
`
`the construction proposed in the Petition and LMS’s proposed alternate
`
`construction require a connection. The Petition provides no support for requiring
`
`the additional, narrower construction. Second, nothing in the ‘181 patent requires
`
`the word lines to run “horizontally.” The Petition offers no reason for so narrowing
`
`the claims. In addition, “horizontally” is ambiguous because it has no relation
`
`within the claimed device. Third, the preamble of the claim already supplies the
`
`context of a semiconductor memory device. There is no need to recite that context
`
`again for the word lines. See Digital-Vending Servs. Int’l LLC v. Univ. of Phoenix,
`
`
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`Inc., 672 F.3d 1270, 1275 (Fed. Cir. 2015) (noting “the well-established rule that
`
`‘claims are interpreted with an eye toward giving effect to all terms in the claim’”).
`
`Likewise, the Petition provides no reason for requiring “in a physical row.”
`
`Claim 1 already recites word lines that are “corresponding to said rows.”
`
`Consequently there is no need for including “in a physical row” within the
`
`construction. Id.
`
`For all of the reasons above, the Board should not adopt the construction of
`
`“word lines” proposed in the Petition.
`
`2. “spare memory cells”
`The phrase “spare memory cells” is an element of independent claim 1 and
`
`is therefore also incorporated in dependent claims 2–7. The phrase appears
`
`separately in claims 2, 6, and 7. Claim 1 recites, in part:
`
`a plurality of first spare memory cells arranged in a
`matrix of rows and columns in a particular one of said
`plurality of first memory blocks, each row of said
`plurality of first spare memory cells being capable of
`replacing a defective row including a defective first
`normal memory cell in said plurality of first memory
`blocks.
`
`The Petition does not identify any grounds that turn on the specific
`
`construction of this term. (See, e.g., Pet. at 30.) Further, the Baker declaration
`
`offers no analysis of how Sukegawa satisfies the elements of the proposed claim
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`construction, despite reciting the construction in its claim charts. (Ex. 1007 at
`
`.062–.066 (A-17–A-21).) Accordingly, no construction should be necessary in
`
`deciding this matter, and the Board need not adopt the construction of “spare
`
`memory cells” proposed in the Petition.
`
`3. “sense amplifier bands”
`The phrase “sense amplifier bands” is an element of dependent claim 3 and
`
`is therefore also incorporated in claim 5, which depends therefrom. Claim 3 recites,
`
`in part:
`
`a plurality of sense amplifier bands provided between
`each of said plurality of first memory blocks and each of
`said second memory blocks, and shared by adjacent
`memory blocks in the column direction for sensing and
`amplifying data in each column of the adjacent memory
`block including a selected memory cell when activated.
`
`No construction should be necessary in deciding this matter. See Vivid Techs., 200
`
`F.3d at 803. The Petition does not identify any grounds that turn on the specific
`
`construction of this term. (See, e.g., Pet. at 39–42.) Further, neither the Petition nor
`
`the Baker declaration offers any analysis of how Sukegawa or Prince discloses
`
`“amplifiers along the horizontal direction,” or how those amplifiers “restore
`
`(amplify) [memory cells] to full levels.” (See, e.g., Pet. at 39-42; Ex. 1007 at .075–
`
`.079 (A-30–A-34).)
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`If the Board concludes that the phrase needs construction, a “sense amplifier
`
`band” is a “structure including multiple sense amplifiers.” This construction is
`
`consistent with the claims and the specification of the ’181 patent. Claim 3 already
`
`recites sense amplifier bands with the function of “sensing and amplifying data in
`
`each column of the adjacent memory block including a selected memory cell.” The
`
`only apparent ambiguity in the phrase sense amplifier bands is the structure that
`
`accomplishes this sensing and amplifying function. The specification discloses the
`
`structure, explaining that sense amplifier bands include multiple sense amplifiers
`
`for sensing the information stored in a memory cell.
`
`When one normal memory sub-array or row block is
`selected, the sense amplifiers included in the sense
`amplifier bands provided on both sides are used for
`sensing operation.
`
`(Ex. 1001 at 17:50–53.)
`
`The Board should not adopt the construction proposed in the Petition
`
`because the proposed construction is imprecise and unnecessarily duplicates
`
`existing claim language. The Petition proposes the construction “amplifiers along
`
`the horizontal direction that sense the contents of memory cells and restore
`
`(amplify) them to full levels.”
`
`The Petition provides no reason for requiring the proposed construction.
`
`Several reasons exist for omitting the proposed definitional language. First,
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`nothing in the ‘181 patent requires the sense amplifier bands to run “horizontally.”
`
`The Petition offers no reason for so narrowing the claims. In addition,
`
`“horizontally” is ambiguous because it is not oriented relative to any structure
`
`recited in the claimed device. Second, the phrase “sense the contents of memory
`
`cells and restore (amplify) them” adds nothing to the existing claim language. As
`
`discussed above, the claim language already clearly requires “sensing and
`
`amplifying data in each column of the adjacent memory block including a selected
`
`memory cell.” See Digital-Vending, 672 F.3d at 1275 (construction must give
`
`effect to all terms in the claim). Lastly, the phrase “to full levels” is ambiguous and
`
`unduly narrow, especially where the Petition cannot point to a reason to apply a
`
`narrow definition to such a term. Cuozzo Speed Techs., 778 F.3d at 1282-83
`
`(broadest reasonable interpretation applies in inter partes review proceedings).
`
`For all of the reasons above, the Board should not adopt the construction of
`
`“sense amplifier bands” proposed in the Petition.
`
`III. THE PETITION FAILS TO ESTABLISH A REASONABLE
`LIKELIHOOD THAT MICRON WILL PREVAIL AS TO THE
`GROUNDS ASSERTED CLAIMS 3 AND 5
`
`Inter partes review should not be granted with respect to claim 3, at
`
`minimum, because the Petition does not demonstrate a reasonable likelihood of
`
`success. Claim 5 depends from claim 3 and therefore includes all of the elements
`
`of claim 3 in addition to others. Claim 5 is therefore also not invalid for the same
`
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`reasons as claim 3. With respect to the alleged ground of invalidity, the Petition
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`mischaracterizes the disclosures of Sukegawa and Prince and therefore fails to
`
`address each element of the claim.
`
`A.
`
`Legal Standard
`
`As the Petitioner, Micron bears the burden of demonstrating a reasonable
`
`likelihood that it would prevail in showing unpatentability on the grounds asserted
`
`in its Petition. 37 C.F.R. § 42.108(c); See Travelocity.com L.P. et al. v. Cronos
`
`Technologies, LLC, CBM2014-00082 paper 12 at 9-10 (Oct. 16, 2014) (denying
`
`request for rehearing after declining to institute trial, notwithstanding that the
`
`grounds had not been argued in Patent Owner’s Preliminary Response).
`
`Under 35 U.S.C. § 103, Petitioner must prove that the claimed subject matter
`
`would have been obvious to a person of ordinary skill in the art at the time of the
`
`invention. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). In considering
`
`obviousness, the Board must determine the scope and content of the prior art,
`
`differences between the prior art and the claims and the level of ordinary skill in
`
`the pertinent art, as well as consider any objective indicia of nonobviousness.
`
`Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`
`Importantly, the obviousness inquiry must be taken without any “hint of
`
`hindsight,” Star Scientific, Inc. v. R.J. Reynolds Tobacco Co., 655 F.3d 1364, 1375
`
`(Fed. Cir. 2011), so as to avoid “reconstruction by using the patent in suit as a
`
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`guide through the maze of prior art references, combining the right references in
`
`the right way so as to achieve the result of the claims in suit.” In re NTP, Inc., 654
`
`F.3d 1279, 1299 (Fed. Cir. 2011) (internal citation omitted).
`
`B.
`
`The Petition Fails To Establish That Claim 3 Is Obvious Over
`Sukegawa In View Of Prince Because It Does Not Show That
`Every Element Of The Claim Is Present In the Combined
`References
`
`Neither Sukegawa nor Prince discloses the element of claim 3 reciting “a
`
`plurality of sense amplifier bands provided between each of said plurality of first
`
`memory blocks and each of said second memory blocks, and shared by adjacent
`
`memory blocks in the column direction.” (Emphasis added.) Claim 3 depends from
`
`claim 2, which depends from claim 1. The ‘181 patent’s figure 15, illustrated
`
`below, discloses structure that corresponds to claims 1, 2, and 3. First, claim 1
`
`recites “a plurality of first memory blocks,” which are illustrated below in yellow.
`
`Second, claim 2 recites “a plurality of second memory blocks arranged
`
`alternatively with said plurality of first memory blocks along the column
`
`direction,” which are illustrated below in red. Lastly, the sense amplifier bands
`
`recited in claim 3 are illustrated below in purple.
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`
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`(Ex. 1001 at FIG. 15.) The Petition fails to identify sense amplifiers in the prior art
`
`that correspond to the claimed sense amplifiers.
`
`1. Neither Sukegawa Nor Prince Discloses Sense Amplifier Bands
`Located Between Memory Blocks
`
`Claim 3 of the ‘181 patent recites, in part, “a plurality of sense amplifier
`
`bands provided between each of said plurality of first memory blocks and each of
`
`said second memory blocks.” The Petition argues that Sukegawa discloses sense
`
`amplifiers between each memory block. (Pet. at 40.) The Petition argues
`
`alternatively that placing sense amplifiers between memory blocks would have
`
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`been obvious in view of Prince. (Pet. at 41.) Neither reference, however, discloses
`
`sense amplifier bands located between the memory blocks.
`
`As a first matter, Sukegawa’s written disclosure is utterly silent as to the
`
`location or even the existence of sense amplifiers or sense amplifier bands. In
`
`concluding that Sukegawa discloses sense amplifier bands located between
`
`memory blocks, neither the Petition nor Dr. Baker’s declaration points to any text
`
`from the written description. (Pet. at 39–40; Ex. 1007 at .075–.079 (A-30–A-34).)
`
`Rather than point to actual evidence within Sukegawa, the Petition and the
`
`Baker declaration rely upon misleading annotation of the drawing figures from
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`Sukegawa. In particular, both documents annotate Sukegawa’s figure 1 in several
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`misleading ways by incorrectly orienting the memory blocks within each quadrant.
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`Both the Petition and the Baker declaration incorrectly orient the memory
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`blocks within each quadrant to be between the heavy lines labeled “S/A.”
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`(Pet. at 40; Ex. 1007 at .050 (A-5), .076 (A-31).) Sukegawa explains that:
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`
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`FIG. 1 shows a 64M bits dynamic random access
`memory chip known as 64M DRAM prepared using the
`submicron technology. This chip is equally divided to
`eight quadrants of 8M bits. Each of the eight memory
`quadrants contains eight 1M bits memory blocks. Each
`memory block is made of two 512K bits portions.
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`(Ex. 1005 at 1:39–44.) Thus, each of the illustrated quadrants should be divided
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`into eight memory blocks, as illustrated below.
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`1
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`5
`6
`7
`8
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`(Ex. 1005 at FIG. 1 (excerpted and annotated to show the correct orientation of
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`memory blocks).) Any other eight-way division of the quadrant simply does not
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`align with the lines in the drawing figure. As illustrated above, the heavy “S/A”
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`line appears within the last block, not between.
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`If one adopts the orientation of the memory blocks proposed in the Petition,
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`the memory blocks simply do not line up to illustrate the disclosed eight memory
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`blocks per quadrant.
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`1
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`6
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`9
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`1
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`9
`10
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`(Ex. 1005 at FIG. 1 (excerpted and annotated to show the incorrect orientation of
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`memory blocks proposed in the Petition).) As illustrated above, the orientation
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`selected in the Petition results in ten memory blocks (green numbering, above), or
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`nine memory blocks if one assumes the column decoders do not divide the middle
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`block (blue numbering, above).
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`In short, if sense amplifier bands existed between each of eight memory
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`blocks, the quadrant depicted above would show either seven or nine of the heavy
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`sense amplifier lines. But that is not what is depicted. The figure shows exactly
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`eight sense amplifier bands, each residing within a single memory block. Keeping
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`with the written description, the sense amplifier band divides the 1M memory
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`blocks into two 512K bit halves.2 (See Ex. 1005 at 1:41–44 (“Each memory block
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`is made of two 512K bits portions.”).) No subject matter expertise is required to
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`observe that the Petition incorrectly characterizes this aspect of Sukegawa. The
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`illustrated memory blocks are not oriented between the heavy “S/A” lines.
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`As with the location of the memory block in quadrant 6, the Petition and Dr.
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`Baker’s declaration mislabel the location of the memory blocks in the call-out view
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`section of Sukegawa’s figure 1.
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`2 Even if each 512K bit half of the memory blocks were considered to be a
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`“memory block” as claimed, the device would not have “sense amplifier bands
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`between each of said plurality of first memory blocks and each of said second
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`memory blocks” as claimed because only one side of each 512K bit portion is
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`adjacent to a sense amplifier band in Watanabe.
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`IPR2016-00096: Patent Owner’s Preliminary Response
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`(Pet. at 40; Ex. 1007 at .076 (A-31) (annotated to indicate the erroneous labels).)
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`Although it offers no support for its conclusion, the Petition appears to correctly
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`identify the location of the sense amplifier bands. (See Pet. at 40; Ex. 1007 at .076
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`(A-31).)
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`(Ex. 1005 at FIG. 1 (excerpted to show “LOCAL I/O” label pointing at the heavy
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`“S/A” line in quadrant 8.) As illustrated, the local I/O appears to coincide with the
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`sense amplifier bands.
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`The Petition does not, however, offer any evidence from Sukegawa’s written
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`description or drawing figures to indicate that the local I/O or the sense amplifier
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`structures are located between memory blocks. In fact, the opposite appears to be
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`true, as illustrated below.
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`6
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`7
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`8
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`(Ex. 1005 at FIG. 1 (excerpted and annotated).) The blocks in the call-out view
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`section align as illustrated with the blocks shown in quadrant 6. As discussed
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`above, sense amplifier bands coincide with the local I/O data lines running from
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`left to right in the call-out view, between the I/O switches. Further, the circled
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`arrow above makes this arrangement explicit. In light of the memory block
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`boundaries illustrated above, the local I/O lines and the “S/A” bands are within the
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`memory block, as illustrated below. The memory block boundaries indicated in the
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`Petition are without any support whatsoever. Because it mislabels the orientation
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`of memory blocks within Sukegawa’s drawing figures, the Petition fails to
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`establish that Sukegawa discloses the claimed sense amplifiers.
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`Figure 1 from Sukegawa’s Japanese priority document supports the
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`conclusions above and makes several facts even more clear.
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`(Ex. 2001 at .006 (FIG. 1).)
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`1. Local I/O lines
`clearly within
`block boundaries.
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`2. Memory block
`boundaries line up
`with the call-out
`arrow.
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`3. “S/A” clearly
`refers to the heavy
`black band.
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`1
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`2
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`3
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`1
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`5
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`6
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`(Ex. 2001 at .006 (excerpt of FIG. 1, annotated to illustrate teachings of
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`Sukegawa’s Japanese priority document).) First, the local I/O lines in the call-out
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`view of the figure are clearly located within the memory block boundaries. This
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`emphasizes that the sense amplifiers and the local I/O lines are located in the
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`middle of the memory block. Second, the arrow calling out the block boundaries in
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`the call-out view is even more clearly not connected to the sense amplifier bands in
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`quadrant 6. Third, the heavy lines labeled “S/A” in