UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`MICRON TECHNOLOGY, INC.
`Petitioner
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC
`Patent Owner
`
`________________________
`
`Case IPR. No. Unassigned
`U.S. Patent No. 5,894,441
`Title: SEMICONDUCTOR MEMORY DEVICE
`WITH REDUNDANCY CIRCUIT
`
`
`
`
`
`
`
`________________________
`
`Petition For Inter Partes Review of U.S. Patent No. 5,894,441 Under
`35 U.S.C §§ 311-319 and 37 C.F.R. §§ 42.1-.80, 42.100-.123
`
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
`
`1.
`
`2.
`
`3.
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`4.
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`5.
`
`6.
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`7.
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`8.
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`Table of Contents
`
`INTRODUCTION ........................................................................................... 1
`
`REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW ........ 1
`
`2.1. Grounds for Standing (37 C.F.R. § 42.104(a)) ..................................... 1
`
`2.2. Notice of Lead and Backup Counsel and Service Information ............. 1
`
`2.3. Notice of Real-Parties-in-Interest (37 C.F.R. § 42.8(b)(1)) .................. 2
`
`2.4. Notice of Related Matters (37 C.F.R. § 42.8(b)(2)) .............................. 2
`
`2.5. Fee for Inter Partes Review ................................................................... 3
`
`2.6. Proof of Service ..................................................................................... 4
`
`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`(§ 42.104(B)) ................................................................................................... 4
`
`OVERVIEW OF THE 441 PATENT .............................................................. 4
`
`PROSECUTION HISTORY ........................................................................... 9
`
`CLAIM CONSTRUCTION ............................................................................ 9
`
`6.1. Applicable Law ..................................................................................... 9
`
`6.2. Construction of Claim Terms .............................................................. 10
`
`6.2.1. “transfer gate” (claims 3 and 13) ..............................................10
`PERSON HAVING ORDINARY SKILL IN THE ART ............................. 11
`
`DESCRIPTION OF THE PRIOR ART ........................................................ 11
`
`8.1. U.S. PATENT NO. 5,270,975 (“MCADAMS”) ................................. 11
`
`8.2.
`
`JAPANESE PATENT APPLICATION NO. H06-052696
`(“MINAMI”) ....................................................................................... 14
`
`9.
`
`GROUND #1: CLAIMS 1-3 AND 5 OF THE 441 PATENT ARE
`UNPATENTABLE AS ANTICIPATED BY MCADAMS .......................... 16
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`9.1. Claim 1 is anticipated by McAdams ................................................... 16
`
`9.1.1. [1.P] “A semiconductor memory device comprising, . . .” .......16
`9.1.2. [1.1] “a plurality of column selection lines, at least one
`redundant column selection line,”.............................................16
`9.1.3. [1.2] “a column decoder for activating one of said
`plurality of column selection lines in response to a
`column address,” .......................................................................18
`9.1.4. [1.3] “a first circuit generating a detection signal when
`the column address of a defective column selection line is
`supplied,” ..................................................................................18
`9.1.5. [1.4] “and a second circuit activating said redundant
`column selection line in response to said detection signal
`and at least a part of said row address.” ....................................19
`9.2. Claim 2 is anticipated by McAdams ................................................... 22
`
`9.2.1. [2.0] “The semiconductor memory device as claimed in
`claim 1, wherein said first circuit includes a fuse block
`storing said column address of said defective column
`selection line to generate said detection signal.” ......................22
`9.3. Claim 3 is anticipated by McAdams ................................................... 23
`
`9.3.1. [3.0] “The semiconductor memory device as claimed in
`claim 2, wherein said second circuit including a transfer
`gate controlled by said part of said row address to
`transfer said detection signal to activate said redundant
`column selection line.” ..............................................................23
`9.4. Claim 5 is anticipated by McAdams ................................................... 24
`
`9.4.1. [5.0] “The semiconductor memory device as claimed in
`claim 1, wherein said part of said row address includes a
`most significant bit of said row address.” .................................24
`10. GROUND #2: CLAIMS 3 AND 6-15 OF THE 441 PATENT ARE
`UNPATENTABLE AS OBVIOUS OVER MCADAMS IN VIEW OF
`MINAMI ........................................................................................................ 26
`
`10.1. Claim 3 is obvious over McAdams in view of Minami ...................... 30
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`[3.0] “The semiconductor memory device as
`10.1.1.
`claimed in claim 2, wherein said second circuit including
`a transfer gate controlled by said part of said row address
`to transfer said detection signal to activate said redundant
`column selection line.” ..............................................................30
`10.2. Claim 6 is obvious over McAdams in view of Minami ...................... 32
`
`[6.0] “A semiconductor memory device
`10.2.1.
`comprising:” ..............................................................................32
`10.2.2.
`[6.1] “a plurality of word lines including at least
`first and second word lines; a plurality of bit lines
`including at least first and second bit lines;” ............................32
`10.2.3.
`[6.2] “a plurality of redundant bit lines including
`at least first and second redundant bit lines;” ...........................35
`10.2.4.
`[6.3] “a plurality of memory cells each of which
`is disposed on intersections of said word lines and bit
`lines; a plurality of redundant memory cells each of
`which is disposed on intersections of said word lines and
`redundant bit lines;” ..................................................................36
`10.2.5.
`[6.4] “a plurality of column selection lines
`including at least a first column selection line; said first
`and second bit lines being selected when said first
`column selection line is activated, a redundant column
`selection line; said first and second redundant bit lines
`being selected when said redundant column selection line
`is activated,” ..............................................................................37
`10.2.6.
`[6.5] “a column decoder activating said first
`column selection line in response to a first column
`address when said first word line is activated; and” .................39
`10.2.7.
`[6.6] “a column redundancy decoder activating
`said redundant column selection line in response to said
`first column address when said second word line is
`activated.” .................................................................................42
`10.3. Claim 7 is obvious over McAdams in view of Minami ...................... 44
`
`[7.0] “The semiconductor memory device as
`10.3.1.
`claimed in claim 6, wherein said first word line intersects
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
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`said first bit line and said first redundant bit line without
`intersecting said second bit line and said second
`redundant bit line, said second word line intersecting said
`second bit line and said second redundant bit line without
`intersecting said first bit line and said first redundant bit
`line”
`44
`10.4. Claim 8 is obvious over McAdams in view of Minami ...................... 45
`
`[8.0] “The semiconductor memory device as
`10.4.1.
`claimed in claim 7, wherein said column decoder is
`inhibited to activate said first column selection line in
`response to said first column address when said second
`word line is activated. ...............................................................46
`10.5. Claim 9 is obvious over McAdams in view of Minami ...................... 47
`
`[9.0] “The semiconductor memory device as
`10.5.1.
`claimed in claim 7, wherein said plurality of bit lines
`further includes third and fourth bit lines, said plurality of
`column selection lines further including a second column
`selection line, said third and fourth bit lines being
`selected when said second column selection line is
`activated, said column decoder activating said second
`column selection line in response to a second column
`address when said second word line is activated, said
`column redundancy decoder activating said redundant
`column selection line in response to said second column
`address when said first word line is activated.” ........................47
`10.6. Claim 10 is obvious over McAdams in view of Minami .................... 50
`
`[10.0] “The semiconductor memory device as
`10.6.1.
`claimed in claim 9, wherein said column decoder is
`inhibited to activate said first column selection line in
`response to said first column address when said second
`word line is activated and inhibited to activate said
`second column selection line in response to said second
`column address when said first word line is activated. ............50
`10.7. Claim 11 is obvious over McAdams in view of Minami .................... 51
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`[11.0] “The semiconductor memory device as
`10.7.1.
`claimed in claim 9, wherein said first word line further
`intersects said third bit line without intersecting said
`fourth bit line, said second word line further intersecting
`said fourth bit line without intersecting said third bit
`line.”
`51
`10.8. Claim 12 is obvious over McAdams in view of Minami .................... 53
`
`[12.0] “The semiconductor memory device as
`10.8.1.
`claimed in claim 9, wherein said column redundancy
`decoder includes first and second fuse blocks, said first
`fuse block activating a first matching signal in response
`to said first column address, and said second fuse block
`activating a second matching signal in response to said
`second column address.” ...........................................................53
`10.9. Claim 13 is obvious over McAdams in view of Minami .................... 55
`
`[13.0] “The semiconductor memory device as
`10.9.1.
`claimed in claim 12, wherein said column redundancy
`decoder further includes first and second transfer gates
`said first transfer gate being activated to transfer said first
`matching signal to said redundant column selection line
`responsive to said second word line being activated said
`second transfer gate being activated to transfer said
`second matching signal to said redundant column
`selection line responsive to said first word line being
`activated.” .................................................................................55
`10.9.1.1. McAdams discloses this limitation if “transfer
`gate” means “logic that transfers the logic value
`of a signal” ..................................................................56
`10.9.1.1. McAdams in view of Minami discloses this
`limitation if “transfer gate” means “transistor
`which transfers a signal from its source to its
`drain (or drain to its source)” .....................................57
`10.10. Claim 14 is obvious over McAdams in view of Minami .................... 58
`
`[14.0] “The semiconductor memory device as
`10.10.1.
`claimed in claim 6, wherein said second bit line is
`defective. ...................................................................................58
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`10.11. Claim 15 is obvious over McAdams in view of Minami .................... 59
`
`[15.0] “The semiconductor memory device as
`10.11.1.
`claimed in claim 9, wherein said second and third bit
`lines are defective......................................................................59
`11. CONCLUSION .............................................................................................. 60
`
`
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
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`Exhibit List
`
`Description
`
`U.S. Patent No. 5,895,441 (“the 441 Patent”)
`
`File History for U.S. Patent No. 5,894,441
`
`Declaration of Dr. R. Jacob Baker (“Baker Decl.”)
`
`Curriculum Vitae of Dr. R. Jacob Baker
`
`U.S. Patent No. 5,270,975 (“McAdams”)
`
`Japanese Patent Application No. H06-052696 (“Minami”)
`
`Excerpts from Betty Prince, Semiconductor Memories (2d ed.
`1992) (“Prince”)
`
`Micron
`Exhibit #
`
`MICRON-
`1001
`
`MICRON-
`1002
`
`MICRON-
`1003
`
`MICRON-
`1004
`
`MICRON-
`1005
`
`MICRON-
`1006
`
`MICRON-
`1007
`
`
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
`
`1.
`
`INTRODUCTION
`
`Pursuant to 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42.100, Micron
`
`Technology, Inc. (“Petitioner”) hereby petitions the Patent Trial and Appeal Board
`
`to institute an inter partes review of claims 1-3 and 5-15 of U.S. Patent No.
`
`5,894,441, titled “Semiconductor Memory Device With Redundancy Circuit”
`
`(MICRON-1001, “the 441 Patent”), and cancel those claims as unpatentable.
`
`2.
`
`REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW
`2.1. Grounds for Standing (37 C.F.R. § 42.104(a))
`Petitioner certifies that the 441 Patent is available for inter partes review and
`
`that Petitioner is not barred or estopped from requesting inter partes review of the
`
`challenged claims of the 441 Patent on the grounds identified herein.
`
`2.2. Notice of Lead and Backup Counsel and Service Information
`Pursuant to 37 C.F.R. §§ 42.8(b)(3), 42.8(b)(4), and 42.10(a), Petitioner
`
`provides the following designation of Lead and Back-Up counsel.
`
`Lead Counsel
`Jeremy Jason Lang (Reg. No. 73604)
`(jason.lang@weil.com)
`
`Postal & Hand-Delivery Address:
`Weil, Gotshal & Manges LLP
`201 Redwood Shores Parkway
`Redwood Shores, CA 94065
`T: 650-802-3237; F: 650-802-3100
`
`Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney for the Petitioner is
`
`Back-Up Counsel
`Justin L. Constant (Reg. No. 66883)
`(justin.constant@weil.com)
`
`Postal & Hand-Delivery Address:
`Weil, Gotshal & Manges LLP
`700 Louisiana, Suite 1700
`Houston, TX 77002
`T: 713-546-5217; F: 713-224-9511
`
`attached.
`
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
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`2.3. Notice of Real-Parties-in-Interest (37 C.F.R. § 42.8(b)(1))
`Petitioner, Micron Technology, Inc., is the real-party-in-interest. No other
`
`parties exercised or could have exercised control over this petition; no other parties
`
`funded or directed this petition. (See Office Patent Trial Practice Guide, 77 Fed.
`
`Reg. 48759-60.)
`
`2.4. Notice of Related Matters (37 C.F.R. § 42.8(b)(2))
`Limestone has asserted the 441 Patent and U.S. Patent Nos. 5,805,504 (“the
`
`504 Patent”), 6,233,181 (“the 181 Patent”), 5,943,260 (“the 260 Patent”), and
`
`6,697,296 (“the 296 Patent”) (collectively, “the asserted patents”) against Micron
`
`in a co-pending litigation, Limestone Memory Sys. LLC v. Micron Tech., Inc., 8:15-
`
`cv-00278 (C.D. Cal.) (“Co-Pending Litigation”). Limestone has also asserted one
`
`or more of the asserted patents in the following actions: Limestone Memory Sys.
`
`LLC v. OCZ Storage Solutions, Inc., 8:15-cv-00658 (C.D. Cal.) (the 504, 441, 181
`
`and 296 Patents); Limestone Memory Sys. LLC v. PNY Techs., Inc., 8:15-cv-00656
`
`(C.D. Cal.) (the 260 Patent); Limestone Memory Sys. LLC v. Lenovo (US) Inc.,
`
`8:15-cv-00650 (C.D. Cal.) (the 504, 441, 260, 181, and 296 Patents); Limestone
`
`Memory Sys. LLC v. Kingston Tech. Co. Inc., 8:15-cv-00654 (C.D. Cal.) (the 504,
`
`441, 260, 181, and 296 Patents); Limestone Memory Sys. LLC v. Transcend Info.,
`
`Inc. (California), 8:15-cv-00657 (C.D. Cal.) (the 260 Patent); Limestone Memory
`
`Sys. LLC v. Acer America Corp., 8:15-cv-00653 (C.D. Cal.) (the 504, 441, 260,
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
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`181, and 296 Patents); Limestone Memory Sys. LLC v. Dell Inc., 8:15-cv-00648
`
`(C.D. Cal.) (the 504, 441, 260, 181, and 296 Patents); Limestone Memory Sys. LLC
`
`v. Hewlett-Packard Co., 8:15-cv-00652 (C.D. Cal.) (the 504, 441, 260, 181, and
`
`296 Patents); and Limestone Memory Sys. LLC v. Apple Inc., 8:15-cv-01274 (C.D.
`
`Cal.) (the 504, 441, 181, and 296 Patents).
`
`In addition to this Petition, Petitioner is filing petitions for inter partes
`
`review of each asserted patent in the Co-Pending Litigation: Petition for Inter
`
`Partes Review of U.S. Patent No. 5,805,504, IPR2015-Unassigned (to be filed
`
`concurrently); Petition for Inter Partes Review of U.S. Patent No. 6,233,181,
`
`IPR2015-Unassigned (to be filed concurrently); Petition for Inter Partes Review of
`
`U.S. Patent No. 5,943,260, IPR2015-Unassigned (to be filed concurrently); and
`
`Petition for Inter Partes Review of U.S. Patent No. 6,697,296, IPR2015-
`
`Unassigned (to be filed concurrently).
`
`The 441 Patent claims priority to foreign patent application JP-09-081203.
`
`The 441 Patent does not claim priority to any other U.S. patent applications.
`
`2.5. Fee for Inter Partes Review
`The Director is authorized to charge the fee specified by 37 C.F.R.
`
`§ 42.15(a), and any other required fees, to Deposit Account No. 506499.
`
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
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`2.6. Proof of Service
`Proof of service of this petition on the patent owner at the correspondence
`
`address of record for the 441 Patent is attached.
`
`3.
`
`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`(§ 42.104(B))
`Ground #1: Claims 1-3, and 5 are invalid under (pre-AIA) 35 U.S.C.
`
`§ 102(b) on the ground that they are anticipated by U.S. Patent No. 5,270,975, to
`
`McAdams (“McAdams”), entitled “Memory Device Having A Non-Uniform
`
`Redundancy Decoder Arrangement,” filed with the USPTO on August 13, 1992,
`
`issued December 14, 1993. McAdams is attached as MICRON-1005.
`
`Ground #2: Claims 3 and 6-15 are invalid under (pre-AIA) 35 U.S.C. § 103
`
`on the ground that they are obvious over McAdams in view of Japanese Patent
`
`Application No. H06-052696 (“Minami”), which was filed on July 31, 1992 and
`
`was published on February 25, 1994. Minami is attached as MICRON-1006.
`
`These grounds are explained below and are supported by the Declaration of
`
`Dr. R. Jacob Baker (MICRON-1003, “Baker Decl.”).
`
`4. OVERVIEW OF THE 441 PATENT
`The 441 Patent was filed on March 31, 1998 and issued on April 13, 1999.
`
`The 441 Patent is directed to a semiconductor memory device that purportedly
`
`enhances the relief efficiency of defective bit lines by means of redundant bit lines.
`
`MICRON-1001, 441 Patent at Abstract.
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`In a semiconductor memory device, memory cells are located in a grid at the
`
`intersection of word lines and bit lines. MICRON-1001, 441 Patent at Figure 2;
`
`MICRON-1003, Baker Decl. at ¶ 27. As a general matter, word lines run in the
`
`row direction whereas bit lines run in the column direction. MICRON-1003,
`
`Baker Decl. at ¶¶ 27-28. Column selection lines are associated with the bit lines
`
`and also run in the column direction. MICRON-1001, 441 Patent at Figure 2;
`
`MICRON-1003, Baker Decl. ¶¶ 27-28.
`
`Almost all semiconductor memory devices include defective components.
`
`MICRON-1001, 441 Patent at 1:14-17; MICRON-1003, Baker Decl. ¶ 29. So that
`
`the devices can operate with such defects, it has long been general practice to
`
`include redundancy circuits that allow the manufacturer to disable the use of a
`
`defective component and replace it with a redundant one. MICRON-1001, 441
`
`Patent at 1:18-22; MICRON-1003, Baker Decl. ¶¶ 29, 30. To replace the
`
`maximum number of defective word lines or bit lines, it is desirable to include as
`
`many redundant components, e.g., redundant word lines and/or bit lines, as
`
`practicable. MICRON-1001, 441 Patent at 1:34-37; MICRON-1003, Baker Decl. ¶
`
`29. However, these redundant word and/or bit lines, and the corresponding
`
`redundancy circuitry to activate and utilize those redundant components come at a
`
`cost since they require additional silicon space. MICRON-1001, 441 Patent at
`
`1:37-42; MICRON-1003, Baker Decl. ¶ 30. The 441 Patent purports to increase
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`the relief efficiency of redundant bit lines so that fewer redundant lines are needed,
`
`thus reducing cost and space needed for redundancy circuitry. MICRON-1001,
`
`441 Patent at 2:8-13; MICRON-1003, Baker Decl. ¶ 30.
`
`The alleged invention is directed to a semiconductor device with a divided
`
`bit line architecture. MICRON-1001, 441 Patent at 3:1-2. This means that, “in the
`
`same column, a bit line is divided into plural parts . . . .” MICRON-1001, 441
`
`Patent at 3:23-27. This structure is depicted in Figure 1.
`
`
`MICRON-1001, 441 Patent at Figure 1 (annotated).
`
`The above annotated Figure 1 depicts a single column selection line (122)
`
`that is connected to multiple sense amplifiers (124, 126). MICRON-1001, 441
`
`Patent at 3:22-34; MICRON-1003, Baker Decl. ¶ 32. These sense amplifiers are
`
`each connected to different bit lines. Id. These bit lines, respectively, intersect
`
`two different word lines (118, 120). MICRON-1001, 441 Patent at 3:18-34;
`
`MICRON-1003, Baker Decl. ¶ 32. The memory cells (MC) are at the intersection
`
`of the word lines and the bit lines. Id. This is called a divided bit line architecture
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`because there are multiple bit lines along a single column that are selected by a
`
`single column selection line. MICRON-1003, Baker Decl. ¶¶ 31-32.
`
`When a memory cell is written or read, a column and row address are
`
`provided that specify the particular memory cell. MICRON-1003, Baker Decl.
`
`¶ 33; MICRON-1001, 441 Patent at 3:6-9. As shown in Figure 1, which shows a
`
`prior art architecture, the row address X is provided to the row decoder 106 which
`
`activates the appropriate word line, and the column address Y is provided to the
`
`column decoder 108 which activates the designated column select line. MICRON-
`
`1001, 441 Patent at 3:9-16. “[W]hen the column selection line 122 is activated in
`
`response to a Y address, [multiple] sense amplifiers are selected simultaneously.”
`
`Id. at 3:28-31. “However, only the data corresponding to an activated word line is
`
`selected finally out of the [multiple] selected sense amplifiers, and is readout.” Id.
`
`at 3:32-34.
`
`As shown in Figure 1, the column address Y is also provided to a
`
`redundancy column decoder 116. MICRON-1003, Baker Decl. ¶ 34; MICRON-
`
`1001, 441 Patent at 3:6-9. If the column address corresponds to a column with a
`
`defective bit line, then the column redundancy decoder causes a redundant column
`
`selection line (with redundant bit lines) to be activated. MICRON-1003, Baker
`
`Decl. ¶ 35; MICRON-1001, 441 Patent at 3:53-60. The regular column decoder
`
`108 is also inhibited from activating the column with a defective bit line. Id.
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
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`According to the 441 Patent, the problem with the approach depicted in
`
`Figure 1 is that all of the bit lines along a single column are replaced even if only
`
`one of the bit lines is defective. MICRON-1001, 441 Patent at 3:62-65. The 441
`
`Patent purports to correct this inefficiency by enabling a single redundant column
`
`selection line to partially replace components from different columns. MICRON-
`
`1003, Baker Decl ¶ 37; see also MICRON-1001, 441 Patent at 7:25-29 (“In other
`
`words, half of the single redundant column selection line 230 replaces half of the
`
`column selection line 222, and the remaining half of the same redundant column
`
`selection line 230 replaces half of the column selection line 290.”). This is
`
`accomplished by using a portion of the row address in addition to the column
`
`address when determining whether to activate a redundant column selection line.
`
`See MICRON-1001, 441 Patent at Figure 2 (showing XA0 and XA1, part of the
`
`row address X, being passed to the column redundancy decoder 216); MICRON-
`
`1003, Baker Decl. ¶ 38. If the portion of the row address is associated with a
`
`selection of rows connected to a defective bit line and the column address is
`
`associated with a defective bit line, then the redundant column selection line is
`
`activated. MICRON-1003, Baker Decl. ¶ 39. However, if the portion of the row
`
`address is not associated with a selection of rows connected to a defective bit line
`
`and the column address is associated with a defective bit line, then the regular
`
`column selection line is activated. Id. The effective result is that only the portion
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
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`of the column select line with the defective bit line is replaced with a portion of the
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`redundant column selection line as opposed to replacement of the entire line. Id. ¶
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`40. This allows the other portions of the redundant column selection line to be
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`used to correct other defects in other lines, thus increasing efficiency. Id.
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`5.
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`PROSECUTION HISTORY
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`The examiner allowed all 15 claims in the first office action without any
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`rejections. The examiner noted in the Reasons for Allowance that “[t]he PRIOR
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`ART fails to disclose or suggest such a column redundant circuit responsive to the
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`row address as described above . . . .” MICRON-1002, 11-23-1998 Notice of
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`Allowability at .090.
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`6.
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`CLAIM CONSTRUCTION
`6.1. Applicable Law
`A claim subject to inter partes review is given the “broadest reasonable
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`construction in light of the specification of the patent in which it appears.”1 37
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` Any ambiguity regarding
`C.F.R. § 42.100(b).
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`1 The district court, in contrast, affords a claim term its “ordinary and customary
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`the “broadest reasonable
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`meaning . . . to a person of ordinary skill in the art in question at the time of the
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`invention.” Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005) (en
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`banc). Petitioner expressly reserves the right to argue different or additional claim
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`construction positions under this standard in district court.
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
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`construction” of a claim term is resolved in favor of the broader construction
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`absent amendment by the patent owner. Final Rule, 77 Fed. Reg. 48680, 48699
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`(Aug. 14, 2012).
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`6.2. Construction of Claim Terms
`All claim terms not specifically addressed in this Section have been
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`accorded their broadest reasonable interpretation as understood by a person of
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`ordinary skill and consistent with the specification of the 441 Patent. Petitioner
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`respectfully submits that the following term shall be construed for this IPR:
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`6.2.1. “transfer gate” (claims 3 and 13)
`The term “transfer gate” is a limitation of claims 3 and 13 of the 441 Patent.
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`The 441 Patent does not provide an explicit definition of the term “transfer gate.”
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`Petitioner respectfully submits that the plain and ordinary meaning of this term is
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`“logic that transfers the logic value of a signal.”
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`The specification and claims describe the operation of the transfer gates
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`disclosed in the patent as transferring a signal. For example, claim 13 requires that
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`the “first transfer gate being activated to transfer said first matching signal to
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`said redundant column selection line . . . .”2 MICRON-1001, 441 Patent at claim
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`13. Further, the specification describes the functionality of transfer gate 310 as
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`outputting “the matching signal 306 as the YRED when XAO is at the high level” and
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`2 Throughout this Petition, emphasis is added unless otherwise noted.
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
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`the functionality of the transfer gate 312 as outputting “the matching signal 308 as
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`the YRED when XA1 is at the high level.” MICRON-1001, 441 Patent at 5:55-61.
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`The pictorial representations of the transfer gates in the figures appear to be
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`a pair of transistors which pass a signal (310 or 312) from the drain to the source of
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`the transistors as controlled by part of a row address (XA0, XA1). MICRON-
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`1003, Baker Decl. ¶ 47. However, there is nothing in the specification that limits
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`them to that particular embodiment. Id. ¶ 48.
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`7.
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`PERSON HAVING ORDINARY SKILL IN THE ART
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`A person of ordinary skill in the art with respect to the technology described
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`in the 441 Patent would be a person with a Bachelor of Science degree in electrical
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`engineering, computer engineering, computer science or a closely related field,
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`along with at least 2-3 years of experience in the design of memory devices. An
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`individual with an advanced degree in a relevant field would require less
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`experience in the design of memory devices. MICRON-1003, Baker Decl. ¶ 49.
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`8.
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`DESCRIPTION OF THE PRIOR ART
`8.1. U.S. PATENT NO. 5,270,975 (“MCADAMS”)
`U.S. Patent No. 5,270,975 (“McAdams”) (MICRON-1005) was filed on
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`August 13, 1992 and claims priority to two abandoned U.S. Applications, the
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`earliest of which was filed on March 29, 1990. McAdams issued on December 14,
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`1993, to Hugh McAdams, and is entitled “Memory Device Having A Non-Uniform
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`Redundancy Decoder Arrangement.” The original assignee was Texas Instruments
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`Incorporated. McAdams is prior art to the 441 Patent under at least (pre-AIA) 35
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`U.S.C. § 102(b) because the patent issued more than one year before the
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`application that led to the 441 Patent was filed on March 31, 1998.
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`Like the 441 Patent, McAdams is directed to a semiconductor memory
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`device with redundant column select lines and redundant bit lines. MICRON-
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`1005, McAdams at 5:57-60, 6:43-48. McAdams refers to bit lines as “bitline
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`segments.” MICRON-1003, Baker Decl. ¶ 60. McAdams refers to column
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`selection lines as column select lines. Id. ¶ 61. The semiconductor memory device
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`has an array of memory cells arranged into addressable rows and columns along
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`row lines and column lines. MICRON-1005, McAdams at 22:28-32; MICRON-
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`1003, Baker Decl. ¶ 53. The array is broken up into 16 sub-blocks of a specified
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`number of rows as shown in Figure 2.
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`MICRON-1005, McAdams at Figure 2.
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`Each one of the different sub-blocks has separate bit line segments.
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`MICRON-1005, McAdams at Figure 3; MICRON-1003, Baker Decl. ¶ 54.
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`However, the column select lines YS and YRS run through each of the sub-blocks.
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`Id. This is evidenced by the single column decoder at the bottom of Figure 2.
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`MICRON-1003, Baker Decl. ¶ 56. Like the 441 Patent, this is a divided bit line
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`architecture because there are multiple bit lines along a single column that are
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`selected by a single column selection line. Id. As shown in Figure 3, McAdams
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`discloses the use of redundant column selection lines (YRS1-RSN) and the associated
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`redundant bit lines.3 MICRON-1005, McAdams at Figure 3. Like the 441 Patent,
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`McAdams discloses the use of row and column address information to determine
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`whether to activate redundant column selection lines. MICRON-1005, McAdams
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`at Abstract (“These column repair decoder circuits are programmable with column
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`and row address information corresponding to a section of an array column
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`containing a defective memory cell to replace the defective cell with a memory cell
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`in one of the repair columns.”). Also like the 441 Patent, the redundant column
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`select lines “[are] capable of replacing multiple defective column portions with
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`multiple redundant column portions which are enabled by the same redundant
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`column select line.” Id. at 3:12-16. Like the 441 Patent, this is possible because
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`both the column address and part of the row address are used when determining
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`3 Figure 3 depicts the word line running vertically and the column selection line
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`running horizontally. That is, it is rotated 90 degrees relative to Figure 2.
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`Petition for Inter Partes Review of U.S. Pat. No. 5,894,441
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`whether to activate th