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`PATENT NUMBER
`
`5894441
`ll~~~~~(~llllllllll/111
`
`U.S. UTILITY PATENT APPLICATION
`'C__b PATENT DATE
`O.I.P.E.
`APR 13 l999d
`
`SCANNED
`
`SECTOR CLASS
`
`SUBCLASS
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`FILED WITH: D DISK (CRF) D FICHE
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`(Attached in pocket on right inside flap)
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`PREPARED AND APPROVED FOR ISSUE
`
`ORIGINAL
`/'/
`/
`SUBCL~
`&2._1:)--0
`
`/
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`1
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`CLASS
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`INTERNATIONAL CLASSIFICATION
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`CLASS
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`'s 's-
`
`D Continued on Issue Slip Inside File Jacket
`
`D TERMI~.JAL
`DISCLAIMER
`
`D a) The term of this patent
`subsequent to _____ (date)
`has been disclaimed.
`D b) The term of this patent shall
`not extend beyond the expiration date
`of U.S Patent. No.
`
`D c) The terminal __ months of
`this patent have been disclaimed.
`
`DRAWINGS
`·'
`shee;gVrwg. ·"" Figs. Drwg ...
`,,
`
`
`. /' ./ 19
`
`Print Fig.
`3
`
`CLAIMS ALLOWED
`
`TotaVCiaims
`
`Print Claim for O.G.
`1
`
`NOTICE OF ALLOWANCE MAILED
`
`., .• /
`
`(Date)
`
`6~ 2,f'~
`A-u 28./¥
`VuA.Le
`Primary Examiner
`(Primary Examiner)
`
`(Date)
`
`ISSUE FEE
`
`WARNING:
`The information disclosed herein may be restricted. Unauthorized disclosure may be prohibited by the United States Code Title 35, Section
`Possession outside the U.S. Patent & Trademark Office is restricted to authorized employees and contractors only.
`
`Form PT0·436A
`(Rev. I 0197)
`
`(LABEL AREA)
`
`(FACE)
`
`MICRON-1002.001
`
`

`
`JC542 U · S · PTO
`
`; 09/050354''
`: I 1\\1\1 \lU Ill\\ 111\111\1\ l\1\11\l\1\\1
`03/31/98
`
`PATENT APPLICATION
`I 1\\111 \\II\ 1\111\\1\1\1111\\1\\ Ill~\ \1111\1\11\\1 ~
`
`09050354
`
`CONTENTS
`
`.
`
`.
`INIT~LS
`APR ~45
`
`/
`
`papers.
`
`1. ~pcation _ 'i{
`2. \-'r I 0 r d1
`fh.fe.cs
`~1 3.--:rns
`(/;~~;) PTo L- $7
`-5. Pro GRANT #•PR 1 3 1999
`
`6. _ ___ ___ _
`
`7. _____ __ _ _
`
`8. _____ __ _ _
`
`9. _ ___ ___ _
`
`10. _ ___ ___ _
`
`11. _ ___ ___ _
`
`12. _ ___ ___ _
`
`13. ___ _____ _
`
`14. _ ___ ___ _
`
`15. _ ___ ___ _
`
`16. _ ___ ___ _
`
`17. _______ _
`
`18. __ ______ _
`
`19. ___ _ ___ _ _
`
`20. ___ _ ___ _ _
`
`21. ___ _ ___ _ _
`
`22. ___ _ ___ _ _
`
`23. __ __ __ _ _
`
`24. _______ _
`
`25. ___ _ ___ _
`
`26. - - - - - - - . . , . - - - -
`27. ________ _
`
`28. _______ _
`
`29. ________ _
`
`30. ___ ____ _
`
`31. ___ ____ _
`
`32. __ __ ___ _
`
`33.
`34. __ __ ___ _
`
`35. __ __ ___ _
`
`36. _ ____ __ _
`
`37. _ ____ __ _
`
`38. _ ____ __ _
`
`39. _ ____ __ _
`
`40. _ _____ :...___
`
`41. _ ______ _
`
`Date received
`(Incl. C. of M.)
`or
`Date Mailed
`
`Date received
`(Incl. C. of M.)
`or
`Date Mailed
`
`31:3 J /q~
`3.GJ -[q~
`I\... 2.:3-~ Jft
`
`42.
`
`43.
`
`44.
`
`45.
`
`46.
`
`47.
`
`48.
`
`49.
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`50.
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`51.
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`52.
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`53.
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`54.
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`55.
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`56.
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`57.
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`58.
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`59.
`
`60.
`
`61.
`
`62.
`
`63.
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`64.
`
`65.
`
`66.
`
`67.·
`
`68.
`
`69.
`
`70.
`
`71.
`
`72.
`
`73.
`
`74.
`
`75.
`
`76.
`
`77.
`
`78.
`
`79.
`
`80.
`
`81.
`
`82.
`
`(FRONT)
`
`MICRON-1002.002
`
`

`
`.
`
`ISSUE SLIP STAPLE AREA (for additional cross references)
`.•
`.
`
`POSITION·
`
`IDNO.
`
`DATE
`
`FEE DETERMINATION
`O.I.P.E. CLASSIFIER
`FORMALITY REVIEW
`
`i
`)
`
`j
`
`Claim
`Iii !I X
`~ 1-~
`Iii '61
`~ 0
`i.i:
`I ~oo..,1 1.:::::
`2
`7-
`~ 3
`4 4
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`7 7
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`8
`9 9
`to 10
`11
`\\
`\7 .. 12
`'l~ 13
`ilr 14
`,,- 15 r::=:
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`48
`49
`50
`
`INDEX OF CLAIMS
`
`................................. Rejected
`t/
`= ................................. Allowed
`(Through numeral) Canceled
`................................. Restricted
`
`N ................................. Non-elected
`I ................................. Interference
`A ................................. Appeal
`0 ................................. Objected
`
`Date
`
`Claim
`
`Date
`
`Claim
`
`Date
`
`Iii
`~
`Iii '61
`~ 0
`i.i:
`51
`52
`53
`54
`55
`56
`57
`58
`59
`60
`61
`62
`63
`64
`65
`66
`67
`68
`69
`70
`71
`72
`73
`74
`75
`76
`77
`78
`79
`70
`81
`82
`83
`84
`85
`86
`87
`88
`89
`90
`91
`92
`93
`94
`95
`96
`97
`98
`99
`~0(
`
`Iii
`~
`Iii '61
`~ 0
`i.i:
`11_(:
`11~
`m
`11~
`115
`116
`117
`118
`119
`10
`111
`112
`113
`114
`115
`116
`117
`118
`119
`120
`121
`122
`123
`124
`125
`~26
`127
`128
`~29
`130
`131
`~32
`13:!
`13L
`13f
`13€
`131
`38
`39
`p40
`141
`14~
`14,
`14L
`45
`46
`141
`1~
`14~
`15_(
`
`If more than 150 claims or 1 0 actions
`staple additional sheet here
`
`(LEFT INSIDE)
`
`MICRON-1002.003
`
`

`
`PATENT NUMBER
`
`~~ .
`'
`
`'
`
`APPLICATION SERIAL NUMBER
`
`of} oi-o 5 .s.-4-
`
`APPLICANT'S NAME (PLEASE PRINT)
`
`.
`
`'
`
`.
`
`.~£W;tll-
`.. · N ft/<.:11- 2A LJ A
`
`IF ~EISSUE. ORIGINAL PATENT NUMBER
`
`INTERNATIONAL CLASSIFICATION
`
`ltr- \
`
`l c.
`
`PT0270
`(REV. 5-91)
`
`7 /oo
`7
`7
`7
`
`STAPLE
`
`AREA
`
`,.U.S. GOVERNMENT PRINTING OFFICE: 1998-440·769
`
`CLASS
`
`ORtGir.Al CLASSIFICATION
`SUBCLASS
`
`- .
`3~)
`
`'2.0--V
`
`.
`
`.
`
`CLASS
`-~6~
`
`I
`i
`
`I
`
`CROSSIRfFERENCE(S)
`SUBCLASS
`(ONE SUBCLASS PER BLOCK)
`.2.$o,o) 2.3o, c~
`
`i
`I
`I
`7 I
`
`GROUP
`ART UNIT
`
`ASSIST ANT EXAMINER (PLEASE STAMP OR PRINT FULL NAME)
`
`2glK' PRIMARY EXAMINER (PLEASE STAMP OR PRINT FULL NAME)
`
`~
`
`\/u A
`I -
`,
`ISSUE CLASSIFICATION sl?nmary Exam1ner
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK oFFicE
`
`MICRON-1002.004
`
`

`
`SEA
`
`Class
`
`Sub.
`
`3bS-
`
`/)_DO
`c£ 0 (
`2 ?o. o 3
`2.. ~0. Ob
`
`Date
`1//2- qg
`
`I
`
`Exmr.
`
`&'-
`
`I
`
`OTES
`(INCLUDING SEARCH STRATEGY}
`
`Date
`
`Exmr.
`
`INTERFERENCE SEARCHED
`Sub.
`Exmr.
`.:r-<
`
`Class
`5tr
`
`/}..oo
`J,._jo. IJ6
`'2-$o.o3
`
`Date
`;ll~j/ft
`
`'
`
`(RIGHT OUTSIDE)
`
`MICRON-1002.005
`
`

`
`PATENT APPLICATION SERIAL NO . - - - - - - - -
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
`
`04/0211998 1fLOYJ)
`01 FCI101
`
`00000005 09050!1.00 OP
`nv
`
`PT0-1556
`(5/87)
`
`MICRON-1002.006
`
`

`
`SERIAL NUMBER
`
`09/050,354
`
`FILING DATE
`
`03/31/98
`
`CLASS
`
`365
`
`GROUP ART UNIT
`
`ATIORNEY DOCKET NO.
`
`2818
`
`Q49706
`
`1-z SHIGEYUKI NAKAZAWA, TOKYO, JAPAN.
`5
`:J a..
`a..
`<(
`
`**CONTINUING DOMESTIC DATA*********************
`VERIFIED
`
`**371 (NAT'L STAGE) DATA*********************
`VERIFIED
`
`**FOREIGN APPLICATIONS************
`JAPAN
`VERIFIED
`
`81203/1997
`
`03/31/97
`
`STATE OR
`\'Zfyes Ono
`115¥es ono OMet after Allowance COUNTRY
`lJt.(
`
`'!PX
`
`Foreign Priority claimed
`35 USC 119 (a·d) conditions met
`
`Verified and Acknowledged
`"'
`FYAfilT ner
`SUGHRUE MION ZINN MACPEAK & SEAS
`~ 2100 PENNSYLVANIA AVENUE NW
`w
`~ t'IASHINGTON DC 20037
`0
`<(
`
`SHEETS
`DRAWING
`8
`
`TOTAL
`CLAIMS
`15
`
`INDEPENDENT
`CLAIMS
`2
`
`SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY CIRCUIT
`
`w
`..J
`!:::
`1-
`
`FILit,.) FEE
`RECEIVED
`
`$790
`
`FEES: Authority has been given in Paper
`No.
`to charge/credit DEPOSIT ACCOUNT
`NO.
`for the following:
`
`0 All Fees
`
`8 1.16 Fees (Filing)
`
`1.17 Fees (Processing Ext. of time)
`0
`1.18 Fees (Issue)
`0 Other-----
`0 Credit
`
`MICRON-1002.007
`
`

`
`SUGHRUE, MION, ZINN, MACPEAK & SEAS, PLLC
`
`LAW OFFICES.
`
`2100 PENNSYLVANIA AVENUE, N.W.
`WASHINGTON, D.C. 20037-3202
`TELEPHONE (202) 293-7060
`FACSIMILE (202) 293-7860
`
`March 31, 1998
`
`JAPAN OFFICE
`TOE! NISHI SHIMBASHI BLDG. 4F
`13-5 NISHI SHIMBASHI 1-CHOME
`MINATO-KU, TOKYO 105, JAPAN
`TELEPHONE (03) 3503-3760
`FACSIMILE (03) 3503-3756
`
`CALIFORNIA OFFICE
`1010 EL CAMINO REAL
`MENLO PARK, CA 94025
`TELEPHONE (650) 325-5800
`FACSIMILE (650) 325-6606
`
`BOX PATENT APPLICATION
`Assistant Commissioner for Patents
`Washington, D.C. 20231
`
`Re:
`
`Application of Shigeyuki NAKAZA WA
`"SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY CIRCUIT"
`Our Ref: Q49706
`
`Dear Sir:
`
`Attached hereto is the application identified above including the specification and claims, 8 sheets of formal
`drawings, an Information Disclosure Statement with Form PT0-1449 and references, an executed Assignment and
`PT0-1595 form, and an executed Declaration and Power of Attorney.
`
`The Government filing fee is calculated as follows:
`
`20
`3
`
`J2..(cid:173)
`_1_-
`
`Total claims
`Independent claims
`Base Fee
`Multiple Dependent Claim Fee $270.00
`TOTAL FILING FEE
`Recordation of Assignment
`TOTAL FEES
`
`X $22 =
`X $82 =
`
`$ 790.00
`
`$ 790.00
`$ 40.00
`$ 830.00
`
`Checks for the statutory filing fee of $790.00 and Assignment recordation fee of $40.00 are attached. You
`are also directed and authorized to charge or credit any difference or overpayment to Deposit Account No. 19-4880.
`The Commissioner is hereby authorized to charge any fees under 37 C.F.R. §§ 1.16 and 1.17 and any petitions for
`extension of time under 37 C.F.R. § 1.136 which may be required during the entire pendency of the application to
`Deposit Account No. 19-4880. A duplicate copy of this transmittal letter is attached.
`
`Priority is claimed from Japanese Patent Application No. 081203/97 filed March 31, 1997. A certified copy
`of the priority document is enclosed herewith.
`
`/
`
`Respectfully submitted,
`
`SUGHRUE, MION, ZINN,
`MACPEAK & SEAS, PLLC
`Attorneys for Applicant
`
`By:~~
`
`:Frank Osha
`Reg. No. 24,625
`
`MICRON-1002.008
`
`

`
`SUGHRUE, MION, ZINN, MA.CPEAK & SEAS, PLLC
`
`LAW OFFICES
`
`2100 PENNSYLVANIA AVENUE, N.W.
`WASHINGTON, D.C. 20037-3202
`TELEPHONE (202) 293-7060
`FACSIMILE (202) 293-7860
`
`March 31, 1998
`
`JAPAN OFFICE
`TOE! NISHI SHIMBASHI BLDG. 4F
`13-5 NISHI SHIMBASHI 1-CHOME
`MINATO-KU, TOKYO 105, JAPAN
`TELEPHONE (03) 3503-3760
`FACSIMILE (03) 3503-3756
`
`CALIFORNIA OFFICE
`1010 EL CAMINO REAL
`MENLO PARK, CA 94025
`TELEPHONE (650) 325-5800
`FACSIMILE (650) 325-6606
`
`BOX PATENT APPLICATION
`Assistant Commissioner for Patents
`Washington, D.C. 20231
`
`Re:
`
`Application of Shigeyuki NAKAZA W A
`"SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY CIRCUIT"
`Our Ref: Q49706
`
`Dear Sir:
`
`Attached hereto is the application identified above including the specification and claims, 8 sheets of formal
`drawings, an Information Disclosure Statement with Form PT0-1449 and references, an executed Assignment and
`PT0-1595 form, and an executed Declaration and Power of Attorney.
`
`The Government filing fee is calculated as follows:
`
`20
`3
`
`_li_ -
`_L -
`
`Total claims
`Independent claims
`Base Fee
`Multiple Dependent Claim Fee $270.00
`TOTAL FILING FEE
`Recordation of Assignment
`TOTAL FEES
`
`X $22 =
`X $82 =
`
`$ 790.00
`
`$ 790.00
`$ 40.00
`$ 830.00
`
`Checks for the statutory filing fee of $790.00 and Assignment recordation fee of $40.00 are attached. You
`are also directed and authorized to charge or credit any difference or overpayment to Deposit Account No. 19-4880.
`The Commissioner is hereby authorized to charge any fees under 37 C.P.R. §§ 1.16 and 1.17 and any petitions for
`extension of time under 37 C.P.R. § 1.136 which may be required during the entire pendency of the application to
`Deposit Account No. 19-4880. A duplicate copy of this transmitt~lletter is attached.
`
`Priority is claimed from Japanese Patent Application No. 081203/97 filed March 31, 1997. A certified copy
`of the priority document is enclosed herewith.
`
`Respectfully submitted,
`
`SUGHRUE, MION, ZINN,
`MACPEAK & SEAS, PLLC
`Attorneys for Applicant
`
`By:~~
`
`:Frank Osha
`Reg. No. 24,625
`
`MICRON-1002.009
`
`

`
`J 7 ~~,t)(J ~ st/
`/ '
`
`SEMICONDUCTOR MEMORY DEVICE
`
`WITH REDUNDANCY CIRCUIT
`
`Field of the Invention
`The present invention relates to a semiconductor memory device equipped
`
`with a redundancy circuit, and more particularly, to a semiconductor memory device
`
`having an enhanced relief efficiency of a defective bit line by means of a redundant
`
`bit line.
`
`Background of the Invention
`Accompanying fine geometry, high integration, and large capacity of the
`
`semiconductor memory devices in recent years, it is becoming extremely difficult
`
`to obtain perfect products which are absolutely free from defects. In other words,
`
`almost all of the produced semiconductor memory devices include defective
`
`memory cells, defective work lines, or defective bit lines. In order to make it
`
`possible to deliver semiconductor memory devices that include such defects as
`
`acceptable products, it is a general practice to provide the semiconductor memory
`
`device with a redundancy circuit.
`
`The redundancy circuit is for disabling the· use of a defective word or bit line
`
`when there exists one, and replacing the defective word or bit line with a redundant
`
`word or bit line. By designing a circuit configuration such that a defective word
`
`line or a defective bit line can be replaced by a redundant word line or a redundant
`
`bit line, as in the above, it is possible to deliver a semiconductor memory device as
`
`if it is absolutely free from defectiveness. Accordingly, ·a redundancy circuit
`
`contributes significantly to the enhancement of the yield of the semiconductor
`
`memory devices.
`
`-
`
`1 -
`
`MICRON-1002.010
`
`

`
`In order to relieve as many defective word lines or defective word lines or
`
`defective bit lines as possible, it is most effective to incorporate as many redundant
`
`word lines or redundant bit lines as its practicable. However, since the redundancy
`
`circuit is a superfluous circuit in the sense that it is useless unless there exists
`
`defectiveness in the manufactured semiconductor memory device, it is not
`
`recommended to provide a large scale redundancy circuit within the semiconductor
`
`memory device. For this reason, it is desirable to relieve as many defective word
`
`lines or defective bit lines as possible with a minimum number of redundant word
`
`lines or redundant bit lines.
`
`Under those circumstances, a variety of methods for improving the relief
`
`efficiency of defective word lines or defective bit lines by means of a redundant
`
`circuit have been proposed. As examples, there may be mentioned methods
`
`disclosed in USP 5,349,556, USP 5,355,339, USP 5,359,560, and USP 5,414,660.
`
`The method described in these patents is what is called the row flexible redundancy
`
`method. The row flexible redundancy method is a technique for efficiently
`
`relieving the word line defects, which has a feature in that the range of replacement
`
`covered by one redundant word line is broad.
`
`However, according to the row flexible redundancy method, the relief
`
`efficiency for defective bit lines remains unchanged, although the relief efficiency
`
`for defective word lines can be improved. Because of this, a method which can also
`
`improve the relief efficiency for defective bit lines is ip demand.
`'
`
`Summary of the Invention
`
`It is an object of the present invention to provide a semiconductor memory
`
`device equipped with a redundancy circuit having a high relief efficiency.
`
`It is another object of this invention to provide a semiconductor memory .
`
`- 2 -
`
`MICRON-1002.011
`
`

`
`device by which defective bit lines can be relieved by a smaller number of
`
`redundant bit lines.
`
`It is still another object of this invention to provide a semiconductor memory
`
`device which is capable of relieving a larger number of defective bit lines while
`
`minimizing the increase in the chip area.
`
`It is still another object of this invention to provide a semiconductor memory
`
`device equipped with a redundant circuit which is capable of improving the relief
`
`efficiency for defective bit lines while employing a row flexible redundancy circuit.
`
`The semiconductor memory device according to this invention comprises a
`
`plurality of column selection lines, at least one redundant column selection line, a
`
`column decoder which activates one line out of the plurality of column selection
`
`lines in response to a column address, a first circuit which generates a detection
`
`,,,
`
`signal when the column address of a defect-related column selection line is
`
`supplied, and a second circuit which receives at least a part of a row address, and
`
`activates the redundant column selection line in response to at least a part of the row
`
`address and the detection signal. With this arrangement, when defect occurs in one
`
`bit line, instead of replacing all of the many bit lines included in the column
`
`selection line to which the defective bit line belongs, it is possible to relieve a larger
`
`number of defective bit lines using a single redundant column selection line by
`
`replacing only a part of these bit lines.
`
`Brief Description of the Drawings
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`,/ /
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`The above and other objects, advantages and features of the present invention
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`will be apparent from the following description taken in conjunction with the
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`accompanying drawings, in which:
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`Fig. 1 is a block diagram showing a semiconductor memory device 1 00 with ,
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`MICRON-1002.012
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`

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`divided bit lines, which is an object of this invention;
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`Fig. 2 is a block diagram showing a semiconductor memory device 200
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`according to a first embodiment of this invention;
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`Fig. 3 is a circuit diagram showing a part of a column redundancy decoder
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`216 in Fig. 2;
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`Fig. 4 shows a fuse blocks 302 and 304 shown in Fig. 3;
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`Fig. 5 is a timing chart showing the timings for bit line replacement by the
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`semiconductor memory device 200;
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`Fig. 6 is a block diagram showing a semiconductor memory device 600
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`according to a second embodiment of this invention;
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`Fig. 7 is a block diagram showing a semiconductor memory device 700
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`according to a third embodiment of this invention;
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`Fig. 8 is a circuit diagram of a control circuit 750 in Fig. 7;
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`Fig. 9 is a circuit diagram showing a part of a column redundancy decoder
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`716 in Fig. 7; and
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`Fig. 10 is a timing chart showing the timings for bit line replacement
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`according to the semiconductor memory device 700.
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`Detailed Description of the preferred Embodiments
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`First, referring to Fig. 1, the semiconductor memory device 100 which is the
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`object of application of this invention will be described prior to detailed description
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`of the semiconductor memory device of this invention.
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`A semiconductor memory device 100 shown in Fig. 1 is a semiconductor
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`memory device with divided bit lines. The cell array region of the semiconductor
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`memory device 100 consists of a normal cell array region 102 and a redundant cell
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`array region 104.
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`MICRON-1002.013
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`An X address (row address) is supplied to a row decoder 1 06 and a row
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`redundancy decoder 112, and a Y address (column address) is supplied to a column
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`decoder 108 and a column redundancy decoder 116. Upon receipt of the X address
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`the row decoder 106 activates one word line corresponding to the X address out of
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`a plurality of word lines. In Fig. 1, only word lines 118 and 120 are indicated for
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`convenience. On the other hand, upon receipt of a Y address, the column decoder
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`108 activates one column selection line corresponding to the Y address out of a
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`plurality of column selection lines. In Fig. 1, only the column selection line 122 is
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`indicated for convenience.
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`Many memory cells MC are connected to each of the word lines 118 and 120,
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`and respective memory cells MC are connected to sense amplifiers 124, 126, and
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`the like.
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`Here, it is to be noted that the column selection line 122 activates the plurality
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`of sense amplifiers 124, 126, and the like. That is, in the same column, a bit line is
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`divided into plural parts, and the column decoder 108 selects all the sense amplifiers
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`connected to the plurality of divided bit lines, in response to the Y address.
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`Although only two bit lines are indicated in Fig. 1 for convenience, it will be
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`assumed that the number of divided bit lines is actually 16. In other words, when
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`the column selection line 122 is activated in response to a Y address, 16 sense
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`amplifiers are selected simultaneously. However, only the data corresponding to an
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`activated word line is selected finally out of the 16 selected sense amplifiers, and
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`is readout.
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`The row redundancy decoder 112 detects the supply of the X address
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`corresponding to a defective word line. The row redundancy decoder 112 includes
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`a plurality of fuse elements, and stores the X address corresponding to a defective
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`MICRON-1002.014
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`word line according to whether or not these fuses are blown out. Namely, when the
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`X address corresponding to a defective word line is supplied, the row redundancy
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`decoder 112 supplies an inhibit signal132 to the row decoder 106 to deactivate the
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`row decoder 106, and activates a redundant word line driver 110 to activate a
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`specified redundant word line 128. In this way, the defective word line is replaced
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`by the redundant word line 128.
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`On the other hand, the column redundancy decoder 116 detects the supply of
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`the Y address corresponding to a defective bit line. The column redundancy
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`decoder 116 also includes a plurality of fuse elements, and stores the Y address
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`corresponding to a defective bit line according to whether or not these fuses are
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`blown out. In other words, when the Y address corresponding to the defective bit
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`line is supplied, the decoder 116 deactivates the column decoder 108 by supplying
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`an inhibit signal 134 to the column decoder 108, and activates the redundant column
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`selection driver 114 in order to activate a specified redundant column selection line
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`130. In this way, the defective bit line is replaced by a redundant bit line (not
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`shown) corresponding to the redundant column selection line 130.
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`However, such a semiconductor memory device 100 has the following
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`problem. Namely, if one bit line is defective, not only the defective bit line but also ,
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`other bit lines that share the column selection line are replaced to the redundant bit
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`lines. More specifically, as a result of defect in a bit line, for example, the bit line
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`corresponding to the sense amplifier 124, all of the 16 bit lines selected by the same
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`column selection line 122 are disabled, and all of the 16 bit lines are replaced to the
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`redundant bit lines. Thus, many redundant bit lines will be wasted for a small
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`number of bit line defects. In effect, it leads to the problem of deterioration of the
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`relief efficiency of the defective bit lines.
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`MICRON-1002.015
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`In the semiconductor memory devices according to each of the embodiments
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`that will be described in the following, the above problem is resolved to realize a
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`high relief efficiency.
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`The semiconductor memory device according to a first embodiment of this
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`inv·ention 200 has a feature in that a column redundancy decoder 216 receives not
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`only a Y address but also a part of an X address, as shown in Fig. 2. The remaining
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`portions are basically the same as that of the semiconductor memory device 100
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`shown in Fig. 1.
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`Namely, the semiconductor memory device 200 shown in Fig. 2 is a
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`semiconductor memory device with divided bit lines, and the cell array region
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`consists of a normal cell array region 202 and a redundant cell array region 204.
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`In addition to an X address being supplied to a row decoder 206 and a row
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`redundancy decoder 212, XAO and XA1 which show the logical level of the most
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`significant bit of the X address are supplied also to the column redundancy decoder
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`216. As mentioned above, XAO and XA1 are signals showing the logical level of
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`the most significant bit of the X address, in which XAO is 11 111 and XA 1 is 11011 when
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`the most significant bit of the X address is 0, and on the contrary, XAO is 11011 and
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`XA 1 is 11 111 when the most significant bit of the X address is 1. In short, XAO and
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`XA1 are mutually complementary signals.
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`On the other hand, a Y address is supplied to a column decoder 208 and the
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`column redundancy decoder 216.
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`Upon receipt of the X address, the row decoder 206 activates one word line
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`corresponding to the X address out of a plurality of word lines. In Fig. 2, only word
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`line 218 and word line 220 are indicated for convenience. On the other hand, upon
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`receipt of theY address, the column decoder 208 activates one column selection
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`MICRON-1002.016
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`

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`line corresponding to the Y address out of a plurality of column selection lines. In
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`Fig. 2, column selection lines 222 and 290 alone are indicated for convenience.
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`Each of the word lines 218, 220, and the like is connected to a memory cell
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`MC, and each memory cell MC is connected to a corresponding one of sense
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`amplifiers 224, 226, and the like.
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`In the semiconductor memory device 200 shown in Fig. 2, the column
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`selection line 222 activates, as before, a plurality of sense amplifiers 224, 226, and
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`the like. That is, analogous to the semiconductor memory device 100, a bit line is
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`divided into plural parts in the same column, and the column decoder 208 selects
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`all the sense amplifiers connected to a plurality of divided bit lines in response to
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`the Y address. Although only two bit lines are indicated in Fig. 2 for convenience,
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`it will be assumed that a bit line is actually divided into 16 parts as before. Namely,
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`when the column selection line 222, 290, or the like is activated in response to a Y
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`address, 16 sense amplifiers are selected simultaneously. Data corresponding only
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`to the activated word line is selected finally out of the 16 sense amplifiers, and is
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`read out.
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`The row redundancy decoder 212 detects the supply of the X address
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`corresponding to a defective word line. The row redundancy decoder 212 contains
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`a plurality of fuse elements, and stores the X address corresponding to defective
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`word lines depending upon whether or not these fuses are blown out. Typically,
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`polysilicon is used for these fuses, but the present invention is not limited to this
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`choice, and permits the use of any kind of material for the fuses. In addition,
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`although laser irradiation is employed typically as the method of fuse bow-out, this
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`invention is not limited to this case, and permits the use of any type of blow-out
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`method. For example, the fuse may be blown out by the passing of a large current
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`8 -
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`MICRON-1002.017
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`

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`in the fuse.
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`When an X address corresponding to a defective word line is received, the
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`row redundancy decoder 212 deactivates the row decoder 206 by supplying an
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`inhibit signal 232 to the row decoder 206, and activates a redundant word line
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`driver 210 in order to activate a specified redundant word line 228. As a result, the
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`defective word line is replafl'ed to the redundant word line 228. Accordingly, it will
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`look as if there exists no defect when seen from the outside.
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`In the meantime, the column redundancy decoder 216 detects that a Y address
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`corresponding to a defective bit line is supplied. Referring to Fig. 3, a specific
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`circuit diagram and the operation of the column redundancy decoder 216 will be
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`described.
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`Fig. 3 shows a specific circuit configuration of the column redundancy
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`decoder 216, but it does not show the all circuit parts that are included in the
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`column redundancy decoder 216. Namely, the column redundancy decoder 216'
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`shown in Fig. 3 illustrates only the circuit part corresponding to one redundant
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`column selection line YRED of the column redundancy decoder 216. Accordingly,
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`in the decoder 216, there actually exist as many column redundancy decoders 216'
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`as equals to the number of the redundant column selection lines YRED. For
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`example, if there exist 8 redundant column selection lines YRED, 8 column
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`redundancy decoders 216' are needed, and if there exist 16 redundant column
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`selection lines YRED, then 16 column redundancy decoders 216' are needed.
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`As shown in Fig. 3, two fuse blocks 302 and 304 are included in the column
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`redundancy decoder 216', and the Y address is supplied in common to these fuse
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`blocks 302 and 304. A specific circuit configuration of these fuse blocks 302 and
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`304 is as shown in Fig. 4. As shown in Fig. 4, in the fuse blocks 302 and 304 are
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`- 9 -
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`MICRON-1002.018
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`included a plurality of fuses 402, and the Y address of a defective bit line is stored
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`by programming theY address of the defective bit line in these fuses 402. Namely,
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`when the Y address of a defective bit line is supplied to the fuse blocks 302 and 304
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`where the Y address of the defective bit line is programmed, a wiring 404 goes to
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`the ground potential, and matching signals 306 and 308 go to a high level (active
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`level). In contrast, when an address different from the Y address of the defective
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`bit line is supplied to the fuse blocks 302 and 304, the wiring 404 is held at a
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`potential V cc, and the matching signals 306 and 308 are held at a low level (inactive
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`level).
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`That the material and the blow-out method to be employed by the fuse 402
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`are not limited is similar to the case of the row redundancy decoder 212.
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`As shown in Fig. 3, the column redundancy decoder 216' further includes two
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`transfer gates 310 and 312. The transfer gate 310 outputs the matching signal 3 06
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`as the YRED when XAO is at the high level, and the transfer gate 312 outputs the
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`matching signal 308 as the YRED when XA1 is at the high level. As mentioned
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`above, XAO and XA1 are complementary signals showing the logical level of the
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`most significant bit of the X address, so that either one of the transfer gates 31 0 or
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`312 is necessarily in the energized state and the other is in the deenergized state.
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`Although it is not explicitly indicated in Fig. 3, when a YRED goes to the
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`high level (active level), the inhibit signal 234 goes to the active level, and inhibits
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`the operation of the column decoder 208.
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`Next, the replacement operation of a defective bit line is the semiconductor
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`memory device 200 will be described.
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`As an example, the case in which a bit line corresponding to the sense
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`amplifier 224 is defective will be described. In this case, the bit line corresponding
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`- 10 -
`
`MICRON-1002.019
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`

`
`to the column selection line 222 is defective, so the Y address corresponding to the
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`column selection line 222 is programmed in the column redundancy decoder 216.
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`What is important at this time is to program this Y address in the fuse block 302
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`within the column redundancy decoder 216.
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`After programming in this manner, when the memory cell MC corresponding
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`to the defective bit line is accessed, the fuse block 302 brings the matching signal
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`306 to the high level by detecting the matching of theY signals. Further, since the
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`defective bit line belongs to the cell array region where the most significant bit of
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`the X address is 0, XAO is "1 ", and the transfer gate 310 goes to the energized state.
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`Accordingly, the YRED goes to the active level, and corresponding to this, the
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`redundant column selection line drive 214 activates the specifies redundant column
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`selection line 230. On the other hand, the operation of the column decoder 208 is
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`inhibited by the inhibit signal 234.
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`.;f'
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`<:.
`As a result, the defective bit line is replaJed to a redundant bit line belonging
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`to the redundant column selection line.
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`On the other hand, when a memory cell connected to a bit line belonging to
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`a cell array region where the most significant bit of the X address is "1 ", among the
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`other bit lines corresponding to the column ~election line 222, is accessed, the
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`replacement of the bit line is not carried out. The reason for this is that, although
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`the fuse block 3 02 activates the matching signal 3 06 as a result of matching of the
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`Y addresses, the transfer gate 310 is deenergized in this case, and the YRED is not
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`activated. As a result of the nonactivation of the YRED, the inhibit signal 234 is
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`not activated either, and the column decoder 208 carries out the normally operation.
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`In this connection, it should be noted that the above fact means that only half
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`of the bit lines, namely, only those bit lines belonging to the cell array region where
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`MICRON-1002.020
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`

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`the most significant bit of the X address is "1 ", out of the bit lines corresponding to
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`the column selection line 222, are replased to the redundant bit lines.
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`Here, the case in which another bit line, for example, a bit line belonging to
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`the cell array region where the most significant bit of the X address is "1" among the
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`bit lines belonging to the column selection line 290, is defective, will be described.
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`In this case, since a bit line corresponding to the column selection line 290 is
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`defective, the Y address corresponding to the column selection line 290 is
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`programmed in the column redundancy decoder 216. What is important at this time
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`is to program theY address in the fuse block 304 in the column redundancy decoder
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`216.