HIIII||l|||||||lI|ll|||||||l|||Illlllllll||||||||||||l|l|||||H|||||||Il||l
`
`USO05598405A
`
`United States Patent
`
`[19]
`
`Hirose
`
`[11] Patent Number:
`
`5,598,405
`
`[45] Date of Patent:
`
`Jan. 28, 1997
`
`[54] TIME DIVISION MULTIPLE ACCESS TIME
`DIVISION DUPLEX TYPE
`
`TRANSMITTER'RECEIVER
`Inventor: Yoshitaka Ifirose’ Soma, Japan
`
`[75]
`
`[73] Assignee: Alps Electric Co., Ltd., Tokyo, Japan
`
`A
`
`.
`PP1 N0
`Filed:
`
`21
`
`1
`[
`[22]
`
`J 377 571
`9
`Jan. 23, 1995
`_
`_
`,
`_
`,
`Foreign Apphcatmn Pnomy Data
`[30]
`Jan. 25, 1994
`[JP]
`Japan .................................. .. 6—006482
`Jan. 25, 1994
`[JP]
`Japan .................................... 6-006483
`[51]
`Int. Cl.“ ........................................................ H03L 7/06
`[52] US. Cl.
`.......................... 370/280; 375/3751375/376;
`327/156: 331/25v 370/347
`[58] Field of Search .................................. 370/29, 32, 24,
`370/93, 105.3, 110.1, 95.1, 95.2; 455/84,
`86, 87, 75, 76, 77,181.1, 152.1, 180.3,
`260; 331/14, 17, 18, 25; 375/219, 220,
`371, 373, 375, 376; 327/141-164
`
`[56]
`
`References Cited
`U_S_ PATENT DOCUMENTS
`
`4,083,015
`1121008
`
`4/1978 Popodi
`6/1992
`
`...................................... .. 331/4
`370/29
`
`5’175’511
`5’230’088
`5:33-7:010
`5,339,309
`5,465,400
`
`12/1992
`7/1993
`8/1994
`8/1994
`11/1995
`
`331/18
`455/84
`330/255
`370/32
`......... 455/127
`
`Vc:
`
`7
`
`VP
`
`V“
`
`5,521,947
`
`5/1996 Madsen ................................... 327/156
`
`.
`.
`Primary Examzner——Alpus H. Hsu
`Assistant Examiner———SeeIna S. Rao
`Attorney, Agent, or Firm——Guy W. Shoup; Patrick T. Bever
`. [57]
`ABSTRACT
`
`_
`_
`_
`A transrnitter-receiver of the TDMA/TDD type which
`includes a phase control loop controlled in such a manner
`that the loop is turned on during the time slot just preceding
`each of a transmission time slot and a reception time slot,
`and the loop is turned 011" during all other time periods
`including the transmissiontime slot and the reception time
`slot. The voltage controlled oscillator includes a variable
`capacitance diofde which producles aln output freqéiefiricy in
`response to a requency contro vo tage receive
`om a
`charge pump when the loop is closed, and in response to a
`charging Voltage Supplied from a loop filter when the loop
`is open. When the loop is closed, a phase comparator
`compares a reference frequency signal with an output fre-
`quency signal of the voltage~controlled oscillator and gen-
`erates error signals for controlling the charge pump. A state
`switching unit switches the state of the phase comparator
`between an operating state, when the loop is closed, and a
`stand-by state in response to a power saving signal when the
`loop is open. A bias supply unit applies a variable bias
`voltage to an anode of the variable capacitance diode. The
`variable bias voltage varies in nearly the same manner as the
`voltage Suppligd to a cathode of the variable
`capacitance diode from the loop filter when the phase
`comparator is in a stand—by state, thereby maintaining the
`voltage across the variable capacitance diode at a relatively
`constant
`level such that the output frequency signal
`is
`maintained at 2. desired ICVGI.
`
`7 Claims, 6 Drawing Sheets
`
`LOOP
`F§LTER
`
`VE0
`
`I
`
`
`
`PLL CLK
`PLL sre.
`PLL DATA *
`LOCK DET.
`PS
`
`RF OUT Vcc
`
`M00. INPUT
`
`TX ENABLE
`
`TRANSMISSION
`TIME SLUT
`
`RECEPTION
`TIME SLOT
`
`OPERATION 0N
`or PLL
`OFF
`
`I
`
`I
`
`I
`
`APPLE 1005
`
`1
`
`APPLE 1005
`
`

`
`U.S. Patent
`
`Jan. 28, 1997
`
`Sheet 1 of 6
`
`5,598,405
`
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`U.S. Patent
`
`Jan.28, 1997
`
`Sheet 2 of 6
`
`_ 5,598,405
`
`I§E8[+IPTION
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`TRANSMISSION AND
`RECEPTION SLOTS
`FIG. 23
`P
`POWER SAVING
`S
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`FIG. 26
`.
`TRANSMISSION C0
`SIGNAL (TX ENAB
`H6. 20
`TX ENABLE
`F/G. 2E
`OPERATING STATE
`SWITCHING TRANSI
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`
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`U.S. Patent
`
`Jan. 28, 1997
`
`Sheet 5 of 6
`
`5,598,405
`
`,
`
`'
`
`I STANDBY STATE OF PLL (LOOP as OPEN)
`
`FIG. 5A
`PRIOR ART
`
`PLL POWER SAVING
`
`5“3NAL ‘PS’
`FIG. 5B
`PRIOR ART
`CHARGING VOLTAGE
`(CATHODE VOLTAGE
`OF VARIABLE
`CAPACITY DIODE)
`FIG. 5C
`PRIOR ART
`OSCILLATIN
`FREQUENCY
`
`VCO
`
`6
`
`

`
`U.S. Patent
`
`Jan. 28, 1997
`
`Sheet 6 of 6
`
`5,598,405
`
`TRANSMISSION
`TIME SLOT
`
`RECEPTION
`TIME SLOT
`
`OPERATION 0N
`or-' PLL
`
`OFF
`
`I
`
`I
`
`I
`
`I
`
`H5. 7 PRIOR ART
`
`TRANSMISSION
`TIME SLOT
`
`RECEPTION
`TIME SLOT
`
`“ME SLOTS
`
`OPERATION
`or PLL
`
`N
`
`0
`
`OFF
`
`7
`
`

`
`5,598,405
`
`1
`TIME DIVISION MULTIPLE ACCESS TIME
`DIVISION DUPLEX TYPE
`TRANSMITTER-RECEIVER
`
`BACKGROUND OF THE INVENTION
`
`1. Field of The Invention
`
`The present invention generally relates to a time division
`multiple access/time division duplex (hereunder abbreviated
`as TDMA/TDD) type transmitter-receiver and more particu-
`larly to a TDMA/TDD type transmitter-receiver in which a
`voltage-controlled oscillator (hereunder sometimes abbrevi-
`ated as VCO) of a phase control loop (namely, a phase-
`locked loop (hereunder sometimes abbreviated as PLL)) acts
`as a carrier oscillator at the time of a transmission and also
`acts as a local oscillator at the time of a reception.
`2. Description of The Prior Art
`Generally, in a cordless telephone system employing a
`TDMA/TDD method, for example, in a DECT (namely,
`Digital European Cordless Telephone) type digital cordless
`telephone system employed in Europe, a frame having a
`frame period (or frame time) of 10 milliseconds for channels
`is divided into 24 time slots with respect to time (thus one
`time slot is about 417 microseconds (us)). Among these time
`slots, two time slots are employed as communication slots.
`Further, one of these speech slots is employed as a master
`slot to be used for a transmission from a transmitter-receiver
`(hereunder referred to as a master set) serving as a master
`telephone set (namely, a base unit) to another transn1itter-
`receiver (hereunder referred to as a slave set) serving as a
`slave cordless telephone set. The other is employed as a
`slave slot to be used for a transmission from the slave set to
`the master set. Thus a desired communication or call is made
`between the master and slave sets. In this case, the master
`slot and the slave slot are interspersed at an interval of
`twelve time slots. For instance, in case where a first time slot
`is used as a master slot, a thirteenth time slot is used as a
`slave slot.
`
`Further, in case where a call is made between the master
`set and the slave set,
`the master set determines which
`channel should be used and which of time slots correspond-
`ing to the determined channel should be used, correspond-
`ingly to each frame. On the other hand,
`the slave set
`monitors all of the charmels and all of the time slots
`corresponding to each channel at all times other than a
`period of time assigned to communication slots to be used
`for the slave set itself. Further, after a speech signal repre-
`senting a message or speech is converted into digital signal
`and further a time base compression is performed on this
`digital signal in the calling set, the compressed signal is
`transmitted therefrom to the called set whereupon the com-
`pressed signal is expanded and subsequently, the expanded
`signal is converted into an analog signal representing the
`original message or speech. Thus, substantially bidirectional
`simultaneous telecommunications can be achieved.
`
`Each transmitter-receiver (namely, each of the master and
`slave sets) employed in such a cordless telephone system
`needs to be provided with two oscillators which are respec-
`tively used for a transmission and a reception. Especially,
`because of the fact
`that
`there have been demands for
`reduction in weight, power consumption and cost of the
`slave set, a PLL oscillation circuit (namely, a PLL synthe-
`sizer oscillation circuit) constituted by a single PLL having
`a VCO is used in the slave set both as a local oscillator for
`reception and a carrier oscillator for transmission.
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`However, if a PLL oscillation circuit is used both for a
`transmission and a reception, the frequency of oscillation of
`the VCO should be changed when the role of the PLL
`oscillation circuit is changed from a local oscillator to a
`carrier oscillator. Further, in the case of a DECT digital
`cordless telephone system, a time slot just preceding each of
`transmission and reception time slots is employed as a
`lock-up time required for changing the role of the PLL
`oscillation circuit. Therefore, a PLL of the high-speed lock-
`up type (namely, a PLL, of which the lock-up time constant
`is reduced by decreasing what is called the CR time constant
`of a loop filter) is employed in the PLL oscillation circuit of
`each transmitter-receiver.
`
`Here, FIG. 3 is a schematic block diagram for illustrating
`the configuration of a TDMA/TDD type transmitter-re-
`ceiver. FIG. 4 is a circuit diagram for showing the detailed
`configuration of an example of a known oscillation circuit
`employed in the transmitter-receiver of FIG. 3.
`In FIG. 3, reference numeral 1 designates a phase control
`loop integrated circuit (namely, a phase-locked loop inte-
`grated circuit (hereunder abbreviated as PLL IC)); 2 a charge
`pump circuit; 3 a loop filter; 4 a VCO (namely, a voltage-
`controlled oscillator); 5 a crystal oscillator; 6 a variable bias
`voltage supply circuit; 35 a prescaler; 36 a PLL control
`circuit; 38 a CPU (namely, a microcomputer control unit);
`39 a transmit/receive switch; 40 an RF receiving amplifier;
`41 a receiving filter; 42 a frequency converter; 43 an
`intermediate frequency filter; 44 an intermediate frequency
`amplifier; 45 a demodulator; 46 a transmitting filter; 47 a
`power amplifier; 48 a Gaussian filter; 49, 50 and 51 ampli-
`fiers; 52 a signal output terminal; and 53 a signal input
`terminal. Incidentally, note that the variable bias voltage
`supply circuit 6 is not provided in a known TDMA/TDD
`type transmitter/receiver but is added to or provided in a
`TDMA/TDD type transmitter/receiver of the present inven-
`tion, which will be described later.
`
`Further, in FIG. 4, reference numeral 7 denotes a power
`terminal; 8 a charge pump feeding terminal; 9 a PLL clock
`signal terminal; 10 a PLL strobe signal terminal; 11 a PLL
`data signal terminal; 12 a power saving (hereunder some-
`times abbreviated as PS) signal terminal; 13 a modulation
`signal terminal; 14 a lock detection signal terminal; 15 an RF
`signal tem1inal; 16 a pull-up PNP transistor; 17 a pull-down
`NPN transistor; 18, 29 and 32 capacitors; 19, 27, 28, 30 and
`31 resistors; and 20 a variable capacitance diode. Moreover,
`in this figure, like reference characters designate like or
`corresponding composing elements of FIG. 3.
`Furthermore, as illustrated in FIG. 3,
`the PLL IC 1
`contains the prescaler 35 and the PLL control circuit 36. This
`PLL control circuit 36 contains a phase comparator (not
`shown) for comparing the phase of a reference frequency
`signal supplied from the crystal oscillator 5 with that of an
`oscillation signal supplied from the VCO 4 through the
`prescaler 35 and for generating error signals «pp and ¢r and
`also contains a variable frequency divider (not shown)
`adapted to change a frequency division ratio according to
`PLL data (see “PLL DATA” in FIG. 4) supplied from the
`CPU 38. A loop circuit portion consisting of the PLL IC 1,
`the charge pump circuit 2, the loop filter 3 and the VCO 4
`composes a PLL synthesizer oscillation circuit. Further, a
`circuit portion consisting of the transmit/receive switch 39,
`the RF receiving amplifier 40, the receiving filter 41, the
`frequency converter 42, the intermediate frequency filter 43,
`the intermediate frequency amplifier 44, the demodulator 45
`and the signal output terminal 52 constitutes a receiving
`circuit. Moreover, another circuit portion consisting of the
`amplifier 51, the transmitting filter 46 and the power ampli-
`
`8
`
`

`
`5,598,405
`
`3
`fier 47 makes up a transmitting circuit. Additionally, a
`reception signal is supplied from the demodulator 45 to the
`signal output terminal 52 and on the other hand, a transmis-
`sion signal is supplied from the signal input terminal 53 to
`the modulation signal terminal 13 (see FIG. 4) of the VCO
`4. The CPU 38 supplies to the PLL control circuit 36 various
`signals including a PS signal.
`Furthermore, as shown in FIG. 4, the charge pump circuit
`2 has the PNP transistor 16 and the NPN transistor 17. The
`error signals ¢p and (pr are supplied from the PLL control
`circuit 36 to the bases of these transistors. Further,
`the
`connection point between the transistors 16 and 17 forms an
`output terminal. The loop filter 3 has the capacitor 18 and the
`resistor 19 which are connected in series with each other.
`One of terminals of this series circuit is connected to the
`output terminal of the charge pump circuit 2 and is also
`connected to the output terminal of the loop filter 3 through
`the series resistance or resistor 27. On the other hand, the
`other terminal of the series circuit is grounded. The VCO 4
`has the variable capacitance diode 20. Further, the cathode
`of the diode 20 is connected to the oscillation circuit of the
`VCO 4 through the series capacitor 29, and the output
`terminal of the loop filter 3 through the series resistor 28. On
`the other hand, the anode of the diode 20 is connected to the
`modulation signal terminal 13 through the resistor 30 and is
`further grounded through a parallel circuit composed of the
`resistor 31 and the capacitor 32. The PLL IC 1 is connected
`to the PLL clock signal terminal 9, the PLL strobe signal
`terminal 10, the PLL data signal terminal 11, the power
`saving signal terminal 12, the lock detection signal terminal
`14 and the RF signal terminal 15. Moreover, the PLL IC 1
`is also connected to the output terminal of the VCO 4 and to
`the output terminal of the crystal oscillator 5. Hereinafter,
`the outline of an operation of the transmitter-receiver con-
`structed as stated hereinabove will be described.
`
`First, at the time of a transmission, the PLL synthesizer
`oscillation circuit operates as a carrier oscillator. At that
`time, if a transmission signal is supplied to the signal input
`terminal 53, the transmission signal is fed to the VCO 4 of
`the PLL synthesizer oscillation circuit through the Gaussian
`filter 48. Thus the output carrier frequency of the PLL
`synthesizer oscillation circuit is modulated according to the
`transmission signal. A resultant modulated carrier wave
`signal is transmitted from an antenna through the amplifiers
`49 and 51 and the transmitting filter 46, the power amplifier
`47 and the transrnit/receive switch 39 which is placed by the
`CPU 38 in the transmission position thereof.
`Next, at the time of a reception, the PLL synthesizer
`oscillation circuit operates as a local oscillator. At that time,
`an RF reception signal received at the antenna is supplied to
`the frequency converter 42 through the transrnit/receive
`switch 39 which is placed by the CPU 38 in the reception
`position thereof,
`the RF receiving amplifier 40 and the
`receiving filter 41. On the other hand, a local oscillation
`signal is similarly supplied to the frequency converter 42
`from the PLL synthesizer oscillation circuit through the
`amplifiers 49 and 50. Thus, an intermediate frequency signal
`is obtained in the frequency converter 42 as a result of a
`frequency conversion performed on the RF reception signal
`by using the local oscillation signal. This intermediate
`frequency signal is supplied through the intermediate fre-
`quency filter 43 and the intermediate frequency amplifier 44
`to the demodulator 45 whereupon the intermediate fre-
`quency signal is demodulated. Thereafter, the demodulated
`signal is supplied to the signal output terminal 52.
`Further,
`the PLL synthesizer oscillation circuit con-
`structed as described above operates as follows.
`
`10
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`Namely, the PLL IC 1 compares the phase of a reference
`frequency signal, which is supplied from the crystal oscil-
`lator 5 to the incorporated PLL control circuit 36, with the
`phase of an oscillation frequency signal supplied thereto
`from the VCO 4 through the prescaler 35 and a variable
`frequency divider (not shown). Thereafter, the PLL IC 1
`generates an error signal ¢p or or according to the direction
`and magnitude of the difference between the phases of the
`two signals. Here, if the error signal ¢p is obtained, the
`pull-up PNP transistor 16 of the charge pump circuit 2 is
`turned on. Further, a voltage supplied from the charge pump
`feeding terminal 8 through the transistor 16 to the capacitor
`18 of the loop filter 3 increases the voltage developed across
`between the terminals of the capacitor 18. This results in
`increase in output terminal voltage of the loop filter 3.
`Moreover, the increased voltage is supplied to the cathode of
`the variable capacitance diode 20 of the VCO 4. Conse-
`quently, the frequency of oscillation of the VCO 4 changes
`in a certain direction. In contrast, if the error signal ¢r is
`obtained, the pull-down NPN transistor 17 of the charge
`pump circuit 2 is turned on. Thus the capacitor 18 becomes
`connected through the NPN transistor 17 to the ground, so
`that
`the voltage developed across the terminals of the
`capacitor 18 is reduced from the charging voltage thereof.
`This results in decrease in output terminal voltage of the
`loop filter 3. Further, the decreased voltage is supplied to the
`cathode of the variable capacitance diode 20. Consequently,
`thefrequency of oscillation of the VCO 4 changes in another
`direction. Moreover, the oscillation frequency signal is sup-
`plied from the output terminal of the VCO 4 to the PLL IC
`1. Then, the aforementioned PLL frequency control opera-
`tion is performed.
`Meanwhile, in the case of the known transmitter-receiver,
`when being in the transmission state, the VCO functions as
`a carrier wave oscillator. Further, a digital signal to be
`transmitted is supplied to the VCO of the PLL oscillation
`circuit. Then, a frequency shift keying (hereunder abbrevi-
`ated as FSK) modulation is performed on the oscillation
`signal of the VCO by using the digital signal. Thus an FSK
`modulation carrier wave signal is generated. In this case, the
`PLL oscillation circuit
`is constituted by a PLL of the
`high-speed lock type as described above. This has an ill
`influence in that when a digital signal having a relatively low
`frequency is input to the VCO, effects of the FSK modula-
`tion performed by use of the VCO is canceled by a frequency
`control signal of the PLL.
`To eliminate this ill influence, in the case of the lcnown
`transmitter-receiver, the generation of a frequency control
`signal is prevented by changing the state of the PLL into a
`stand-by state when the VCO is made to function as a carrier
`wave oscillator only at the time of a transmission. Thereby,
`during a period of time of a transmission time slot, the
`frequency of oscillation of the VCO is controlled according
`to the charging voltage of the loop filter.
`FIG. 7 is a diagram for illustrating transmission and
`reception time slots assigned to a transmitter-receiver of the
`known cordless telephone system and for illustrating oper-
`ating and stand-by states of the PLL of this transmitter-
`receiver.
`
`As illustrated in FIG. 7, in the case of the known cordless
`telephone system, when the transmitter-receiver is in a time
`slot just preceding each of the transmission and reception
`time slots, the PLL thereof having been in a stand-by state
`until then is put into an operating state. Thereafter, when the
`transmission time slot comes, the state of the PLL is changed
`from the operating state to the stand-by state again to thereby
`eliminate the aforementioned ill influence. In contrast, when
`
`9
`
`

`
`5,598,405
`
`5
`the reception time slot comes, the operating state of the PLL
`is maintained. Further, the state of the PLL is not changed
`from the operating state to the stand-by state until the end of
`the reception time slot.
`However, in the case of the known cordless telephone
`system (of the TDMA/TDD type), the PLL is put in an
`operating state during the reception time slot in which the
`VCO functions as a local oscillator. Thus the power con-
`sumption of the PLL is large. Moreover, when the PLL is in
`an operating state, the leakage component of the reference
`frequency signal to be compared with the oscillation signal
`of the VCO is applied to the VCO through the loop filter.
`Further, reference spurious signals are sometimes generated
`at a frequency close to the frequency of oscillation of the
`VCO. However, the cut-ofi frequency of the loop filter can
`not be reduced because of the fact that the PLL is of the
`high-speed lock-up type. Consequently, the spurious char-
`acteristics of the PLL can not be improved. Furthermore, the
`known transmitter-receiver of the TDMA/TDD type has
`encountered various problems. For example, owing to the
`trade-off between the spurious characteristics and the lock-
`up time constant characteristics of the PLL, it takes much
`time and money to design the PLL in such a manner that
`both of the spurious characteristics and the lock-up time
`constant characteristics thereof can be improved.
`Moreover, the known transmitter-receiver of the TDMA]
`TDD type has another problem in that the charging voltage
`of the capacitor 18 of the loop filter 3 varies serially due to
`leakage currents flowing through the charge pump circuit 2,
`the loop filter 3 and the VCO 4 in the period of time in which
`the synthesizing function of the PLL synthesizer oscillation
`circuit is in a dormant state. Further, the variation in the
`charging voltage is accompanied by the variation in the
`frequency of oscillation of the VCO 4. Furthermore, among
`the leakage currents, the leakage current flowing through the
`VCO 4 is much more than the leakage currents flowing
`through the VCO 4 and the loop filter 3. Consequently, the
`variation of the frequency of oscillation of the VCO 4
`depends mainly on the leakage current flowing through the
`charge pump circuit 2.
`FIGS. 5(a) to 5(c) are characteristic diagrams for illus-
`trating examples of changes in the charging voltage of the
`capacitor 18 and in the frequency of oscillation of the VCO
`4 in such a state. FIGS. 5(a), 5(b) and 5(c) illustrate the
`waveform of the power saving (PS) signal, the change in the
`charging voltage of the capacitor 18 and the variation in the
`frequency of oscillation of the VCO 4, respectively.
`As illustrated in FIG. 5(a), when the power saving (PS)
`signal comes to have a low level “0” and the synthesizing
`function is put into a dormant state, the PLL is caused to be
`in an open state (namely, a released state). At that time, as
`illustrated in FIGS. 5(b) and 5(c), after the signal level of the
`power saving (PS) signal is changed into the low level “O”,
`the charging voltage of the capacitor 18 comes to vary
`gradually. Consequently, the frequency of oscillation of the
`VCO 4 comes to vary serially. Thus the aforementioned
`problem is caused.
`The present invention is accomplished to eliminate the
`aforesaid problems.
`Accordingly, an object of the present invention is to
`provide a transmitter-receiver of the TDMA/I‘DD type
`which can reduce the power consumption thereof as much as
`possible and improve the spurious characteristics and insure
`suflicient frequency precision required of a communication
`apparatus of the TDMA type even in when the function of
`the PLL is a dormant state (namely, the PLL is in a stand-by
`state).
`
`6
`SUMMARY OF THE INVENTION
`
`To achieve the foregoing object, in accordance with an
`aspect of the present invention as described in the appended
`claims, there is provided a TDMA/TDD type transn1itter-
`receiver having a PLL (namely, a phase control loop) which
`includes at least a VCO (namely, a voltage-controlled oscil-
`lator) being adapted to act as a carrier oscillator when
`performing a transmissions and to act as a local oscillator
`when performing a reception and a loop filter. The PLL
`(namely,
`the phase control loop) is adapted to control a
`frequency of oscillation of the VCO (namely, the voltage-
`controlled oscillator). In this transmitter-receiver, the PLL
`(namely, the phase control loop) is closed during a period of
`a time slot just preceding a transmission time slot and during
`a period of a time slot just preceding a reception time slot.
`Further, the PLL (namely, the phase control loop) is opened
`during periods of the transmission and reception time slots.
`Moreover, when the loop is opened, the frequency of oscil-
`lation of the voltage-controlled oscillator is controlled
`according to a charging voltage of the loop filter.
`Thus,
`in accordance with the present
`invention as
`described in the appended claims, when the period of a time
`slot just preceding each of the transmission and reception
`time slots assigned to the transmitter-receiver itself begins,
`the loop having been open is controlled in such a manner to
`be closed to put the PLL of the transmitter-receiver into an
`operating state. Moreover, when the transmission time slot
`or the reception time slot comes, the loop is controlled in
`such a manner to be opened to put the PLL into a stand-by
`state.
`
`Further, in accordance with a second aspect of the present
`invention, there is provided a TDMA/TDD type transn1itter-
`receiver which comprises a VCO (a voltage-controlled oscil-
`lator) having a variable voltage reactance element and being
`adapted to be able to change an output frequency thereof
`according to a control voltage supplied to one of electrodes
`of the variable voltage reactance element, a phase compara-
`tor for comparing a reference frequency signal with an
`output frequency signal of the VCO (namely, the voltage-
`controlled oscillator) and for generating error signals, state
`switching means for changing a state of the phase compara-
`tor between an operating state and a stand-by state in
`response to application of a changing signal and bias supply
`means for supplying a variable bias voltage to the other of
`the electrodes of the variable voltage reactance element. In
`the case of this transmitter-receiver, the bias supply means
`has an oscillation circuit for generating a variable bias
`voltage which varies in a nearly same manner as of variation
`of a control voltage supplied to the variable voltage reac-
`tance element, when the phase comparator is in a stand-by
`state.
`
`Thus, in accordance with the second aspect of the present
`invention, when the PLL is in a stand-by state, namely, when
`the phase comparator is in a stand-by state, the variable bias
`voltage varying in nearly the same manner as of the variation
`of the control voltage (namely, the charging voltage of the
`capacitor of the loop filter) fed to an electrode of the variable
`voltage reactance element of the VCO (namely, the voltage-
`controlled oscillator) is supplied to the other electrode of the
`variable voltage reactance element. Thus, when the control
`voltage supplied to one of the electrodes of the variable
`voltage reactance element varies gradually owing to the
`leakage current with the lapse of time, the variable bias
`voltage fed to the other electrode of the variable voltage
`reactance element comes to gradually vary with time in the
`similar direction and range as of the variation in the control
`voltage.
`
`20
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`Consequently, during a period in which the phase com-
`parator is in a stand-by state, the voltage developed across
`the terminals of the variable voltage reactance element 20
`does not vary as time passes. Thereby, the frequency of
`oscillation of the voltage-controlled oscillator (namely, the
`VCO) is maintained at a constant frequency during this
`period.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Other features, objects and advantages of the present
`invention will become apparent from the following descrip-
`tion of a preferred embodiment with reference to the draw-
`ings in which like reference characters designate like or
`corresponding parts throughout several views, and in which:
`FIG. 1 is a circuit diagram for illustrating the configura-
`tion of an example of an oscillation circuit employed in a
`transmitter-receiver of the TDMA/TDD type embodying the
`present invention;
`FIGS. 2(a) to 2(i) show characteristic diagrams for illus-
`trating changes in states of various portions of the PLL
`synthesizer oscillation circuit of FIG. 1, which occur with
`the passage of time;
`FIG. 3 is a schematic block diagram for illustrating the
`configuration of a transmitter-receiver of the TDMA/TDD
`type;
`
`FIG. 4 is a circuit diagram for illustrating the detailed
`configuration of an example of an oscillation circuit
`employed in the transmitter-receiver of the TDMA/TDD
`type of FIG. 3;
`FIGS. 5(a) to 5(c) are characteristic diagrams for illus-
`trating examples of changes in the charging voltage of a
`capacitor 18 and in the frequency of oscillation of the VCO
`of an oscillation circuit of a known transmitter-receiver of
`the TDMA/TDD type;
`FIG. 6 is a diagram for illustrating transmission and
`reception time slots assigned to a transmitter-receiver of a
`cordless telephone system embodying the present invention
`and operating and stand-by states of a PLL of this transmit-
`ter-receiver; and
`
`FIG. 7 is a diagram for illustrating transmission and
`reception time slots assigned to a transmitter-receiver of a
`known cordless telephone system and operating and stand-
`by states of a PLL of this transmitter-receiver.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODHVIENT
`
`Hereinafter, a preferred embodiment of the present inven-
`tion will be described in detail by referring to the accom-
`panying drawings. FIG. 6 is a diagram for illustrating
`transmission and reception time slots assigned to a trans-
`rnitter-receiver of this embodiment of the present invention
`and for illustrating operating and stand-by states of a PLL of
`this transmitter-receiver.
`
`As illustrated in FIG. 6, in the case of the known cordless
`telephone system, when the transmitter-receiver is in a time
`slot just preceding each of the transmission and reception
`time slots, the PLL thereof having been in a stand-by state
`until then is put into an operating state. Thereafter, when the
`transmission time slot comes, the state of the PLL is changed
`from the operating state to the stand-by state again. In this
`respect, this transmitter-receiver is similar to the known
`transmitter-receiver of FIG. 7. However, in the case of this
`embodiment, when the reception time slot comes, the state
`of the PLL is changed from the operating state to the
`
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`stand-by state once again. In this respect, this embodiment
`is different from the known transmitter-receiver of the
`known transmitter-receiver of FIG. 7.
`
`FIG. 1 is a circuit diagram for illustrating the configura-
`tion of an example of an oscillation circuit employed in the
`transmitter-receiver of the TDMA/TDD type embodying the
`present invention, in which the oscillation circuit composes
`a PLL synthesizer oscillation circuit.
`In FIG. 1, reference numeral 1 designates a PLL IC
`(namely, a phase control loop integrated circuit); 2 a charge
`pump circuit; 3 a loop filter; 4 a VCO (namely, a voltage-
`controlled oscillator); 5 a crystal oscillator; 6 a variable bias
`voltage supply circuit (namely, bias supply means); 7 a
`power terminal; 8 a charge pump feeding terminal; 9 a PLL
`clock signal terminal; 10 a PLL strobe signal terminal; 11 a
`PLL data signal terminal; 12 a power saving signal terminal;
`13 a modulation signal terminal; 14 a lock detection signal
`terminal; 15 an RF signal
`terminal; 16 a pull-up PNP
`transistor; 17 a pull-down NON transistor; 18 a first capaci-
`tor; 19 a first resistor; 20 a variable capacitance diode
`(namely, a variable voltage reactance element); 21 a switch-
`ing transistor; 22 a second capacitor; 23 a second resistor; 24
`a protective resistor