Paper No. 1
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________
`
`UNITED SERVICES AUTOMOBILE ASSOCIATION
`
`Petitioner
`
`v.
`
`MAXIM INTEGRATED PRODUCTS, INC.
`
`Patent Owner
`
`
`
`U.S. Patent 6,105,013
`
`
`TITLE: METHOD, APPARATUS, SYSTEM AND FIRMWARE FOR
`SECURE TRANSACTIONS
`
`Issue Date August 15, 2000
`
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
`
`
`
`
`

`
`Petitioner’s Exhibit List
`
`Description
`U.S. Patent No. 6,105,013 (filed Mar. 10, 1998) (issued Aug. 15,
`2000) (“‘013 Patent”)
`Declaration of Dr. James L. Olivier (“Olivier Declaration”)
`PETER L. HAWKES ET AL., INTEGRATED CIRCUIT CARDS, TAGS AND
`TOKENS, NEW TECHNOLOGY AND APPLICATIONS, (Peter L. Hawkes
`et al. eds., BSP Professional Books 1990) (“Hawkes”)
`European Pat. Pub. 0588339 A2 (“Ishiguro”)
`U.S. Patent No. 4,575,621 (filed Mar. 7, 1984) (issued Mar. 11,
`1986) (“Dreifus”)
`U.S. Patent No. 4,906,828 (filed May 31, 1988) (issued Mar. 6,
`1990) (“Halpern”)
`Don Lancaster, BASIC Stamp Microcontroller, Hardware Hacker,
`Selected Reprints, Vol. IV, (July 1993) (“Lancaster”)
`Prosecution history for ‘013 Patent
`Square, Inc. v. J. Carl Cooper, IPR 2014-00157, Papers 12 and 17
`Compass Bank, American Express Company, American Express
`Travel Related Services Company, Inc., Discover Financial Services,
`Discover Bank, Discover Products Inc., and State Farm Mutual
`Automobile Insurance Company v. Maxim Integrated Products, Inc.,
`CBM 2015-00101, Paper 17
`
`Exhibit No.
`1001
`
`1002
`1003
`
`1004
`1005
`
`1006
`
`1007
`
`1008
`1009
`1010
`
`
`
`
`
`35414954.1
`
`-i-
`
`
`
`
`
`
`
`

`
`TABLE OF CONTENTS
`
`Page
`
`INTRODUCTION .......................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(A)(1) ....................... 1
`A.
`Real Party-in-Interest Under 37 C.F.R. § 42.8(b)(1) ........................... 1
`B.
`Related Matters Under 37 C.F.R. § 42.8(b)(2) .................................... 1
`C.
`Lead and Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3) ................. 2
`D.
`Service Information Under 37 C.F.R. § 42.8(b)(4) .............................. 2
`E.
`Payment of Fees ................................................................................... 2
`III. REQUIREMENTS FOR INTER PARTES REVIEW UNDER 37
`C.F.R. §42.104 ................................................................................................ 3
`A. Grounds for Standing Under 37 C.F.R. §42.104(a) ............................. 3
`B.
`Identification of Challenge Under 37 C.F.R. §42.104(B) .................... 3
`1.
`Claims for Which Review is Requested (37 C.F.R. §
`42.104(b)(1)) .............................................................................. 3
`Statutory Grounds of Challenge (37 C.F.R. §
`42.104(b)(2)) .............................................................................. 3
`IV. REASONS FOR THE RELIEF REQUESTED UNDER 37 C.F.R. §§
`42.22(A)(2) AND 42.104(B)(4) ..................................................................... 5
`A.
`Background .......................................................................................... 5
`1.
`The ‘013 Patent .......................................................................... 5
`Relevant Prosecution History ............................................................... 7
`Claim Construction (37 C.F.R. § 42.104(b)(3)) ................................... 8
`Summary of the Prior Art ..................................................................... 9
`1.
`Hawkes ....................................................................................... 9
`2.
`Lancaster .................................................................................. 12
`3.
`Dreifus ...................................................................................... 13
`4.
`Halpern ..................................................................................... 13
`5.
`Ishiguro .................................................................................... 14
`
`B.
`C.
`D.
`
`2.
`
`35414954.1
`
`
`
`-ii-
`
`
`
`

`
`Summary regarding the prior art references ....................................... 15
`The Challenged Claims Are Invalid Under 35 U.S.C. § 102 and
`103(a) .................................................................................................. 16
`6.
`Grounds 1 and 2: Claims 1-4, 6, 9 10, 11, 12, 14, and 15
`are anticipated under 35 U.S.C. § 102(b) by Hawkes, and
`are alternatively obvious under 35 U.S.C. § 103(a) over
`Hawkes ..................................................................................... 16
`a.
`Claim 1 ........................................................................... 16
`b.
`Claims 2 and 14 ............................................................. 22
`c.
`Claims 3 and 12 ............................................................. 23
`d.
`Claims 4 and 10 ............................................................. 24
`e.
`Claims 6 and 15 ............................................................. 24
`f.
`Claim 9 ........................................................................... 25
`g.
`Claim 11 ......................................................................... 28
`Ground 3: Claim 5 is obvious under 35 U.S.C. § 103(a)
`over Hawkes in view of Lancaster ........................................... 29
`Ground 4: Claim 8 is obvious under 35 U.S.C. § 103(a)
`over Hawkes in view of Dreifus .............................................. 31
`Ground 5: Claims 1-4, 6, 9, 10, 12, 14, and 15 are
`obvious under 35 U.S.C. § 103(a) over Halpern in view
`of Ishiguro ................................................................................ 32
`a.
`Claim 1 ........................................................................... 33
`b.
`Claim 2 ........................................................................... 42
`c.
`Claims 3 and 12 ............................................................. 42
`d.
`Claims 4 and 10 ............................................................. 43
`e.
`Claims 6 and 15 ............................................................. 44
`f.
`Claim 9 ........................................................................... 47
`10. Ground 6: Claim 5 is obvious under 35 U.S.C. § 103(a)
`over Halpern, in view of Ishiguro, and in further view of
`Lancaster .................................................................................. 44
`
`7.
`
`8.
`
`E.
`F.
`
`9.
`
`35414954.1
`
`
`
`-iii-
`
`
`
`

`
`11. Ground 7: Claims 8 and 11 are obvious under 35 U.S.C.
`§ 103(a) over Halpern, in view of Ishiguro, and in further
`view of Dreifus ......................................................................... 46
`a.
`Claim 8 ........................................................................... 46
`b.
`Claim 11 ......................................................................... 54
`CONCLUSION ............................................................................................. 57
`
`V.
`
`
`
`
`35414954.1
`
`
`
`-iv-
`
`
`
`

`
`I.
`
`INTRODUCTION
`
`Pursuant to 35 U.S.C. § 312 and 37 C.F.R. § 42.100 et seq., United Services
`
`Automobile Association (“Petitioner”) requests inter partes review of claims 1-6, 8-
`
`12, and 15 (the “Challenged Claims”) of U.S. Patent No. 6,105,013 (“the ‘013
`
`Patent,” Ex. 1001), which issued on August 15, 2000.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(a)(1)
`
`A. Real Party-in-Interest Under 37 C.F.R. § 42.8(b)(1)
`
`United Services Automobile Association, USAA Federal Savings Bank, and
`
`USAA Capital Corporation are the real parties-in-interest.
`
`B. Related Matters Under 37 C.F.R. § 42.8(b)(2)
`
`The ’013 Patent is involved in the following proceedings that may affect or be
`
`affected by a decision in this proceeding:
`
` CBM 2015-00101; and
`
` Maxim Integrated Products, Inc., v. USAA Federal Savings Bank, W.D.
`
`Texas, C.A. No. 5:14-CV-1031-XR; Maxim Integrated Products, Inc.,
`
`v. The American Express Company and American Express Travel
`
`Related Services Company, Inc., W.D. Texas, C.A. No. 5:14-CV-
`
`01027; Maxim Integrated Products, Inc., v. Compass Bank, d/b/a
`
`BBVA Compass, W.D. Texas, C.A. No. 5:14-CV-01028; Maxim
`
`Integrated Products, Inc., v. Discover Bank, W.D. Texas, C.A. No.
`
`35414954.1
`
`
`
`-1-
`
`
`
`

`
`5:14-CV-01029; Maxim Integrated Products, Inc., v. State Farm
`
`Mutual Automobile Ins. Co., W.D. Texas, C.A. No. 5:14-CV-01030-
`
`XR; Maxim Integrated Products, Inc., v. M&T Bank Corp., C.A. No.
`
`1:15-CV-02167; Maxim Integrated Products, Inc., v. HSBC Bank USA,
`
`Nat’l Ass’n, C.A. No. 1:15-CV-02168; Maxim Integrated Products,
`
`Inc., v. Santander Bank, NA, C.A. No. 1:15-CV-02169; Branch Bank
`
`and Trust Company v. Maxim Integrated Products, Inc., C.A. No. 2:12-
`
`CV-00945, No. 2:12-mc-00244 (W.D. Pa.).
`
`C. Lead and Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3)
`
`Petitioner designates Nathan Rees (Reg. No. 63,820) as Lead Counsel, and
`
`Allan Braxdale (Reg. No. 64,276), and Ross Viguet (Reg. No. 42,203), as Back-Up
`
`Counsel.
`
`D.
`
`Service Information Under 37 C.F.R. § 42.8(b)(4)
`
`Email: USAA013IPR@nortonrosefulbright.com
`
`Post: Nathan J. Rees, Norton Rose Fulbright US LLP, 2200 Ross Avenue,
`
`Suite 3600, Dallas, Texas 75201
`
`Phone: 214.855.7164 Fax: 214.855.8200
`
`Petitioner consents to electronic service.
`
`E.
`
`Payment of Fees
`
`The fees for this petition have been paid by credit card. The Board is
`
`35414954.1
`
`
`
`-2-
`
`
`
`

`
`authorized to deduct any underpayment of fees associated with this petition and any
`
`related fees from Norton Rose Fulbright US LLP Deposit Account No. 06-2380,
`
`under Order No. 11504607.
`
`III. REQUIREMENTS FOR INTER PARTES REVIEW UNDER 37 C.F.R.
`§42.104
`
`A. Grounds for Standing Under 37 C.F.R. §42.104(a)
`
`This petition has been filed within one year of the earliest date Petitioner was
`
`served with a complaint in case number 5:14-cv-1031-XR. Petitioner certifies that
`
`the ‘013 Patent is available for inter partes review, and that Petitioner is not barred
`
`or estopped from requesting this inter partes review.
`
`B.
`
`Identification of Challenge Under 37 C.F.R. §42.104(b)
`
`1. Claims for Which Review is Requested (37 C.F.R. §
`42.104(b)(1))
`
`Petitioner requests review and the cancellation as invalid of claims 1-6, 8-12,
`
`and 15 of the ‘013 Patent.
`
`2. Statutory Grounds of Challenge (37 C.F.R. § 42.104(b)(2))
`
`Petitioner requests inter partes review of Challenged Claims 1-6, 8-12, and 15
`
`of the ‘013 Patent on the grounds set forth in the table shown below, and requests
`
`that each of the Challenged Claims be found unpatentable. An explanation of how
`
`these claims are unpatentable under the statutory grounds identified below is
`
`provided in the form of detailed description that follows, indicating where each of
`
`35414954.1
`
`
`
`-3-
`
`
`
`

`
`the claim elements can be found in the cited prior art, and the relevance of that prior
`
`art. Additional explanation and support for each ground of rejection is set forth in
`
`Ex. 1002, referenced throughout this Petition.
`
`Hawkes as Primary Reference:
`
`Ground
`
`‘013 Patent Claims
`
`Basis for Rejection
`
`Ground 1
`Ground 2
`Ground 3
`
`Ground 4
`
`1-4, 6, 9-12, and 15
`1-4, 6, 9-12, and 15
`5
`
`8
`
`35 U.S.C. § 102(b) based on Hawkes
`35 U.S.C. § 103(a) based on Hawkes
`35 U.S.C. § 103(a) based on Hawkes in
`view of Lancaster
`35 U.S.C. § 103(a) based on Hawkes in
`view of Dreifus
`
`Halpern as Primary Reference:
`
`Ground
`
`‘013 Patent Claims
`
`Basis for Rejection
`
`Ground 5
`
`1-4 and 6
`
`Ground 6
`
`5
`
`Ground 7
`
`8-12 and 15
`
`35 U.S.C. § 103(a) based on Halpern in
`view of Ishiguro
`35 U.S.C. § 103(a) based on Halpern, in
`view of Ishiguro, and in further view of
`Lancaster
`35 U.S.C. § 103(a) based on Halpern, in
`view of Ishiguro, and in further view of
`Dreifus
`
`The ‘013 Patent issued Aug. 15, 2000 from Application No. 09/041,190
`
`(“‘190 Appln.”), which was filed Mar. 10, 1998. The ‘190 Appln. is a continuation
`
`of the 08/594,983 Application, filed Jan. 31, 1996, which claims priority to
`
`Provisional Application No. 60/004,510, filed Sep. 29, 1995. Accordingly, the
`-4-
`
`35414954.1
`
`
`
`

`
`earliest possible date to which the ‘013 Patent could claim priority (hereinafter the
`
`“earliest effective filing date”) is September 29, 1995.
`
`Further, Petitioner does not concede that the ‘013 Patent is entitled to this
`
`priority date, but has elected not to argue the issue in the Petition because all prior
`
`art references identified in the Grounds presented below pre-date the earliest
`
`possible priority date for the ‘013 Patent. However, Petitioner explicitly reserves the
`
`right to present such an argument in this proceeding or other proceedings involving
`
`the ‘013 Patent.
`
`Hawkes was published in 1990 by BSP Professional Books. Ex. 1003.
`
`Lancaster was published in 1993 by Electronics Now magazine. Ex. 1007. The
`
`Ishiguro patent application was published on March 23, 1994. Ex. 1004. The
`
`Dreifus and Halpern patents were each issued/published by the United States Patent
`
`and Trademark Office more than one year before the earliest priority date of the
`
`‘013 Patent. Ex. 1005 and Ex. 1006. Therefore, each of the cited references of
`
`Grounds 1-7 are available as prior art under 35 U.S.C. §102(b).
`
`IV. REASONS FOR THE RELIEF REQUESTED UNDER 37 C.F.R. §§
`42.22(A)(2) AND 42.104(B)(4)
`
`A. Background
`
`1. The ‘013 Patent
`
`The ‘013 Patent is directed to an electronic module for exchanging encrypted
`
`information with a service provider’s equipment in order to facilitate secure
`-5-
`
`
`
`35414954.1
`
`
`
`

`
`transactions. Ex. 1001, Abstract. As illustrated in FIG. 1 of the ‘013 Patent,
`
`reproduced below, the electronic module includes a microprocessor, a clock, a math
`
`coprocessor, memory circuitry, an input/output circuit, and an energy circuit. Ex.
`
`1001, 2:34-67, 3:1-9.
`
`
`
`The math coprocessor performs known mathematics operations for RSA
`
`encryption and decryption (e.g., public/private key encryption/decryption); the
`
`memory circuitry includes volatile and non-volatile memories; the input/output
`
`circuit enables bidirectional communication between the electronic module and an
`
`external device; the energy circuit includes a battery to maintain the memory
`
`circuitry and aid in powering other circuitry of the electronic module. Ex. 1001,
`
`2:54-57, 2:58-63, 2:66-3:4, 3:5-9. The ‘013 Patent discloses that the electronic
`
`module is programmed by a service provider to operate as a digital cash dispenser or
`
`35414954.1
`
`
`
`-6-
`
`
`
`

`
`a cash reservoir that allows the end user to participate in transactions whereby the
`
`electronic module is used to make payments for goods and services. Ex. 1001, 7:64-
`
`8:18. The electronic module is incorporated into an articulatable item, such as a
`
`ring, a watch, a wallet, a purse, a necklace, jewelry, an ID badge, a pen, a clipboard,
`
`a token, etc. Ex. 1001, 29:59-64.
`
`B. Relevant Prosecution History
`
`The ‘013 Patent was filed on March 10, 1998 and assigned U.S. Patent
`
`Application No. 09/041,190 (hereinafter “the ‘190 Application”). Claim 1 of the
`
`‘013 Patent corresponds to claim 32 of the ‘190 Application, and claim 9 of the ‘013
`
`Patent corresponds to claim 41 of the ‘190 Application, both of which were
`
`introduced in response filed on November 6, 1998. Ex. 1008 November 6, 1998
`
`Response at 1-5. In response to the Office Action mailed on July 23, 1999, claim 32
`
`of the ‘190 Application was amended to recite “a real time clock, connected to said
`
`microcontroller core, for providing a time measurement for time stamping a
`
`predetermined function,” and claim 41 of the ‘190 Application was amended to
`
`recite “a clock circuit for measuring time and providing time stamp information
`
`responsive to functions being performed by said microcontroller core.” Ex. 1008
`
`October 25, 1999 Response at 2 and 3. Based on this amendment, a Notice of
`
`Allowance was mailed on January 12, 2000, and the ‘190 Application Issued as the
`
`‘013 Patent on August 15, 2000. Ex. 1008 January 12, 2000 Notice of Allowance.
`
`35414954.1
`
`
`
`-7-
`
`
`
`

`
`Patent Owner disclaimed claims 7, 14, and 16 of the ‘013 Patent. CBM 2015-
`
`00101, Ex. 1010.
`
`C. Claim Construction (37 C.F.R. § 42.104(b)(3))
`
`In an inter partes review, a claim in an unexpired patent is given the “broadest
`
`reasonable construction in light of the specification of the patent in which it
`
`appears.” 37 C.F.R. § 42.100(b). Alternatively, a claim term in an expired patent is
`
`construed according to its ordinary and customary meaning, as understood by one of
`
`ordinary skill in the art. See Ex. 1009 Paper 12 at 3 and 4, and Paper 17 at 2 and 3.
`
`Petitioner notes that the 20 year patent term for the ‘013 Patent will expire prior to a
`
`final written decision in this proceeding. Below, Petitioner provides constructions
`
`for certain claim terms in accordance 37 C.F.R. § 42.104(b)(3). Petitioner
`
`respectfully submits that the constructions provided below would be the same under
`
`both the broadest reasonable interpretation standard, which is used to construe claim
`
`terms in an unexpired patent, and the ordinary and customary meaning standard,
`
`which is used to construe claim terms in an expired patent. The following
`
`summarizes how certain claim phrases of the ‘013 Patent should be construed for
`
`purposes of this Inter Partes Review:
`
`1.
`
`“coprocessor”: The claim term “coprocessor” should be construed as
`
`a processor that works with another processor. Ex. 1002 at 23.
`
`2.
`
`“modular exponentiation accelerator circuit”: The ‘013 Patent
`
`35414954.1
`
`
`
`-8-
`
`
`
`

`
`describes a modular exponentiation accelerator circuit as a math coprocessor. Ex.
`
`1001, 2:54-57, 3:24-26. Thus, the claim term “modular exponentiation accelerator
`
`circuit” should be construed as a processor that works with another processor and
`
`performs mathematics of modular exponentiation. Ex. 1002 at 24.
`
`3. “nonvolatile RAM”: The ‘013 Patent discloses that the electronic module
`
`includes memory circuitry 20 that is connected to an energy circuit 34, and teaches
`
`that the energy circuit 34 may include a battery and is necessary to maintain the
`
`memory circuitry 20. Ex. 1001, 3:5-9. Therefore, the claim term “nonvolatile
`
`RAM” should be construed to at least include RAM that is backed up by a battery or
`
`another power source. Ex. 1002 at 25.
`
`4. “real time clock” and “clock circuit”: The ‘013 Patent describes a
`
`continuously running real time clock and clock circuitry that provide information to
`
`track time for generating timestamp information. Ex. 1001, FIG. 12, 3:21-63, 4:44.
`
`Thus, the claim terms “real time clock” and “clock circuit” should be construed to
`
`mean continuously running clock circuitry that tracks time. Ex. 1002 at 26.
`
`D.
`
`Summary of the Prior Art
`
`1. Hawkes
`
`Hawkes describes various design aspects of integrated circuit (IC) cards, tags,
`
`and tokens, and describes various applications for which such devices are used. Ex.
`
`1003, Preface, pages ix-xi, pages 1-11, Table 1.4; Ex. 1002 at 27. For example,
`
`35414954.1
`
`
`
`-9-
`
`
`
`

`
`Hawkes teaches that the tokens or smart cards are operated as an electronic wallet
`
`capable of storing and dispensing data transferred value (e.g., electronic money) in
`
`connection with the purchase of goods or services. Ex. 1003, Preface, page x, pages
`
`7, 36, 37, 65, 69-70; Ex. 1002 at 27.
`
`An exemplary configuration of a token is shown in FIG. 6.3, reproduced
`
`below.
`
`
`
`The token of FIG. 6.3 includes input/output interface (e.g., serial I/O); a
`
`microprocessor circuit (e.g., control processor) connected to the input/output
`
`interface; a coprocessor circuit (e.g., RSA processor) connected
`
`to
`
`the
`
`microprocessor circuit; a timing circuit (e.g., clock) connected to the microprocessor
`
`circuit; a first memory (e.g., data memory shown) connected to the microprocessor
`
`circuit; and a second memory (e.g., program memory) connected to the
`
`35414954.1
`
`
`
`-10-
`
`
`
`

`
`microprocessor circuit. Ex. 1003, FIG. 6.3; Ex. 1002 at 28-36. A side-by-side
`
`comparison of the token illustrated in FIG. 6.3 of Hawkes (left) and the electronic
`
`module illustrated in FIG. 1 of the ‘013 Patent (right) is shown below.
`
`
`
`As can be seen in the side-by-side comparison above, the token of Hawkes contains
`
`the same basic hardware elements (e.g. processor, coprocessor, clock, memory, I/O
`
`circuitry) as the electronic module disclosed in the ‘013 Patent. See Ex. 1002 at 35.
`
`Hawkes teaches that the token is powered by a battery and/or via power
`
`supplied by a terminal, and that the token is programmable. Ex. 1003, pages 86 and
`
`88; Ex. 1002 at 36. Additionally, Hawkes teaches that the RSA processor is
`
`programmed to perform RSA encryption calculations, and all remaining functions of
`
`the IC card are performed by programs executed by the control processor. Ex. 1003,
`
`pages 86-87. Hawkes teaches that it is advantageous to use both a control processor
`
`35414954.1
`
`
`
`-11-
`
`
`
`

`
`and an RSA processor because it allows the two processors to work in parallel,
`
`which reduces and/or hides the encryption calculation time, and enables the control
`
`processor to be programmed using a high-level programming language. Ex. 1003,
`
`pages 86-87; Ex. 1002 at 36.
`
`Hawkes further teaches that the token facilitates the movement of funds
`
`between the token user and retailer accounts during transactions (e.g., purchases).
`
`Ex. 1003, pages 83-89. To avoid “replays” of transactions, Hawkes teaches that a
`
`time and date field must be included in messages (e.g., transaction messages)
`
`exchanged between the token and the terminal. Ex. 1003, page 85, FIG. 6.2; Ex.
`
`1002 at 33 and 38. Additionally, Hawkes teaches that sequence numbers are applied
`
`to transaction messages to deter message reuse, and that details of transactions
`
`which the token participates in are stored in the data memory of the token. Ex.
`
`1003, pages 70, 86, 153; Ex. 1002 at 33 and 38.
`
`2. Lancaster
`
`Lancaster is a book comprised of a collection of columns reprinted from
`
`Electronics Now magazine, and was published in 1994. Ex. 1007, Introduction,
`
`page iii. In an article dated July, 1993, Lancaster describes a microcontroller that
`
`includes an electronically erasable programmable read only memory (EEPROM) for
`
`storing instructions written in the BASIC programming language, and a BASIC
`
`interpreter. Ex. 1007, page 66.1, FIG. 1. At the time the ‘013 Patent was filed, the
`
`35414954.1
`
`
`
`-12-
`
`
`
`

`
`BASIC programming language was commonly known to a person of ordinary skill
`
`in the art as a script programming language. Ex. 1002 at 44.
`
`3. Dreifus
`
`Dreifus discloses a transaction system that includes a portable electronic
`
`transaction device and a terminal. Ex. 1005, Abstract, 3:18-36. As illustrated in
`
`FIG. 5 of Dreifus, the transaction device is embodied as a card that includes an
`
`integrated circuit including: a CPU, a clock, a ROM, a RAM, direct memory access
`
`(DMA) circuitry, an interrupt control unit circuit, a communications buffer, a
`
`time/date clock, a battery, and a liquid crystal display (LCD). Ex. 1005, 8:16-49,
`
`FIG. 5. Dreifus indicates that the transaction device is used to store financial
`
`information and purchase information, and is used to facilitate retail transactions.
`
`Ex. 1005, 4: 21-28, 7:7-32. Dreifus indicates that information provided to or
`
`transmitted from the transaction device is encrypted, and that crypto-keys used for
`
`encryption purposes are dynamically altered “by changing the sequence of reading
`
`the information from ROM 56 (via changing RAM pointers) or reading information
`
`from different locations in ROM 46 (via changing RAM pointers) the CPU can vary
`
`the crypto-key used to encrypt messages.” Ex. 1005, 8:56-58, 13:29-59. Dreifus
`
`indicates that the transaction device is embedded in various objects and form factors,
`
`such as a card, gambling chip, or token. Ex. 1005, 18:4-57.
`
`4. Halpern
`
`35414954.1
`
`
`
`-13-
`
`
`
`

`
`Halpern describes a system for electronically transferring confidential data
`
`between a card device and a terminal. Ex. 1006, 1:7-9. FIG. 2 of Halpern discloses
`
`a card device includes a cipher/decipher circuit for performing encryption and
`
`decryption of information exchanged between the card device and the terminal, an
`
`arithmetic circuit (e.g., a microprocessor), a memory for storing data (e.g,. total
`
`number of transactions, purchase amount information, date information, quantities
`
`of items purchased, etc.), an input/output interface (e.g., inputs and outputs l1 and l2)
`
`a clock phase distributor circuit and program counter, and a pulse shaper and
`
`rectifier circuit for supplying power. Ex. 1006, 2:7-11, 3:30-42, 3:59-67, 6:47-53,
`
`FIGs. 2, 5, 7, and 8. Halpern teaches that the card device is configured to store value
`
`to facilitate consumer purchases, and indicates that the card record quantities of
`
`items purchased. Ex. 1006, 10:8-14 and 54-68, claim 5.
`
`5. Ishiguro
`
`Ishiguro discloses a method and apparatus for settlement of accounts by
`
`integrated circuit (IC) cards that are used as prepaid cards. Ex. 1004, 1:3-5. As
`
`shown in FIG. 3, reproduced below, the IC card includes a processor (e.g., a CPU), a
`
`read only memory (ROM), a random access memory (RAM), an electronically
`
`erasable programmable ROM (EEPROM), an input/output interface, and contacts.
`
`35414954.1
`
`
`
`-14-
`
`
`
`

`
`
`
`Ishiguro teaches that the IC card interacts with a terminal to facilitate
`
`purchases, which includes interactions to increase security using a challenge
`
`procedure whereby the IC card receives a challenge number from the terminal and
`
`returns the challenge number to the terminal in a signed message. Ex. 1004, 12:17-
`
`44, FIG. 6. Ishiguro further teaches that memory of the IC card stores card usage
`
`information, a value amount, and digital signature information, where the value is
`
`decremented based on transaction amounts associated purchases made using the
`
`card. Ex. 1004, 1:6-13, 10:1-11:58.
`
`E.
`
`Summary regarding the prior art references
`
`In view of the above, the prior art relied on herein and the supporting expert
`
`testimony makes clear that each feature outlined in the challenged claims was well
`
`known in the art at least one year before the earliest claimed priority date of the ‘013
`
`Patent. Additionally, as detailed below, the proposed modifications of the art to
`
`meet the claims would have been obvious to one of ordinary skill in the art at the
`
`time of the alleged invention claimed in the ‘013 Patent. Therefore, Petitioner
`-15-
`
`35414954.1
`
`
`
`

`
`submits that there is a reasonable likelihood of success that Petitioner will prevail in
`
`challenging claims 1-6, 8-12, and 15 in an Inter Partes Review. It is noted that the
`
`Patent Trial and Appeal Board has instituted covered business method review of
`
`claims 1-6, 8-13, and 15 the ‘013 Patent in CBM 2015-00101 (the “CBM
`
`proceeding”), finding that the Petitioner in the CBM proceeding is more likely than
`
`not to establish that claims 1-6, 8-12, and 15 of the ‘013 Patent are unpatentable as
`
`obvious over combinations utilizing Hawkes as a primary reference. Ex. 1010,
`
`pages 19-27.
`
`F.
`
`The Challenged Claims Are Invalid Under 35 U.S.C. § 102 and
`103(a)
`
`Pursuant to Rule 42.104(b)(4)-(5), the following demonstrates where each
`
`element of the challenged claims is found in the prior art for each of the grounds
`
`listed above.
`
`6.
`
`Grounds 1 and 2: Claims 1-4, 6, 9-12, and 15 are anticipated
`under 35 U.S.C. § 102(b) by Hawkes, and are alternatively
`obvious under 35 U.S.C. § 103(a) over Hawkes
`
`a. Claim 1
`The preamble of claim 1 of the ‘013 Patent recites “A microcontroller based
`
`secure transaction integrated circuit.” The ‘013 Patent describes a microcontroller
`
`as a microprocessor that interprets and acts on data. Ex. 1001, FIG. 1, 3:22-32.
`
`Hawkes describes tokens and cards that include integrated circuits (e.g., processors,
`
`memories, etc.) to exchange information with an external device, where some of the
`-16-
`
`
`
`35414954.1
`
`
`
`

`
`information (e.g., data transferred value, etc.) is encrypted to provide data security.
`
`Ex. 1003, Preface, page x, page 7. One of ordinary skill in the art would readily
`
`recognize that encrypting data is a well-known technique for securing information
`
`exchanged in a transaction. Ex. 1002 at 27. Accordingly, Hawkes discloses “An
`
`apparatus for receiving and transmitting encrypted data,” as in claim 1 of the ‘013
`
`Patent. See Ex. 1002 at 27.
`
`Claim 1 further recites “a microcontroller core.” As explained above, the
`
`‘013 Patent describes a microcontroller as a microprocessor that interprets and acts
`
`on data. Ex. 1001, FIG. 1, 3:22-32. FIG. 6.3 of Hawkes, reproduced below, shows
`
`that the token device includes a control processor. Ex. 1003, pages 86 and 87.
`
`Hawkes teaches that the control processor executes applications that provide
`
`functionality to a user of the token. Ex. 1003, pages 84-87. Hawkes discloses that
`
`
`
`the control processor may be implemented as the Intel 8085 microprocessor, for
`-17-
`
`
`
`35414954.1
`
`
`
`

`
`example. Ex. 1003, pages 86 and 87; Ex. 1002 at 29 and 43. One of ordinary skill
`
`in the art would readily recognize that the Intel 8085 microprocessor is an example
`
`of a microcontroller core. Ex. 1002 at 29. Therefore, Hawkes discloses “a
`
`microcontroller core,” as in claim 1 of the ‘013 Patent. See Ex. 1002 at 29.
`
`Claim 1 of the ‘013 Patent further recites “a math coprocessor connected to
`
`said microcontroller core, said math coprocessor being for handling complex
`
`mathematics of encryption and decryption.” The ‘013 Patent indicates that the
`
`math coprocessor performs mathematical operations to provide RSA encryption and
`
`decryption. Ex. 1001, 2:54-57. Hawkes teaches that the RSA processor is
`
`programmed to perform RSA encryption and decryption calculations. Ex. 1003,
`
`page 87. Hawkes discloses an 8-bit bidirectional bus buffer to facilitate
`
`communication between the control processor and the RSA processor. Ex. 1003,
`
`page 87. Hawkes teaches that the RSA processor may be implemented as a
`
`TMS32010 microprocessor. Ex. 1003, page 86. One of ordinary skill in the art
`
`would readily recognize that the TMS32010 microprocessor is an example of a math
`
`coprocessor. Ex. 1002 at 30. In view of Hawkes teaching that: (1) the token device
`
`includes an RSA processor programmed to perform RSA encryption and decryption
`
`calculations; and (2) an 8-bit bidirectional bus buffer to facilitate communication
`
`between the control processor and the RSA processor, one of ordinary skill in the art
`
`would readily recognize that the RSA processor of Hawkes teaches a math
`
`35414954.1
`
`
`
`-18-
`
`
`
`

`
`coprocessor connected to a microcontroller core, as described by the ‘013 Patent.
`
`See Ex. 1002 at 30. Thus, Hawkes discloses “a math coprocessor connected to said
`
`microcontroller core, said math coprocessor being for handling complex
`
`mathematics of encryption and decryption,” as in claim 1 of the ‘013 Patent. See
`
`Ex. 1002 at 30.
`
`Claim 1 of the ‘013 Patent further recites “memory circuitry which can be
`
`programmed by a service provider to enable said microcontroller based secure
`
`transaction integrated circuit to perform predetermined functions on behalf of the
`
`service provider and for the benefit of an end user.” As explained above, FIG. 6.3
`
`of Hawkes shows a token or smart card device that includes memory circuitry (e.g.,
`
`a program memory and a data memory). Hawkes teaches that the token, including
`
`memory circuitry, is key to providing services to the person carrying the token, and
`
`that the service provider can program the memory circuitry of the card to provide the
`
`services (e.g., access control, point of sale transactions, and signature of
`
`alphanumeric messages) to the person carrying the token. Ex. 1003, pages 4, 87.
`
`Accordingly, Hawkes discloses “memory circuitry which can be programmed by a
`
`service provider to enable said microcontroller based secure transaction integrated
`
`circuit to perform predetermined functions on behalf of the service provider and for
`
`the benefit of an end user,” as in claim 1 of the ‘013 Patent. See Ex. 1002 at 16, 28,
`
`and 31.
`
`35414954.1
`
`
`
`-19-
`
`
`
`

`
`Claim 1 of the ‘013 Patent further recites “said memory circuitry being
`
`connected to said microcontroller core.” FIG. 6.3 of Hawkes, reprodu