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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`______________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________
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`UNITED SERVICES AUTOMOBILE ASSOCIATION
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`Petitioner
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`v.
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`MAXIM INTEGRATED PRODUCTS, INC.
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`Patent Owner
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`
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`U.S. Patent 6,105,013
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`TITLE: METHOD, APPARATUS, SYSTEM AND FIRMWARE FOR
`SECURE TRANSACTIONS
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`Issue Date August 15, 2000
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`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
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`
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`
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`Petitioner’s Exhibit List
`
`Description
`U.S. Patent No. 6,105,013 (filed Mar. 10, 1998) (issued Aug. 15,
`2000) (“‘013 Patent”)
`Declaration of Dr. James L. Olivier (“Olivier Declaration”)
`PETER L. HAWKES ET AL., INTEGRATED CIRCUIT CARDS, TAGS AND
`TOKENS, NEW TECHNOLOGY AND APPLICATIONS, (Peter L. Hawkes
`et al. eds., BSP Professional Books 1990) (“Hawkes”)
`European Pat. Pub. 0588339 A2 (“Ishiguro”)
`U.S. Patent No. 4,575,621 (filed Mar. 7, 1984) (issued Mar. 11,
`1986) (“Dreifus”)
`U.S. Patent No. 4,906,828 (filed May 31, 1988) (issued Mar. 6,
`1990) (“Halpern”)
`Don Lancaster, BASIC Stamp Microcontroller, Hardware Hacker,
`Selected Reprints, Vol. IV, (July 1993) (“Lancaster”)
`Prosecution history for ‘013 Patent
`Square, Inc. v. J. Carl Cooper, IPR 2014-00157, Papers 12 and 17
`Compass Bank, American Express Company, American Express
`Travel Related Services Company, Inc., Discover Financial Services,
`Discover Bank, Discover Products Inc., and State Farm Mutual
`Automobile Insurance Company v. Maxim Integrated Products, Inc.,
`CBM 2015-00101, Paper 17
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`Exhibit No.
`1001
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`1002
`1003
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`1004
`1005
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`1006
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`1007
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`1008
`1009
`1010
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`TABLE OF CONTENTS
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`Page
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`INTRODUCTION .......................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(A)(1) ....................... 1
`A.
`Real Party-in-Interest Under 37 C.F.R. § 42.8(b)(1) ........................... 1
`B.
`Related Matters Under 37 C.F.R. § 42.8(b)(2) .................................... 1
`C.
`Lead and Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3) ................. 2
`D.
`Service Information Under 37 C.F.R. § 42.8(b)(4) .............................. 2
`E.
`Payment of Fees ................................................................................... 2
`III. REQUIREMENTS FOR INTER PARTES REVIEW UNDER 37
`C.F.R. §42.104 ................................................................................................ 3
`A. Grounds for Standing Under 37 C.F.R. §42.104(a) ............................. 3
`B.
`Identification of Challenge Under 37 C.F.R. §42.104(B) .................... 3
`1.
`Claims for Which Review is Requested (37 C.F.R. §
`42.104(b)(1)) .............................................................................. 3
`Statutory Grounds of Challenge (37 C.F.R. §
`42.104(b)(2)) .............................................................................. 3
`IV. REASONS FOR THE RELIEF REQUESTED UNDER 37 C.F.R. §§
`42.22(A)(2) AND 42.104(B)(4) ..................................................................... 5
`A.
`Background .......................................................................................... 5
`1.
`The ‘013 Patent .......................................................................... 5
`Relevant Prosecution History ............................................................... 7
`Claim Construction (37 C.F.R. § 42.104(b)(3)) ................................... 8
`Summary of the Prior Art ..................................................................... 9
`1.
`Hawkes ....................................................................................... 9
`2.
`Lancaster .................................................................................. 12
`3.
`Dreifus ...................................................................................... 13
`4.
`Halpern ..................................................................................... 13
`5.
`Ishiguro .................................................................................... 14
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`B.
`C.
`D.
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`2.
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`Summary regarding the prior art references ....................................... 15
`The Challenged Claims Are Invalid Under 35 U.S.C. § 102 and
`103(a) .................................................................................................. 16
`6.
`Grounds 1 and 2: Claims 1-4, 6, 9 10, 11, 12, 14, and 15
`are anticipated under 35 U.S.C. § 102(b) by Hawkes, and
`are alternatively obvious under 35 U.S.C. § 103(a) over
`Hawkes ..................................................................................... 16
`a.
`Claim 1 ........................................................................... 16
`b.
`Claims 2 and 14 ............................................................. 22
`c.
`Claims 3 and 12 ............................................................. 23
`d.
`Claims 4 and 10 ............................................................. 24
`e.
`Claims 6 and 15 ............................................................. 24
`f.
`Claim 9 ........................................................................... 25
`g.
`Claim 11 ......................................................................... 28
`Ground 3: Claim 5 is obvious under 35 U.S.C. § 103(a)
`over Hawkes in view of Lancaster ........................................... 29
`Ground 4: Claim 8 is obvious under 35 U.S.C. § 103(a)
`over Hawkes in view of Dreifus .............................................. 31
`Ground 5: Claims 1-4, 6, 9, 10, 12, 14, and 15 are
`obvious under 35 U.S.C. § 103(a) over Halpern in view
`of Ishiguro ................................................................................ 32
`a.
`Claim 1 ........................................................................... 33
`b.
`Claim 2 ........................................................................... 42
`c.
`Claims 3 and 12 ............................................................. 42
`d.
`Claims 4 and 10 ............................................................. 43
`e.
`Claims 6 and 15 ............................................................. 44
`f.
`Claim 9 ........................................................................... 47
`10. Ground 6: Claim 5 is obvious under 35 U.S.C. § 103(a)
`over Halpern, in view of Ishiguro, and in further view of
`Lancaster .................................................................................. 44
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`7.
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`8.
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`E.
`F.
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`9.
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`11. Ground 7: Claims 8 and 11 are obvious under 35 U.S.C.
`§ 103(a) over Halpern, in view of Ishiguro, and in further
`view of Dreifus ......................................................................... 46
`a.
`Claim 8 ........................................................................... 46
`b.
`Claim 11 ......................................................................... 54
`CONCLUSION ............................................................................................. 57
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`V.
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`I.
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`INTRODUCTION
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`Pursuant to 35 U.S.C. § 312 and 37 C.F.R. § 42.100 et seq., United Services
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`Automobile Association (“Petitioner”) requests inter partes review of claims 1-6, 8-
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`12, and 15 (the “Challenged Claims”) of U.S. Patent No. 6,105,013 (“the ‘013
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`Patent,” Ex. 1001), which issued on August 15, 2000.
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`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(a)(1)
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`A. Real Party-in-Interest Under 37 C.F.R. § 42.8(b)(1)
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`United Services Automobile Association, USAA Federal Savings Bank, and
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`USAA Capital Corporation are the real parties-in-interest.
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`B. Related Matters Under 37 C.F.R. § 42.8(b)(2)
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`The ’013 Patent is involved in the following proceedings that may affect or be
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`affected by a decision in this proceeding:
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` CBM 2015-00101; and
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` Maxim Integrated Products, Inc., v. USAA Federal Savings Bank, W.D.
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`Texas, C.A. No. 5:14-CV-1031-XR; Maxim Integrated Products, Inc.,
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`v. The American Express Company and American Express Travel
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`Related Services Company, Inc., W.D. Texas, C.A. No. 5:14-CV-
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`01027; Maxim Integrated Products, Inc., v. Compass Bank, d/b/a
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`BBVA Compass, W.D. Texas, C.A. No. 5:14-CV-01028; Maxim
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`Integrated Products, Inc., v. Discover Bank, W.D. Texas, C.A. No.
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`5:14-CV-01029; Maxim Integrated Products, Inc., v. State Farm
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`Mutual Automobile Ins. Co., W.D. Texas, C.A. No. 5:14-CV-01030-
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`XR; Maxim Integrated Products, Inc., v. M&T Bank Corp., C.A. No.
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`1:15-CV-02167; Maxim Integrated Products, Inc., v. HSBC Bank USA,
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`Nat’l Ass’n, C.A. No. 1:15-CV-02168; Maxim Integrated Products,
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`Inc., v. Santander Bank, NA, C.A. No. 1:15-CV-02169; Branch Bank
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`and Trust Company v. Maxim Integrated Products, Inc., C.A. No. 2:12-
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`CV-00945, No. 2:12-mc-00244 (W.D. Pa.).
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`C. Lead and Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3)
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`Petitioner designates Nathan Rees (Reg. No. 63,820) as Lead Counsel, and
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`Allan Braxdale (Reg. No. 64,276), and Ross Viguet (Reg. No. 42,203), as Back-Up
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`Counsel.
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`D.
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`Service Information Under 37 C.F.R. § 42.8(b)(4)
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`Email: USAA013IPR@nortonrosefulbright.com
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`Post: Nathan J. Rees, Norton Rose Fulbright US LLP, 2200 Ross Avenue,
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`Suite 3600, Dallas, Texas 75201
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`Phone: 214.855.7164 Fax: 214.855.8200
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`Petitioner consents to electronic service.
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`E.
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`Payment of Fees
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`The fees for this petition have been paid by credit card. The Board is
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`authorized to deduct any underpayment of fees associated with this petition and any
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`related fees from Norton Rose Fulbright US LLP Deposit Account No. 06-2380,
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`under Order No. 11504607.
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`III. REQUIREMENTS FOR INTER PARTES REVIEW UNDER 37 C.F.R.
`§42.104
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`A. Grounds for Standing Under 37 C.F.R. §42.104(a)
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`This petition has been filed within one year of the earliest date Petitioner was
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`served with a complaint in case number 5:14-cv-1031-XR. Petitioner certifies that
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`the ‘013 Patent is available for inter partes review, and that Petitioner is not barred
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`or estopped from requesting this inter partes review.
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`B.
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`Identification of Challenge Under 37 C.F.R. §42.104(b)
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`1. Claims for Which Review is Requested (37 C.F.R. §
`42.104(b)(1))
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`Petitioner requests review and the cancellation as invalid of claims 1-6, 8-12,
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`and 15 of the ‘013 Patent.
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`2. Statutory Grounds of Challenge (37 C.F.R. § 42.104(b)(2))
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`Petitioner requests inter partes review of Challenged Claims 1-6, 8-12, and 15
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`of the ‘013 Patent on the grounds set forth in the table shown below, and requests
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`that each of the Challenged Claims be found unpatentable. An explanation of how
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`these claims are unpatentable under the statutory grounds identified below is
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`provided in the form of detailed description that follows, indicating where each of
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`the claim elements can be found in the cited prior art, and the relevance of that prior
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`art. Additional explanation and support for each ground of rejection is set forth in
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`Ex. 1002, referenced throughout this Petition.
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`Hawkes as Primary Reference:
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`Ground
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`‘013 Patent Claims
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`Basis for Rejection
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`Ground 1
`Ground 2
`Ground 3
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`Ground 4
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`1-4, 6, 9-12, and 15
`1-4, 6, 9-12, and 15
`5
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`8
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`35 U.S.C. § 102(b) based on Hawkes
`35 U.S.C. § 103(a) based on Hawkes
`35 U.S.C. § 103(a) based on Hawkes in
`view of Lancaster
`35 U.S.C. § 103(a) based on Hawkes in
`view of Dreifus
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`Halpern as Primary Reference:
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`Ground
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`‘013 Patent Claims
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`Basis for Rejection
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`Ground 5
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`1-4 and 6
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`Ground 6
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`5
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`Ground 7
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`8-12 and 15
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`35 U.S.C. § 103(a) based on Halpern in
`view of Ishiguro
`35 U.S.C. § 103(a) based on Halpern, in
`view of Ishiguro, and in further view of
`Lancaster
`35 U.S.C. § 103(a) based on Halpern, in
`view of Ishiguro, and in further view of
`Dreifus
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`The ‘013 Patent issued Aug. 15, 2000 from Application No. 09/041,190
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`(“‘190 Appln.”), which was filed Mar. 10, 1998. The ‘190 Appln. is a continuation
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`of the 08/594,983 Application, filed Jan. 31, 1996, which claims priority to
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`Provisional Application No. 60/004,510, filed Sep. 29, 1995. Accordingly, the
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`earliest possible date to which the ‘013 Patent could claim priority (hereinafter the
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`“earliest effective filing date”) is September 29, 1995.
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`Further, Petitioner does not concede that the ‘013 Patent is entitled to this
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`priority date, but has elected not to argue the issue in the Petition because all prior
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`art references identified in the Grounds presented below pre-date the earliest
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`possible priority date for the ‘013 Patent. However, Petitioner explicitly reserves the
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`right to present such an argument in this proceeding or other proceedings involving
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`the ‘013 Patent.
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`Hawkes was published in 1990 by BSP Professional Books. Ex. 1003.
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`Lancaster was published in 1993 by Electronics Now magazine. Ex. 1007. The
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`Ishiguro patent application was published on March 23, 1994. Ex. 1004. The
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`Dreifus and Halpern patents were each issued/published by the United States Patent
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`and Trademark Office more than one year before the earliest priority date of the
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`‘013 Patent. Ex. 1005 and Ex. 1006. Therefore, each of the cited references of
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`Grounds 1-7 are available as prior art under 35 U.S.C. §102(b).
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`IV. REASONS FOR THE RELIEF REQUESTED UNDER 37 C.F.R. §§
`42.22(A)(2) AND 42.104(B)(4)
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`A. Background
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`1. The ‘013 Patent
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`The ‘013 Patent is directed to an electronic module for exchanging encrypted
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`information with a service provider’s equipment in order to facilitate secure
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`transactions. Ex. 1001, Abstract. As illustrated in FIG. 1 of the ‘013 Patent,
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`reproduced below, the electronic module includes a microprocessor, a clock, a math
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`coprocessor, memory circuitry, an input/output circuit, and an energy circuit. Ex.
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`1001, 2:34-67, 3:1-9.
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`The math coprocessor performs known mathematics operations for RSA
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`encryption and decryption (e.g., public/private key encryption/decryption); the
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`memory circuitry includes volatile and non-volatile memories; the input/output
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`circuit enables bidirectional communication between the electronic module and an
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`external device; the energy circuit includes a battery to maintain the memory
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`circuitry and aid in powering other circuitry of the electronic module. Ex. 1001,
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`2:54-57, 2:58-63, 2:66-3:4, 3:5-9. The ‘013 Patent discloses that the electronic
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`module is programmed by a service provider to operate as a digital cash dispenser or
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`a cash reservoir that allows the end user to participate in transactions whereby the
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`electronic module is used to make payments for goods and services. Ex. 1001, 7:64-
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`8:18. The electronic module is incorporated into an articulatable item, such as a
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`ring, a watch, a wallet, a purse, a necklace, jewelry, an ID badge, a pen, a clipboard,
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`a token, etc. Ex. 1001, 29:59-64.
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`B. Relevant Prosecution History
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`The ‘013 Patent was filed on March 10, 1998 and assigned U.S. Patent
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`Application No. 09/041,190 (hereinafter “the ‘190 Application”). Claim 1 of the
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`‘013 Patent corresponds to claim 32 of the ‘190 Application, and claim 9 of the ‘013
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`Patent corresponds to claim 41 of the ‘190 Application, both of which were
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`introduced in response filed on November 6, 1998. Ex. 1008 November 6, 1998
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`Response at 1-5. In response to the Office Action mailed on July 23, 1999, claim 32
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`of the ‘190 Application was amended to recite “a real time clock, connected to said
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`microcontroller core, for providing a time measurement for time stamping a
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`predetermined function,” and claim 41 of the ‘190 Application was amended to
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`recite “a clock circuit for measuring time and providing time stamp information
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`responsive to functions being performed by said microcontroller core.” Ex. 1008
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`October 25, 1999 Response at 2 and 3. Based on this amendment, a Notice of
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`Allowance was mailed on January 12, 2000, and the ‘190 Application Issued as the
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`‘013 Patent on August 15, 2000. Ex. 1008 January 12, 2000 Notice of Allowance.
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`Patent Owner disclaimed claims 7, 14, and 16 of the ‘013 Patent. CBM 2015-
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`00101, Ex. 1010.
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`C. Claim Construction (37 C.F.R. § 42.104(b)(3))
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`In an inter partes review, a claim in an unexpired patent is given the “broadest
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`reasonable construction in light of the specification of the patent in which it
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`appears.” 37 C.F.R. § 42.100(b). Alternatively, a claim term in an expired patent is
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`construed according to its ordinary and customary meaning, as understood by one of
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`ordinary skill in the art. See Ex. 1009 Paper 12 at 3 and 4, and Paper 17 at 2 and 3.
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`Petitioner notes that the 20 year patent term for the ‘013 Patent will expire prior to a
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`final written decision in this proceeding. Below, Petitioner provides constructions
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`for certain claim terms in accordance 37 C.F.R. § 42.104(b)(3). Petitioner
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`respectfully submits that the constructions provided below would be the same under
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`both the broadest reasonable interpretation standard, which is used to construe claim
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`terms in an unexpired patent, and the ordinary and customary meaning standard,
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`which is used to construe claim terms in an expired patent. The following
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`summarizes how certain claim phrases of the ‘013 Patent should be construed for
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`purposes of this Inter Partes Review:
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`1.
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`“coprocessor”: The claim term “coprocessor” should be construed as
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`a processor that works with another processor. Ex. 1002 at 23.
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`2.
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`“modular exponentiation accelerator circuit”: The ‘013 Patent
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`describes a modular exponentiation accelerator circuit as a math coprocessor. Ex.
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`1001, 2:54-57, 3:24-26. Thus, the claim term “modular exponentiation accelerator
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`circuit” should be construed as a processor that works with another processor and
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`performs mathematics of modular exponentiation. Ex. 1002 at 24.
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`3. “nonvolatile RAM”: The ‘013 Patent discloses that the electronic module
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`includes memory circuitry 20 that is connected to an energy circuit 34, and teaches
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`that the energy circuit 34 may include a battery and is necessary to maintain the
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`memory circuitry 20. Ex. 1001, 3:5-9. Therefore, the claim term “nonvolatile
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`RAM” should be construed to at least include RAM that is backed up by a battery or
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`another power source. Ex. 1002 at 25.
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`4. “real time clock” and “clock circuit”: The ‘013 Patent describes a
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`continuously running real time clock and clock circuitry that provide information to
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`track time for generating timestamp information. Ex. 1001, FIG. 12, 3:21-63, 4:44.
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`Thus, the claim terms “real time clock” and “clock circuit” should be construed to
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`mean continuously running clock circuitry that tracks time. Ex. 1002 at 26.
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`D.
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`Summary of the Prior Art
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`1. Hawkes
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`Hawkes describes various design aspects of integrated circuit (IC) cards, tags,
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`and tokens, and describes various applications for which such devices are used. Ex.
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`1003, Preface, pages ix-xi, pages 1-11, Table 1.4; Ex. 1002 at 27. For example,
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`Hawkes teaches that the tokens or smart cards are operated as an electronic wallet
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`capable of storing and dispensing data transferred value (e.g., electronic money) in
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`connection with the purchase of goods or services. Ex. 1003, Preface, page x, pages
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`7, 36, 37, 65, 69-70; Ex. 1002 at 27.
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`An exemplary configuration of a token is shown in FIG. 6.3, reproduced
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`below.
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`The token of FIG. 6.3 includes input/output interface (e.g., serial I/O); a
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`microprocessor circuit (e.g., control processor) connected to the input/output
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`interface; a coprocessor circuit (e.g., RSA processor) connected
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`to
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`the
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`microprocessor circuit; a timing circuit (e.g., clock) connected to the microprocessor
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`circuit; a first memory (e.g., data memory shown) connected to the microprocessor
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`circuit; and a second memory (e.g., program memory) connected to the
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`microprocessor circuit. Ex. 1003, FIG. 6.3; Ex. 1002 at 28-36. A side-by-side
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`comparison of the token illustrated in FIG. 6.3 of Hawkes (left) and the electronic
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`module illustrated in FIG. 1 of the ‘013 Patent (right) is shown below.
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`As can be seen in the side-by-side comparison above, the token of Hawkes contains
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`the same basic hardware elements (e.g. processor, coprocessor, clock, memory, I/O
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`circuitry) as the electronic module disclosed in the ‘013 Patent. See Ex. 1002 at 35.
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`Hawkes teaches that the token is powered by a battery and/or via power
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`supplied by a terminal, and that the token is programmable. Ex. 1003, pages 86 and
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`88; Ex. 1002 at 36. Additionally, Hawkes teaches that the RSA processor is
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`programmed to perform RSA encryption calculations, and all remaining functions of
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`the IC card are performed by programs executed by the control processor. Ex. 1003,
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`pages 86-87. Hawkes teaches that it is advantageous to use both a control processor
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`and an RSA processor because it allows the two processors to work in parallel,
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`which reduces and/or hides the encryption calculation time, and enables the control
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`processor to be programmed using a high-level programming language. Ex. 1003,
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`pages 86-87; Ex. 1002 at 36.
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`Hawkes further teaches that the token facilitates the movement of funds
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`between the token user and retailer accounts during transactions (e.g., purchases).
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`Ex. 1003, pages 83-89. To avoid “replays” of transactions, Hawkes teaches that a
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`time and date field must be included in messages (e.g., transaction messages)
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`exchanged between the token and the terminal. Ex. 1003, page 85, FIG. 6.2; Ex.
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`1002 at 33 and 38. Additionally, Hawkes teaches that sequence numbers are applied
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`to transaction messages to deter message reuse, and that details of transactions
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`which the token participates in are stored in the data memory of the token. Ex.
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`1003, pages 70, 86, 153; Ex. 1002 at 33 and 38.
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`2. Lancaster
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`Lancaster is a book comprised of a collection of columns reprinted from
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`Electronics Now magazine, and was published in 1994. Ex. 1007, Introduction,
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`page iii. In an article dated July, 1993, Lancaster describes a microcontroller that
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`includes an electronically erasable programmable read only memory (EEPROM) for
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`storing instructions written in the BASIC programming language, and a BASIC
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`interpreter. Ex. 1007, page 66.1, FIG. 1. At the time the ‘013 Patent was filed, the
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`BASIC programming language was commonly known to a person of ordinary skill
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`in the art as a script programming language. Ex. 1002 at 44.
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`3. Dreifus
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`Dreifus discloses a transaction system that includes a portable electronic
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`transaction device and a terminal. Ex. 1005, Abstract, 3:18-36. As illustrated in
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`FIG. 5 of Dreifus, the transaction device is embodied as a card that includes an
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`integrated circuit including: a CPU, a clock, a ROM, a RAM, direct memory access
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`(DMA) circuitry, an interrupt control unit circuit, a communications buffer, a
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`time/date clock, a battery, and a liquid crystal display (LCD). Ex. 1005, 8:16-49,
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`FIG. 5. Dreifus indicates that the transaction device is used to store financial
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`information and purchase information, and is used to facilitate retail transactions.
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`Ex. 1005, 4: 21-28, 7:7-32. Dreifus indicates that information provided to or
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`transmitted from the transaction device is encrypted, and that crypto-keys used for
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`encryption purposes are dynamically altered “by changing the sequence of reading
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`the information from ROM 56 (via changing RAM pointers) or reading information
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`from different locations in ROM 46 (via changing RAM pointers) the CPU can vary
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`the crypto-key used to encrypt messages.” Ex. 1005, 8:56-58, 13:29-59. Dreifus
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`indicates that the transaction device is embedded in various objects and form factors,
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`such as a card, gambling chip, or token. Ex. 1005, 18:4-57.
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`4. Halpern
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`Halpern describes a system for electronically transferring confidential data
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`between a card device and a terminal. Ex. 1006, 1:7-9. FIG. 2 of Halpern discloses
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`a card device includes a cipher/decipher circuit for performing encryption and
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`decryption of information exchanged between the card device and the terminal, an
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`arithmetic circuit (e.g., a microprocessor), a memory for storing data (e.g,. total
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`number of transactions, purchase amount information, date information, quantities
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`of items purchased, etc.), an input/output interface (e.g., inputs and outputs l1 and l2)
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`a clock phase distributor circuit and program counter, and a pulse shaper and
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`rectifier circuit for supplying power. Ex. 1006, 2:7-11, 3:30-42, 3:59-67, 6:47-53,
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`FIGs. 2, 5, 7, and 8. Halpern teaches that the card device is configured to store value
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`to facilitate consumer purchases, and indicates that the card record quantities of
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`items purchased. Ex. 1006, 10:8-14 and 54-68, claim 5.
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`5. Ishiguro
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`Ishiguro discloses a method and apparatus for settlement of accounts by
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`integrated circuit (IC) cards that are used as prepaid cards. Ex. 1004, 1:3-5. As
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`shown in FIG. 3, reproduced below, the IC card includes a processor (e.g., a CPU), a
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`read only memory (ROM), a random access memory (RAM), an electronically
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`erasable programmable ROM (EEPROM), an input/output interface, and contacts.
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`Ishiguro teaches that the IC card interacts with a terminal to facilitate
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`purchases, which includes interactions to increase security using a challenge
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`procedure whereby the IC card receives a challenge number from the terminal and
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`returns the challenge number to the terminal in a signed message. Ex. 1004, 12:17-
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`44, FIG. 6. Ishiguro further teaches that memory of the IC card stores card usage
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`information, a value amount, and digital signature information, where the value is
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`decremented based on transaction amounts associated purchases made using the
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`card. Ex. 1004, 1:6-13, 10:1-11:58.
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`E.
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`Summary regarding the prior art references
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`In view of the above, the prior art relied on herein and the supporting expert
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`testimony makes clear that each feature outlined in the challenged claims was well
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`known in the art at least one year before the earliest claimed priority date of the ‘013
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`Patent. Additionally, as detailed below, the proposed modifications of the art to
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`meet the claims would have been obvious to one of ordinary skill in the art at the
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`time of the alleged invention claimed in the ‘013 Patent. Therefore, Petitioner
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`submits that there is a reasonable likelihood of success that Petitioner will prevail in
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`challenging claims 1-6, 8-12, and 15 in an Inter Partes Review. It is noted that the
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`Patent Trial and Appeal Board has instituted covered business method review of
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`claims 1-6, 8-13, and 15 the ‘013 Patent in CBM 2015-00101 (the “CBM
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`proceeding”), finding that the Petitioner in the CBM proceeding is more likely than
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`not to establish that claims 1-6, 8-12, and 15 of the ‘013 Patent are unpatentable as
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`obvious over combinations utilizing Hawkes as a primary reference. Ex. 1010,
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`pages 19-27.
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`F.
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`The Challenged Claims Are Invalid Under 35 U.S.C. § 102 and
`103(a)
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`Pursuant to Rule 42.104(b)(4)-(5), the following demonstrates where each
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`element of the challenged claims is found in the prior art for each of the grounds
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`listed above.
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`6.
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`Grounds 1 and 2: Claims 1-4, 6, 9-12, and 15 are anticipated
`under 35 U.S.C. § 102(b) by Hawkes, and are alternatively
`obvious under 35 U.S.C. § 103(a) over Hawkes
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`a. Claim 1
`The preamble of claim 1 of the ‘013 Patent recites “A microcontroller based
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`secure transaction integrated circuit.” The ‘013 Patent describes a microcontroller
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`as a microprocessor that interprets and acts on data. Ex. 1001, FIG. 1, 3:22-32.
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`Hawkes describes tokens and cards that include integrated circuits (e.g., processors,
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`memories, etc.) to exchange information with an external device, where some of the
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`information (e.g., data transferred value, etc.) is encrypted to provide data security.
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`Ex. 1003, Preface, page x, page 7. One of ordinary skill in the art would readily
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`recognize that encrypting data is a well-known technique for securing information
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`exchanged in a transaction. Ex. 1002 at 27. Accordingly, Hawkes discloses “An
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`apparatus for receiving and transmitting encrypted data,” as in claim 1 of the ‘013
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`Patent. See Ex. 1002 at 27.
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`Claim 1 further recites “a microcontroller core.” As explained above, the
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`‘013 Patent describes a microcontroller as a microprocessor that interprets and acts
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`on data. Ex. 1001, FIG. 1, 3:22-32. FIG. 6.3 of Hawkes, reproduced below, shows
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`that the token device includes a control processor. Ex. 1003, pages 86 and 87.
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`Hawkes teaches that the control processor executes applications that provide
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`functionality to a user of the token. Ex. 1003, pages 84-87. Hawkes discloses that
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`the control processor may be implemented as the Intel 8085 microprocessor, for
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`example. Ex. 1003, pages 86 and 87; Ex. 1002 at 29 and 43. One of ordinary skill
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`in the art would readily recognize that the Intel 8085 microprocessor is an example
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`of a microcontroller core. Ex. 1002 at 29. Therefore, Hawkes discloses “a
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`microcontroller core,” as in claim 1 of the ‘013 Patent. See Ex. 1002 at 29.
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`Claim 1 of the ‘013 Patent further recites “a math coprocessor connected to
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`said microcontroller core, said math coprocessor being for handling complex
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`mathematics of encryption and decryption.” The ‘013 Patent indicates that the
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`math coprocessor performs mathematical operations to provide RSA encryption and
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`decryption. Ex. 1001, 2:54-57. Hawkes teaches that the RSA processor is
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`programmed to perform RSA encryption and decryption calculations. Ex. 1003,
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`page 87. Hawkes discloses an 8-bit bidirectional bus buffer to facilitate
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`communication between the control processor and the RSA processor. Ex. 1003,
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`page 87. Hawkes teaches that the RSA processor may be implemented as a
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`TMS32010 microprocessor. Ex. 1003, page 86. One of ordinary skill in the art
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`would readily recognize that the TMS32010 microprocessor is an example of a math
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`coprocessor. Ex. 1002 at 30. In view of Hawkes teaching that: (1) the token device
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`includes an RSA processor programmed to perform RSA encryption and decryption
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`calculations; and (2) an 8-bit bidirectional bus buffer to facilitate communication
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`between the control processor and the RSA processor, one of ordinary skill in the art
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`would readily recognize that the RSA processor of Hawkes teaches a math
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`coprocessor connected to a microcontroller core, as described by the ‘013 Patent.
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`See Ex. 1002 at 30. Thus, Hawkes discloses “a math coprocessor connected to said
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`microcontroller core, said math coprocessor being for handling complex
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`mathematics of encryption and decryption,” as in claim 1 of the ‘013 Patent. See
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`Ex. 1002 at 30.
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`Claim 1 of the ‘013 Patent further recites “memory circuitry which can be
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`programmed by a service provider to enable said microcontroller based secure
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`transaction integrated circuit to perform predetermined functions on behalf of the
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`service provider and for the benefit of an end user.” As explained above, FIG. 6.3
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`of Hawkes shows a token or smart card device that includes memory circuitry (e.g.,
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`a program memory and a data memory). Hawkes teaches that the token, including
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`memory circuitry, is key to providing services to the person carrying the token, and
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`that the service provider can program the memory circuitry of the card to provide the
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`services (e.g., access control, point of sale transactions, and signature of
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`alphanumeric messages) to the person carrying the token. Ex. 1003, pages 4, 87.
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`Accordingly, Hawkes discloses “memory circuitry which can be programmed by a
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`service provider to enable said microcontroller based secure transaction integrated
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`circuit to perform predetermined functions on behalf of the service provider and for
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`the benefit of an end user,” as in claim 1 of the ‘013 Patent. See Ex. 1002 at 16, 28,
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`and 31.
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`Claim 1 of the ‘013 Patent further recites “said memory circuitry being
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`connected to said microcontroller core.” FIG. 6.3 of Hawkes, reprodu