UNITED STATES PATENT AND TRADEMARK OFFICE
`________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________________
`
`Linear Technology Corporation
`Petitioner
`v.
`In-Depth Test LLC
`Patent Owner
`
`Patent No. 6,792,373
`Issued: September 14, 2004
`Filed: May 24, 2002
`Inventors: Eric Paul Tabor
`
`Title: METHODS AND APPARATUS FOR SEMICONDUCTOR TESTING
`________________________
`
`Inter Partes Review No. Unassigned
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`__________________________________________________________________
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`DECLARATION OF ADIT SINGH
`REGARDING U.S. PATENT NO. 6,792,373
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`Singh Declaration
`U.S. Pat. 6,792,373
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`Declaration of Adit Singh
`Regarding U.S. Patent No. 6,792,373
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`I, Adit Singh, a resident of Auburn, Alabama, declare as follows:
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`I have been retained by McDermott Will & Emery to provide my
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`1.
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`2.
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`opinion concerning the validity of U.S. Patent No. 6,792,373 (“the ‘373 Patent”)
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`(Ex. 1001). McDermott Will & Emery is compensating me for my time at the rate
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`of $500 per hour.
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`3. My declaration contains the following sections beginning at the
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`designated pages:
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`I.
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`II.
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`III.
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`IV.
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`V.
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`VI.
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`Basis for My Opinion ................................................................................... 4
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`Introduction and Qualifications .................................................................... 5
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`My Understanding of the Governing Law ................................................... 8
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`A. Types of Claims -- Dependent and Independent Claims ...................... 8
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`B. Patentability and Validity of Claims ..................................................... 8
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`C. IPR Proceedings and Claim Interpretation .......................................... 10
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`D. Relevant Time Period .......................................................................... 11
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`E. Level of Ordinary Skill in the Art and Relevant Timeframe .............. 13
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`Background of the Relevant Discipline of the ‘373 Patent ........................ 13
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`The Technical Overview of The ‘373 Patent ............................................. 17
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`My Interpretation of Certain Claim Terms ................................................. 21
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`A. “component” ........................................................................................ 21
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`B. “recipe file” ......................................................................................... 22
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`VII.
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`References Used In My Analysis ............................................................... 23
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`A. Lane - U.S. Patent No. 4,967,381........................................................ 23
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`B. Western ................................................................................................ 30
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`VIII. Analysis of the ‘373 Patent Claims ............................................................ 36
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`A. General Description of the Claims and Organization of
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`Analysis ............................................................................................... 36
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`B. Invalidity of the Independent Claims .................................................. 37
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`i.
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`ii.
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`Independent Claim 1 ...................................................................................... 37
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`Independent Claim 8 ...................................................................................... 52
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`iii.
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`Independent Claim 15 .................................................................................... 57
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`C. Invalidity of the Dependent Claims .................................................... 61
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`iv. Dependent Claim 2, 9, and 16 ....................................................................... 61
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`v.
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`Dependent Claim 3, 10, and 17 ..................................................................... 64
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`vi. Dependent Claim 4, 11, and 18 ..................................................................... 66
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`vii. Dependent Claim 5, 12, and 20 ..................................................................... 68
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`viii. Dependent Claims 6 and 13 ........................................................................... 69
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`ix. Dependent Claim 7, 14, and 19 ..................................................................... 72
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`IX.
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`CONCLUSION .......................................................................................... 74
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`
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`I.
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`Basis for My Opinion
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`4.
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`In preparing this declaration, I have reviewed:
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`a. United States Patent No. 6,792,373 (the “ʼ373 Patent”) (Ex.
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`1001);
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`b. United States Patent No. 4,967,381 (“Lane”) (Ex. 1002);
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`c. Western Electric Co., STATISTICAL QUALITY CONTROL
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`HANDBOOK (Delmar Printing Co., 1956) (“Western”) (Ex.
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`1003);
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`d. Linear Tech. Corp. v. In-Depth Test LLC, Case IPR2015-
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`00421— Paper 12, Patent Owner’s Preliminary Response (the
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`“Preliminary Response”);
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`e. Reexamination 90/008,313—Request for Reexamination dated
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`October 30, 2006 (Ex. 1009);
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`f. Andrew Grochowski, Integrated Circuit Testing for Quality
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`Assurance in Manufacturing: History, Current Status, and
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`Future Trends, 44 IEEE TRANS. ON CIR. & SYS. 8, 610-33 (Aug.
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`1997) (“Grochowski”) (Ex. 1010);
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`g. Higaki, Remote Monitoring and Control of Semiconductor
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`Processing, Hewlett-Packard Journal, 30 (Jul. 1985) (“Higaki”)
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`(Ex. 1011);
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`h. Computer Focus – International, Hewlett Packard (Sept. 1985)
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`(Ex. 1012);
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`i. Semiconductor Process Analysis Software
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`Incorporates
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`Graphics Package, IEEE CG&A, 8 (Dec. 1985) (Ex. 1013).
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`5.
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`In forming my opinions expressed below, I have considered the above
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`listed documents and my experience and knowledge based on my work in this area
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`as described below. I also have provided a claim chart summarizing the support
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`for my opinion expressed in this declaration. In some instances, I have provided
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`additional citations of support in the claim chart that do not appear in my analysis
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`below, which I have found relevant in forming my opinion. I understand that my
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`claim chart has been submitted in this filing as Exhibit 1008.
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`II.
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`Introduction and Qualifications
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`6.
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`I received an undergraduate degree from the Indian Institute of
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`Technology (IIT) in Kanpur in 1976, and my M.S. and Ph.D. from Virginia Tech
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`in 1978 and 1982, respectively, all in Electrical Engineering.
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`7.
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`Since September 2002, I have been serving as a James B. Davis
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`Distinguished Professor of Electrical and Computer Engineering at Auburn
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`University, where I direct the VLSI Design and Test Laboratory. Before joining
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`Auburn in 1991, I was Associate, and earlier Assistant, Professor of Electrical and
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`Computer Engineering at the University of Massachusetts in Amherst. In the past,
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`I held visiting positions during sabbaticals at major universities, most recently in
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`2012 serving as “Guest Professor” at the University of Freiburg, Germany. My
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`research program directed to semiconductor testing has received extensive support
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`from U.S. National Science Foundation and private industry, and also from
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`international agencies such as the Max Plank Society of Germany, the Fulbright
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`Foundation, the Ministry of Science and Technology in India, and the National
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`Science Council of Taiwan.
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`8. My technical expertise spans all aspects of VLSI technology, in
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`particular, integrated circuit test and reliability. I am particularly recognized for
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`my pioneering contributions to statistical methods in test and adaptive testing. In
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`this regard, I have published over two hundred research papers, served as a
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`consultant to many of the largest semiconductor companies around the world, and
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`am the primary inventor listed in several international patents, some of which have
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`been licensed to industry. I have also held leadership roles as General Chair/Co-
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`Chair/Program Chair for dozens of international VLSI design and test conferences.
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`Most recently I was Program Chair of the 2014 International Conference on VLSI
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`Design, Co-Chair of the 2014 Workshop on Reliability Aware Design, and am the
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`Program Chair for the 2015 Asian Test Symposium. I also currently serve on the
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`editorial boards of IEEE Design and Test Magazine and the Journal of Testing and
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`Test Applications (JETTA), and on the Steering and Program Committees of many
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`of the major IEEE international test and design automation conferences.
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`9.
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`Over the years, I have become a popular lecturer. In addition to the
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`dozens of talks and seminars I have presented around the world directed to
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`research involving semiconductor testing, I have been regularly invited by
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`conferences and industry events to conduct training courses on cutting edge
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`technical topics in my specialty. I have conducted almost 100 such courses,
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`ranging from a half day to three days in length, in over a dozen different countries,
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`and in-house for many major companies (IBM, Texas Instruments, AMD, National
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`Semiconductor, NXP, Advantest, Bell Labs, etc.). For more than ten years, I have
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`been regularly invited to conduct a half or full day short course on statistical and
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`adaptive test methods at the flagship International Test Conference, the largest
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`annual technical meeting on integrated circuit testing worldwide.
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`10.
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`I also have received numerous research and teaching awards. I was
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`made a Fellow of IEEE, the world’s largest engineering professional society, in
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`2002 for “contributions to defect based testing and test optimization in VLSI
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`circuits”. I am a Golden Core member of the IEEE Computer Society. I served
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`two elected terms (2007-11) as Chair of the IEEE Test Technology Technical
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`Council (TTTC), and I currently serve (2011-15) on the Board of Governors of the
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`IEEE Council on Design Automation (CEDA).
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`III. My Understanding of the Governing Law
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`A.
`11.
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`Types of Claims -- Dependent and Independent Claims
`I understand that patents have two types of claims – independent
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`claims and dependent claims. I understand that independent claims only include
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`the aspects stated in those independent claims. I further understand that dependent
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`claims include the aspects stated in the dependent claim plus the aspects stated in
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`the independent claim from which the dependent claim depends.
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`B.
`12.
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`Patentability and Validity of Claims
`I understand that an invention described in a patent must be new, it
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`cannot be obvious, and it must be useful to be a valid patent. To determine
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`whether a patent meets these requirements, one must look at each of the claims. I
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`understand that a patent claim is not valid if it is not new, obvious, or not useful.
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`13.
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`I understand that prior art refers to publically available information
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`(e.g., published, on sale, or in public use in the United States) before the “critical
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`date” of a particular patent claim.
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`14.
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`I understand that a patent claim is not new (which I understand to be
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`termed “anticipated”) if each element of the claim is disclosed expressly or
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`inherently in a single prior art reference.
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`15.
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`I further understand that the determination of whether a claim is
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`obvious is evaluated from the perspective of a person of ordinary skill in the
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`relevant area of the invention, at the time the invention was made. In analyzing
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`obviousness, I understand that it is important to understand the scope of the claims
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`at issue, the level of skill in the relevant area of the invention, the scope and
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`content of the prior art references, the differences between the prior art references
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`and the claims, and any secondary considerations that would demonstrate that an
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`invention is not obvious. I also understand that if a technique has been used to
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`improve one system or method, and a person of ordinary skill in the relevant area
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`would improve similar systems or methods in the same way, using the technique is
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`obvious unless actual application is beyond his or her skill to do so. I understand
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`that if more than one reference is used, there must be a motivation to combine the
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`references through an explicit or implicit teaching, suggestion or motivation to
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`arrive at the invention, or of prior art references, such as common sense of a person
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`of skill in the relevant area, market demand, or an industry need for the invention.
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`16.
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`I understand that secondary considerations indicating that a patent
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`claim is not obvious may include evidence of commercial success caused by the
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`invention, evidence of a recognized need that was solved by the invention,
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`evidence that others copied the invention, or evidence that the invention achieved a
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`surprising result. I understand that such secondary considerations must have a
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`causal relationship to the elements of a claim.
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`17.
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`I am unaware of any such secondary considerations relating to any
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`claim (namely, claims 1 through 20) of the ‘373 Patent.
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`C.
`18.
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`IPR Proceedings and Claim Interpretation
`I understand that this “inter partes review” (“IPR”) proceeding is a
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`proceeding before the United States Patent and Trademark Office (“USPTO”) for
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`challenging the patentability of the ‘373 Patent. I understand that an IPR is
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`conducted by the Patent Trial and Appeal Board (the “Board”) if a trial is
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`instituted.
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`19.
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`I understand that in an IPR proceeding, the Board gives the challenged
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`patent’s claims their broadest reasonable interpretation in light of the specification
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`of the patent. I understand that the specification of a patent includes all of the
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`figures, background discussions, any detailed description, examples, and claims
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`within the patent document.
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`20.
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`I understand that the Board will look at the specification of the patent
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`to see if a claim term has been defined by the patent applicant, and if not, will
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`apply the broadest reasonable ordinary meaning from the perspective of a person
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`of ordinary skill in the relevant area. However, I also understand that if a term has
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`no previous meaning to those of ordinary skill in the relevant area, its meaning
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`then must be found in the patent.
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`D. Relevant Time Period
`I understand that the patent application leading to ‘373 Patent (Ex.
`21.
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`1001) was filed on May 24, 2002. I understand that the ‘373 Patent purports to
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`claim the benefit of U.S. Provisional Application No. 60/293,577, filed on May 24,
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`2001; U.S. Provisional Application No. 60/295,188, filed May 31, 2001; U.S.
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`Provisional Application No. 60/374,328, filed on April 21, 2002; and U.S.
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`Continuation-in-part Application No. 09/872,195, filed May 31, 2001 (the “Priority
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`Applications”). (Id.) It is my understanding that the owner of the ‘373 Patent
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`might try to evidence a priority date based on one or more of the Priority
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`Applications.
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`22. Based on my review of the Priority Applications, it is my view that
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`none of the claims of the ‘373 Patent are supported by U.S. Provisional No.
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`60/293,577, filed May 24, 2001, or U.S. Provisional Application No. 09/872,195,
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`filed May 31, 2001. It is also my view that at least claims 2, 4, 5, 7, 9, 11, 12, 14,
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`16, 18, and 20 are not supported by U.S. Provisional Application No. 60/295,188,
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`filed May 31, 2001. It is also my view that at least claims 2, 9, and 16 are not
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`supported by U.S. Provisional Application No. 60/374,328, filed April 21, 2002.
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`23.
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`I understand that the earliest priority date a patent owner may
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`evidence is one year prior to the earliest effective filing date of a patent. However,
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`during the Reexamination of the ‘373 Patent, filed in November 2006, the inventor
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`of the ‘373 Patent contested the patentability of the ‘373 Patent and submitted
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`Gneiting which has a publication date of October 11, 2000 as evidence that at least
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`independent claims 1, 8, and 15 were invalid. (See Ex. 1009.) Clearly the inventor
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`believed that there was no opportunity to prove a priority date before this
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`publication date.
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`24. The following table summarizes the earliest possible priority dates
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`that I have attributed to each claim for the purpose of my analysis.
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`Claims
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`1, 8, 15
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`2, 9, 16
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`3, 10, 17
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`4, 11, 18
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`5, 12, 20
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`6, 13
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`7, 14
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`19
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`Priority date used
`for my analysis
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`October 12, 2000
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`May 24, 2001
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`October 12, 2000
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`April 21, 2001
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`April 21, 2001
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`October 12, 2000
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`April 21, 2001
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`October 12, 2000
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`Level of Ordinary Skill in the Art and Relevant Timeframe
`E.
`25. The ‘373 Patent is directed to a method and apparatus for testing
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`semiconductors, including the identification of defective or potentially defective
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`semiconductor components based on the analyzed data. Accordingly, I believe that
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`a person of ordinary skill in the art in the field of developing the technology of the
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`‘373 Patent would have a Bachelor of Science degree in combination with 1-2
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`years training in semiconductor testing. This description is approximate, and a
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`higher level of training or skill might make up for less education, and vice-versa.
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`26.
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`I believe that I would qualify as at least a person of ordinary skill in
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`the art in the fields of using and developing the technology of the ‘373 Patent, as
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`described above, and that I have a sufficient level of knowledge, experience and
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`education to provide an expert opinion in these fields of the ‘373 Patent. This is
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`true regardless of whether the testimony provided in this opinion is given in the
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`past or present tense.
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`IV. Background of the Relevant Discipline of the ‘373 Patent
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`27.
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`In the field of semiconductor manufacturing, generally hundreds of
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`semiconductor circuits are printed or manufactured on a wafer at a time, and
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`hundreds of wafers may be manufactured on a manufacturing line. Each wafer
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`goes through up to 80 or more processing steps. The process is automated, and
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`optimized at each step as a result of extensive testing to reduce defects. In this
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`regard, it is desirable to know if any process step injects too many defects into a
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`wafer or group of devices on a wafer before the same defects are carried on in
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`further processing of the wafer, or injected into other wafers in the manufacturing
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`line. Providing test data to semiconductor test engineers during the manufacturing
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`process or after the semiconductor is manufactured allows the engineers to adjust
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`the manufacturing process in the future. For example, identifying defects during
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`the diffusion step may indicate that an extra level of cleaning is required, or that
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`the chemicals used are unclean, thereby alerting the process engineer to use a new
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`solution for the next wafer lot.
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`28. Up until about late 1980s, in the field of semiconductor testing,
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`integrated circuits were tested in an absolute way. That is, input signals were
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`applied to semiconductor circuits and if the expected response was observed, the
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`circuit was good. If the expected response was not received, the circuit was
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`declared bad. Using digital circuits as an example, when an expected 0’s and 1’s
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`pattern is received at the output in response to an input, the circuit is good.
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`Otherwise, the circuit is classified as bad, or defective. However, all possible test
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`cases cannot be applied; i.e., testing of some microprocessors would take an
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`inconceivable amount of time to apply all possible input cases. So, for any test
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`applied to a circuit, the test is necessarily incomplete. And not only is it
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`incomplete, but, only a fraction of all possible defects is tested.
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`29. As shown by literature, the automated test equipment (ATE) industry
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`was started as early as the late 1960s by Teradyne and other companies to test
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`linear analog ICs. (Ex. 1010 at 612-13.) ATE is generally semiconductor test
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`equipment that includes some form of automation in a manufacturing environment,
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`for example by way of being synchronized with other equipment or by being
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`controlled by a computer to automatically perform a series of tasks. (Id. at 611-13.)
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`30.
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` By the 1980s, automation was recognized in semiconductor testing as
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`common, and wafer processing was controlled and monitored remotely using
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`workstation computers. (Ex. 1011 at 30.) These computers stored and applied
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`“recipes” or process programs to computer control repeatability of process steps.
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`(Id.) Using a computer, a test engineer could “request equipment status, store
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`measurement data, remotely control equipment, store and restore calibration data,
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`and store and restore recipes. Equipment-generated alarm conditions [could be]
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`recorded and reported.” (Id.)
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`31. These computer systems also implemented statistical software to
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`assist technicians in analyzing data received from semiconductor test equipment.
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`For example, in 1985, Hewlett Packard implemented a statistical software program
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`called Enhansys into its semiconductor test environment. (Ex. 1012 at 9.)
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`Enhansys enabled engineers to retrieve and visually analyze semiconductor test
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`data. (Ex. 1013 at 9.) Using Enhansys, test engineers could “sort, analyze, and
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`query a data subset, and obtain a hard-copy report.” (Id.)
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`32. The amount of data collected by computer-enabled test systems
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`continued to grow as semiconductor processing and testing became more
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`automated, and as the number of test measurements for each device increased.
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`Mass production of semiconductor devices only amplified the amount of data
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`collected. By the late 1980s, statistical software programs were in place to
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`supplement visual graph inspection to determine whether a circuit was good or
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`bad. (See Ex. 1002.) In this manner, a computer generated a graph using statistical
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`pen-and-paper mythologies for statistical charting that have been used since the
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`1920’s to determine the quality of a batch of products or to control a process for
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`the production of such products. (Ex. 1003 at 23, Preface.) Large amounts of test
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`results produced from semiconductor test equipment could be analyzed by
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`comparing the data against sample populations of statistically similar data. (See
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`Ex. 1002 Abstract.)
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`33.
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`If the software program detected that a device under test behaved in
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`an unexpected fashion different from the sample population, for example by
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`producing “outlying” test results that stray from the sample population or
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`otherwise behave in an outlier fashion, the device was classified as potentially
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`defective and/or less reliable.
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`34. By the 1990s, the trend in the industry was to offer automated test
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`equipment (ATE) with mixed signal capabilities. (Ex. 1010 at 613.) Mixed-signal
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`ATE systems were and still are sophisticated computer controlled systems that
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`operate under a “test plan” written in a high level programming language such as C
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`to test both analog and digital qualities of devices under test. Under the control of
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`the test plan, the ATE “generates and applies stimuli to an IC . . . senses and
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`digitizes the IC's responses, and . . . analyzes these responses.” (Id.)
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`35. During this time, new statistical testing methods were employed for
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`dealing with both analog and digital test results, and for more efficiently
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`classifying whether a device was good, bad, or marginal/less reliable.
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`V. The Technical Overview of The ‘373 Patent
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`36. The ‘373 Patent is directed to a system for testing semiconductors.
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`(Ex. 1001 Abstract.) In this regard, I understand that ‘373 Patent to be an attempt
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`to capture the methodology of outlier detection developed and used during the
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`1990s, and its application to known ATE.
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`37. The ’373 Patent describes testing semiconductors with test equipment
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`connected to a computer to detect whether a test result is an outlier. Figure 1,
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`reproduced below, depicts a tester 102 that tests components 106. (Ex. 1001 Fig.
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`1.)
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`(Ex. 1001, Fig. 1)
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`38. The tester 102 used by the ’373 Patent is described as “automatic test
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`equipment (ATE)” or “any test equipment that tests components 106 and generates
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`output data.” (Id. at 3:24-37.) A “Teradyne tester” is given as an example. (Id. at
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`3:37.) The tester 102 is described as operating in connection with a “computer
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`system 108 that receives tester data from the tester.” (Id. at 3:42-49.)
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`39. The computer implements a statistical engine (software) running on
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`the computer to analyze data received from the tester. (Id. at 3:45-51.) The
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`software includes a supplementary data analysis element 206 which analyzes
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`output test data from the tester 102. (Id. at 5:25-33, FIG. 2.) The ’373 patent
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`explains how the supplementary data analysis element 206 identifies outliers:
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`The supplementary data analysis element 206 may operate in any
`suitable manner to designate outliers, such as by comparison to
`selected values and/or according to treatment of the data in the data
`smoothing process. For example, an outlier identification element
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`according to various aspects of the present invention initially
`automatically calibrates its sensitivity to outliers based on selected
`statistical relationships for each relevant datum (step 434). Some of
`these statistical relationships are then compared to a threshold or other
`reference point, such as the data mode, mean, or median, or
`combinations thereof, to define relative outlier threshold limits. In the
`present embodiment, the statistical relationships are scaled, for
`example by one, two, three, and six standard deviations of the data, to
`define the different outlier amplitudes (step 436). The output test data
`may then be compared to the outlier threshold limits to identify and
`classify the output test data as outliers (step 438).
`(Ex. 1001 at 13:49-65 (emphasis added).)
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`40. The supplementary data analysis element 206 includes an outlier
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`classification element 212, which is “configured to identify and/or classify the
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`various outliers in the data according to selected algorithms.” (Id. at 14:7-14.) I
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`note that the patent owner distinguished part classification from outlier
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`identification, stating that part classification may be based on “traditional threshold
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`testing” and/or the “number of outliers and in what range the outliers fall.” (Ex.
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`1006 at 9-10.) To the extent that the classification element classifies data
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`congruent with the statistical rules disclosed in the above example of outlier
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`identification (Ex. 1001 at 13:49-65), the ’373 patent explains that the
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`classification of the data may be used to identify outliers. For example, the ’373
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`patent explains:
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`The outlier classification element may classify data in accordance
`with conventional SPC control rules, such as Western Electric rules,
`to characterize the data.
`The outlier classification element suitably classifies the data using a
`selected set of classification
`limit calculation methods. Any
`appropriate classification methods may be used to characterize the
`data according to the needs of the operator. The present outlier
`classification element, for example, classifies outliers by comparing
`the output
`test data
`to selected
`thresholds, such as values
`corresponding to one, two, three, and six statistically scaled standard
`deviations from a threshold, such as the data mean, mode, and/or
`median. The identification of outliers in this manner tends to
`normalize any identified outliers for any test regardless of datum
`amplitude and relative noise.
`
` (Id. at 1-16 (emphasis added). Compare with id. at 14:59-61 (classifying
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`components).)
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`41. The ’373 Patent further explains that the computer may generate an
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`output report. The output is broadly defined by the ’373 Patent, which states that
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`“[a]ny form, such as graphical, numerical, textual, printed, or electronic form, may
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`be used to present the output report for use or subsequent analysis.” (Ex. 1001 at
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`18:2-4.) The ’373 Patent also states that the “output report may be provided in any
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`suitable manner, for example output to a local workstation, sent to a server,
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`activation of an alarm, or any other appropriate manner (step 712). In one
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`embodiment, the output report may be provided off-line such that the output does
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`not affect the operation of the system.” (Id. at 18:57-62.)
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`VI. My Interpretation of Certain Claim Terms
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`“component”
`
`A.
`42. The ’373 Patent specification defines component by example to
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`include “semiconductor devices on a wafer, circuit boards, packaged devices, or
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`other electrical or optical systems.” (Ex. 1001 at 3:26-29.) The ‘373 Patent
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`provides one other example in which "the general resistivity of resistor components
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`in the semiconductor devices varies across the wafer," and discusses measuring the
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`resistance of a “resistor component." (Ex. 1001 at 17:30-36 (emphasis
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`added).) Because the ’373 Patent states that these resistor components are in the
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`semiconductor devices, it is my understanding that a skilled person would
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`conclude that the components may be discrete portions of a semiconductor device.
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`43. Other than the foregoing examples, the ’373 Patent does not limit a
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`component to any specific structure. Instead, the ’373 Patent describes the
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`identification and/or selection of components generically, stating that a component
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`may be identified based on “x-y coordinates corresponding to a position of the
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`component 106 on a wafer map for the tested wafer” (Ex. 1001 at 4:15-18), and
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`that “predetermined components may be selected according to any criteria, such as
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`data for various circumferential zones, radial zones, random components, or
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`individual stepper fields” (id. at 18:17-20). The ’373 Patent states that a
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`“component” produces an output signal in response to a signal applied to the
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`component by a tester, but does not discuss how such signals are structurally
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`applied. (Ex. 1001 at 6:22-25.)
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`44. Accordingly,
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`it
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`is my opinion
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`that
`
`the broadest reasonable
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`interpretation of “component” is “any discrete portion of a semiconductor wafer,
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`including any zone, field, chip, device, or other discrete portion having an
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`identifiable position with respect to the wafer and that is subject to testing.”
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`“recipe file”
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`B.
`45. Claims 2, 9, and 16 recite configuration data being in or read from a
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`recipe file using the computer system, and claim 16 recites “identifying the outlier
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`according to the configuration data in the recipe file.”
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`46. The ’373 Patent discloses that “configuration algorithms, parameters,
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`and any other criteria may be stored in a recipe file.” (Ex. 1001 at 6:11–18.)
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`However, this disclosure does not require, for example, that a configuration
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`algorithm or parameter actually be stored in the claimed recipe file, and does not
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`further define the recipe file with respect to the claims. The ’373 Patent also
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`discloses “sensitivity parameters in a recipe configuration file” (Ex. 1001 at 17:1–
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`3); however, claim 16 recites a broader “recipe file.”
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`47. Accordingly,
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`it
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`is my opinion
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`that
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`the broadest reasonable
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`interpretation of “recipe file” is “a file storing configuration data for testing
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`purposes.”
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`VII. References Used In My Analysis
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`A. Lane - U.S. Patent No. 4,967,381
`48. U.S. Patent 4,967,381 (“Lane”) (Ex. 1002) describes a system that is
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`useful in process control of machines and processes, and which provides “a set of
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`predefined data management or data analysis tasks which the operator of the
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`system can use when using the system to run a selected process.” (Ex. 1002 at
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`2:56-3:39, 4:6-17.) “Acces