`Paper No. _____
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`________________________
`
`Linear Technology Corporation
`
`Petitioner
`
`v.
`
`In-Depth Test LLC
`
`Patent Owner
`
`Case No. IPR__________
`Patent No. 6,792,373
`
`________________________
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,792,373
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. §§ 42.1-42.80, 42.100-42.123
`________________________
`
`
`__________________________________________________________________
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`________________________
`
`Linear Technology Corporation
`
`Petitioner
`
`v.
`
`In-Depth Test LLC
`
`Patent Owner
`
`Case No. IPR__________
`Patent No. 6,792,373
`
`________________________
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,792,373
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. §§ 42.1-42.80, 42.100-42.123
`________________________
`
`
`__________________________________________________________________
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
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`TABLE OF CONTENTS
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`U.S. Patent No. 6,792,373
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`INTRODUCTORY STATEMENT .......................................................................... 1
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`I.
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`COMPLIANCE WITH REQUIREMENTS FOR A PETITION FOR
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`INTER PARTES REVIEW .............................................................................. 1
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`A. Grounds for Standing (37 C.F.R. § 42.104(a)) .................................... 1
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`B.
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`Payment of Fees (37 C.F.R. § 42.103) ................................................. 2
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`C. Mandatory Notices (37 C.F.R. § 42.8(a)(1)) ........................................ 2
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`(a) Real Party-In-Interest (37 C.F.R. § 42.8(b)(1)) ......................... 2
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`(b) Related Matters (37 C.F.R. § 42.8(b)(2)) .................................. 2
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`(c)
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`(d)
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`Lead and Back-Up Counsel (37 C.F.R. § 42.8(b)(3)) ............... 2
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`Service Information (37 C.F.R. § 42.8(b)(4)) ............................ 3
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`II.
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`STATEMENT OF THE PRECISE RELIEF REQUESTED ......................... 3
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`III.
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`SUMMARY OF PRIOR ART PRESENTED BY PETITIONER ................. 5
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`A. U.S. Patent No. 6,366,108 to O’Neill et al. .......................................... 6
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`B.
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`C.
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`U.S. Patent No. 5,206,582 to Ekstedt et al. .......................................... 6
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`Z. Ghaemi, Application of data screening to the
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`characterization of integrated circuits ................................................. 6
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`D. U.S. Patent No. 5,442,282 to Rostoker et al. ....................................... 6
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`E.
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`F.
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`U.S. Patent No. 5,761,064 to La et al. .................................................. 7
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`Daasch, Variance Reduction Using Wafer Patterns in IddQ Data ........ 7
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`i
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`U.S. Patent No. 6,792,373
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`IV. THE ‘373 PATENT ........................................................................................ 8
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`A.
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`B.
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`C.
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`Prosecution History and Priority Dates of the ‘373 Patent .................. 8
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`The ‘373 Patent’s Claims ................................................................... 10
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`Brief Overview of the ‘373 Patent ..................................................... 10
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`V.
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`PERSON OF ORDINARY SKILL IN THE ART ....................................... 14
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`VI. CLAIM CONSTRUCTION (37 C.F.R. §§ 42.104(B)(3)) ........................... 14
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`A.
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`B.
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`C.
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`D.
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`E.
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`F.
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`“outlier” .............................................................................................. 14
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`“output report” .................................................................................... 15
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`“section group of components on a wafer” ........................................ 15
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`“recipe file” ........................................................................................ 16
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`“Correlate the test data” ..................................................................... 16
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`“identify the outlier at run time” ........................................................ 17
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`VII.
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`IDENTIFICATION OF THE CHALLENGE (37 C.F.R. § 42.104(B)) ...... 17
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`A.
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`All Independent Claims are Unpatentable Based on O’Neill ............ 17
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`(a) O’Neill - U.S. Patent No. 6,366,108 ........................................ 17
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`(b)
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`Independent claims 1, 8, and 15 based on O’Neill .................. 21
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`B.
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`All Independent Claims are Unpatentable Based on Ekstedt ............ 29
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`(a)
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`Ekstedt - U.S. Patent No. 5,206,582 ........................................ 29
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`(b) Ghaemi – Non-patent Publication from 1989 .......................... 32
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`ii
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`U.S. Patent No. 6,792,373
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`(c)
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`Independent claims 1, 8, and 15 based on Ekstedt or
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`Ekstedt and Ghaemi ................................................................. 33
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`C.
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`All Dependent Claims are Unpatentable ........................................... 42
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`(a) Dependent claims 2, 9, 16 – O’Neill, Ekstedt .......................... 42
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`(b) Dependent claims 3, 10, and 17 –O’Neill, Ekstedt,
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`Rostoker ................................................................................... 44
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`(c) Dependent claims 4, 11, and 18 - O’Neill, Ekstedt,
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`Ghaemi ..................................................................................... 47
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`(d) Dependent claims 5, 12, and 20 - O’Neill, Ekstedt,
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`Ghaemi, La ............................................................................... 50
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`(e) Dependent claims 6 and 13 - O’Neill or Ekstedt ..................... 54
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`(f) Dependent claims 7, 14, and 19 – O’Neill, Ekstedt,
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`Daasch ..................................................................................... 56
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`VIII. CONCLUSION ............................................................................................. 60
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`IX. PRAYER FOR RELIEF ............................................................................... 60
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`CERTIFICATE OF SERVICE ............................................................................... 61
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`iii
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`U.S. Patent No. 6,792,373
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`INTRODUCTORY STATEMENT
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`Linear Technology Corporation (“Petitioner”) in accordance with 35 U.S.C.
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`§§ 311 – 319 and 37 C.F.R. §§ 42.1-.80, 42.100-42.123, respectfully requests inter
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`partes review (“IPR”) for Claims 1-20 of U.S. Patent No. 6,792,373 (“the ‘373
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`Patent”). (Ex. 1001) Accordingly, this petition seeks review and cancellation of all
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`20 claims of the ‘373 Patent.
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`In short, claims 1, 2, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 18, 19, and 20 of
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`the ‘373 Patent are anticipated under 35 U.S.C. § 102 by U.S. Patent No. 6,366,108
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`(“O’Neill”) (Ex. 1019). Alternatively, claims 1, 2, 5, 6, 8, 9, 12, 13, 15, 16, 19, and
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`20 are anticipated under 35 U.S.C. § 102 by U.S. Patent 5,206,582 (“Ekstedt”) (Ex.
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`1021), or at minimum unpatentable as obvious under 35 U.S.C. § 103 in view of
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`Ekstedt and Application of Data Screening to the Characterization of Integrated
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`Circuits, CAN. J. PHYS. , Vol. 67, No. 4, 221 (Apr. 1989) (“Ghaemi”) (Ex. 1018).
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`The remaining dependent claims are unpatentable under § 103 in view of the
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`foregoing and one or more references as discussed herein.
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`I.
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`Compliance With Requirements for A Petition For Inter Partes Review
`A. Grounds for Standing (37 C.F.R. § 42.104(a))
`Petitioner certifies that (1) the ’373 Patent is available for inter partes
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`review, and that (2) Petitioner is not barred or estopped from requesting inter
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`partes review challenging the identified claims. Petitioner has submitted this
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`Petition within one year of having been served with an infringement complaint by
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`1
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`U.S. Patent No. 6,792,373
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`the patent owner. 37 U.S.C. § 315(b). A true copy of the Proof of Service of
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`Summons and Complaint, showing the date of service of September 29, 2014 is
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`submitted herewith. (Exhibit 1029) The ’373 Patent has not been the subject of a
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`prior inter partes review. Petitioner has not filed a civil action challenging the
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`validity of a claim of the ‘373 Patent. 37 U.S.C. § 315(a).
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`Payment of Fees (37 C.F.R. § 42.103)
`
`B.
`The required fees are submitted with this petition. The Director may charge
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`any fee deficiency or credit any overpayment to Deposit Account No. 504914.
`
`C. Mandatory Notices (37 C.F.R. § 42.8(a)(1))
`(a) Real Party-In-Interest (37 C.F.R. § 42.8(b)(1))
`Linear Technology Corporation (“Linear”) is the real party in interest.
`
`(b) Related Matters (37 C.F.R. § 42.8(b)(2))
`The ‘373 Patent is owned by a Patent Assertion Entity, which has asserted it
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`in five co-pending litigations filed in 2014 in Delaware: In-Depth Test LLC v.
`
`Intersil Corp., Case No. 1-14-cv-00886 (D. Del. Jul. 8, 2014); In-Depth Test LLC
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`v. Maxim Integrated Prods., Inc., Case No. 1-14-cv-00887 (D. Del. Jul. 8, 2014);
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`In-Depth Test LLC v. Vishay Intertechnology, Inc., Case No. 1-14-cv-00888 (D.
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`Del. Jul. 8, 2014); In-Depth Test LLC v. Fairchild Semiconductor Corp., Case No.
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`1-14-cv-01090 (D. Del. Aug. 22, 2014); In-Depth Test LLC v. Linear Tech. Corp.,
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`Case No. 1-14-cv-01091 (D. Del. Aug. 22, 2014).
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`(c) Lead and Back-Up Counsel (37 C.F.R. § 42.8(b)(3))
`2
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`U.S. Patent No. 6,792,373
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`Service may be had to Lead Counsel and Backup Counsel for Petitioner at
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`the following, by mail, email or fax.
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`Lead Counsel:
`Backup Counsel:
`Kenneth Cheney
`Bernard Knight
`Reg. No. 61,841
`Reg. No. L0911
`kcheney@mwe.com
`bknight@mwe.com
`Tel: (949) 757-7111
`Tel: (202) 756-8421
`Fax: (949) 851-9348
`Fax: (202) 591-2699
`McDermott Will & Emery
`McDermott Will & Emery
`4 Park Plaza
`500 North Capitol Street, N.W.
`Irvine, CA 92614
`Washington, DC 20001
`(d) Service Information (37 C.F.R. § 42.8(b)(4))
`Papers concerning this matter should be addressed to counsel at the
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`addresses provided above. Petitioner consents to electronic service by email at:
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`IPdocketMWE@mwe.com, bknight@mwe.com, and kcheney@mwe.com.
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`II.
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`STATEMENT OF THE PRECISE RELIEF REQUESTED
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`Petitioner requests inter partes review and cancellation of Claims 1-20 of the
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`ʼ373 Patent (Ex. 1001) based on the grounds set forth under 35 U.S.C. §§ 102
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`and/or 103. This petition presents evidence of unpatentability and establishes a
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`reasonable likelihood that the Petitioner will prevail in establishing that all of the
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`claims are unpatentable. The chart below summarizes how the claims may be
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`grouped for the instant challenge, and the grounds for invalidity as to each claim.
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`Where more than one ground exists for a claim, the ground(s) relying on additional
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`references should be treated as alternative(s).
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`3
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`U.S. Patent No. 6,792,373
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`All Claims are Unpatentable Based on O’Neill
`35 U.S.C.
`References
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`§ 102(a)/(e)
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`O’Neill
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`Claims
`1, 2, 4, 5, 6, 7, 8, 9,
`11, 12, 13, 14, 15,
`16, 18, 19, and 20
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`3, 10, 17
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`Claims
`1, 2, 3, 5, 6, 8, 9,
`10, 12, 13, 15, 16,
`17, 19, and 20
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`O’Neill in view of Rostoker
`§ 103(a)
`All Claims are Unpatentable Based on Ekstedt
`35 U.S.C.
`References
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`§ 102(b)
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`Ekstedt
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`4, 11, 18
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`§ 103(a)
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`Ekstedt in view of Ghaemi
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`7, 14
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`O’Neill anticipates all claims except dependent claims 3, 10, and 17, which
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`Ekstedt in view of Daasch
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`§ 103(a)
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`are directed to a “section group of components on a wafer.” As explained below, a
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`person of ordinary skill in the art would have considered the combination of
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`O’Neill and Rostoker to show the limitations of dependent claims 3, 10, and 17.
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`Ekstedt anticipates all claims except dependent claims 4, 11, and 18, which
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`are directed to calibrating a sensitivity for identifying outliers, and dependent
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`claims 7 and 14, which are directed to identifying outliers in smoothed test data.
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`As explained below, a person of ordinary skill in the art would have considered the
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`combination of Ekstedt and Ghaemi to show the limitations of dependent claims 4,
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`11, and 18, and would have considered the combination of Ekstedt and Daasch to
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`4
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`U.S. Patent No. 6,792,373
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`show the limitation of dependent claims 7 and 14.
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`Petitioner also raises the following alternative grounds in the event the
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`Board disagrees with Petitioner’s analysis of one or more of the above claims.
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`Claims
`2, 9, 16
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`5, 12, 20
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`7, 14, 19
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`1, 8, and 15
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`3, 10, 17
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`5, 12, 20
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`19
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`Alternative Grounds
`35 U.S.C.
`References
`O’Neill in view of Ekstedt
`§ 103(a)
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`§ 103(a)
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`§ 103(a)
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`§ 103(a)
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`§ 103(a)
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`§ 103(a)
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`§ 103(a)
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`O’Neill in view of La
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`O’Neill in view of Daasch
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`Ekstedt in view of Ghaemi
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`Ekstedt in view of Rostoker
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`Ekstedt in view of La
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`Ekstedt in view of Daasch
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`The Petitioner appreciates that the Board is charged with securing the just,
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`speedy and inexpensive resolution of every proceeding. 37 C.F.R. § 42.1(b).
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`Should the Board wish to have guidance as to Petitioner’s preferred grounds for
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`institution, Petitioner respectfully submits that O’Neill anticipates every claim of
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`the ‘373 Patent under 35 U.S.C. § 102 except dependent claims 3, 10, and 17, and
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`claims 3, 10, and 17 are unpatentable as obvious by O’Neill in view of Rostoker.
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`All of the grounds presented, however, are deserving of institution.
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`III. SUMMARY OF PRIOR ART PRESENTED BY PETITIONER
`Petitioner relies upon the following patents and printed publications.
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`5
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`U.S. Patent No. 6,792,373
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`A. U.S. Patent No. 6,366,108 to O’Neill et al.
`U.S. Patent No. 6,366,108 to O’Neill et al. (“O’Neill”) (Ex. 1019) was filed
`
`on December 1, 1998, and issued on April 2, 2002. O’Neill is directed to testing
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`quiescent current (IddQ) in semiconductor devices. (Ex. 1019, Abstract; Ex. 1028 ¶
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`45.) O’Neill is prior art to the ‘373 Patent under 35 U.S.C. § 102(a) or 102(e).
`
`B. U.S. Patent No. 5,206,582 to Ekstedt et al.
`U.S. Patent No. 5,206,582 to Ekstedt et al. (“Ekstedt”) (Ex. 1021) was filed
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`August 21, 1990, and issued April 27, 1993. Ekstedt discloses defining and
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`executing parametric test sequences using automated test equipment (ATE). (Ex.
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`1028 ¶ 52.) Ekstedt is prior art to the ‘373 Patent under 35 U.S.C. § 102(b).
`
`C. Z. Ghaemi, Application of data screening to the characterization of
`integrated circuits
`Zarrin Ghaemi, Application of data screening to the characterization of
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`integrated circuits (“Ghaemi”) (Ex. 1018) is a non-patent publication that was
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`published in the Canadian Journal of Physics in April 1989, as part of the
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`Proceedings of the Fourth Canadian Semiconductor Technology Conference.
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`Ghaemi discloses a data-screening method
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`that automatically “detects
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`abnormalities (clusters and outliers) in data.” (Ex. 1018 at 221, Abstract; Ex. 1028
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`¶ 139.) Ghaemi is prior art to the ‘373 Patent under 35 U.S.C. § 102(b).
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`D. U.S. Patent No. 5,442,282 to Rostoker et al.
`U.S. Patent 5,442,282 (“Rostoker”) et al. (Ex. 1024) was filed July 2, 1992,
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`6
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`U.S. Patent No. 6,792,373
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`and issued August 15, 1995. Rostoker discloses selectively testing a plurality of
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`unsingulated dies on a semiconductor wafer (using a selection mechanism resident
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`on the wafer). (Ex. 1024, Abstract, 4:39-43; Ex. 1028 ¶ 53.) Using a selection
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`mechanism, test signals may be selectively applied to any portion of the wafer.
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`(Ex. 1024 at 4:39-43, 32:12-16; Ex. 1028 ¶ 53.) Rostoker is prior art to the ‘373
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`Patent under 35 U.S.C. § 102(b).
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`E. U.S. Patent No. 5,761,064 to La et al.
`U.S. Patent 5,761,064 to La et al. (“La”) (Ex. 1025) was filed October 6,
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`1995, and issued June 2, 1998. La discloses “an automated semiconductor wafer
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`defect management system.” (Ex. 1025 at 1:7-10; Ex. 1028 ¶ 54.) La is prior art to
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`the ‘373 Patent under 35 U.S.C. § 102(b).
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`F. Daasch, Variance Reduction Using Wafer Patterns in IddQ Data
`W. Robert Daasch, Variance Reduction Using Wafer Patterns in IddQ Data,
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`in INT’L TEST CONF. 2000 Proc. 189-198 (Oct. 3, 2000) (“Daasch”) (Ex. 1020) is a
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`non-patent publication directed to the systematic use of die location and patterns to
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`reduce variance in semiconductor test data. (Ex. 1020, Abstract.) Daasch was
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`presented during the Reexamination of the ‘373 Patent. However, the application
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`of Daasch to the dependent claims (7, 14, and 19) was not relevant to the final
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`decision in the Reexamination. (See Ex. 1013 at 6 (stating that Daasch does not
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`suggest the features of the independent claims); Ex. 1028 ¶ 55.) Daasch is prior art
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`7
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`U.S. Patent No. 6,792,373
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`to the ‘373 Patent under 35 U.S.C. § 102(b).
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`IV. The ‘373 Patent
`The ‘373 Patent generally describes a system for testing semiconductors.
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`Prosecution History and Priority Dates of the ‘373 Patent
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`A.
`The ‘373 Patent (U.S. App. No. 10/154,627) was filed on May 24, 2002, and
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`issued on September 14, 2004. (Ex. 1001.) The ‘373 Patent claims the benefit of
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`several provisional applications and a continuation-in-part application, the earliest
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`filed on May 24, 2001. Petitioner has reviewed these applications and does not
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`agree that they fully support all of the claims of the ‘373 Patent. (Ex. 1028 ¶ 22.)
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`During prosecution, the application for the ‘373 Patent was rejected as being
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`anticipated by U.S. Pat. 5,835,891 (“Stoneking”) or a non-patent literature
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`publication (“Becker”). (Ex. 1002.) The applicant of the ‘373 Patent conceded that
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`the applied references disclosed detecting outliers. (Ex. 1003 at 7-8.) The
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`applicant argued, however, that Becker did not disclose “a tester,” did not disclose
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`“identif[ing] outliers in the semiconductor test data,” and did not disclose
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`“generating test data for multiple components.” (Id. at 6.) The applicant argued
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`that Stoneking did not generate an “output report” or testing “at run time.” (Id. at
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`7-8.) The next action was a Notice of Allowance. (Ex. 1004.)
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`The ‘373 Patent was later the subject of Reexamination No. 90/008,313,
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`filed October 30, 2006 by the inventor of the ‘373 Patent. The inventor presented
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`8
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`U.S. Patent No. 6,792,373
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`Stoneking in combination with various secondary references to show, among other
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`things, the “output report.” In a first Office Action, the Examiner instead rejected
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`the claims based on U.S. Pat. 6,574,760 (“Mydill”). (Id.) Mydill detects Vdd and
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`IddQ for outliers using, for example, an “Iddq limit . . . or other outlier limit.” (Ex.
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`1027 at 7:39-43.)
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`In response the rejection, the patent owner conceded that Mydill included
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`detection of outliers, but argued that “the outliers are not identified in a report” and
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`that Mydill “fails to disclose identifying outliers in the test data at run time.” (Ex.
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`1010 at 3, 4-5.) The Examiner maintained the rejection (Ex. 1011), and the patent
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`owner appealed (Ex. 1012). The Examiner withdrew the rejection in response to
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`the appeal, and issued a Reexamination Certificate (Ex. 1013).
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`During the Reexamination, the inventor of the ‘373 Patent submitted a non-
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`patent publication by Thomas Gneiting (“Gneiting”), published October 11, 2000,
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`as evidence that at least the independent claims were invalid. (See Ex. 1005.)
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`Clearly the inventor believed that there was no opportunity to prove a priority date
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`before the publication date of Gneiting. (Ex. 1028 ¶ 23.) The priority status of
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`Gneiting was also not challenged by the patent owner. (See Ex. 1007.)
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`Accordingly, should the patent owner attempt to evidence a claim’s priority date
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`before the ‘373 Patent’s filing date, the earliest possible priority date would be
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`October 12, 2000, the day after the publication date of Gneiting. (Ex. 1028 ¶ 23.)
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`U.S. Patent No. 6,792,373
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`The ‘373 Patent’s Claims
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`B.
`The ‘373 Patent lists 20 claims, with claims 1, 8, and 15 being the
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`independent claims. Independent claim 1 is directed to a “test system,” claim 8 is
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`directed to a “data analysis system for semiconductor test data,” and claim 15 is
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`directed to a “method for testing semiconductors.” Claims 2-7 are dependent on
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`claim 1 (“first dependent claim set”), and claims 9-14 are dependent on claim 8
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`(“second dependent claim set”), and claims 16-20 are dependent on claim 15
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`(“third dependent claim set”). Many of the claims of the second and third
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`dependent claim sets are similar to if not the same as many of the claims of the first
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`dependent claim set. For efficiency, Petitioner discusses matching dependent
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`claims together in groups.
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`C. Brief Overview of the ‘373 Patent
`The ‘373 Patent describes testing semiconductors with test equipment
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`connected to a computer to detect whether a device under test is an outlier device
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`(i.e., defective or possibly defective). (Ex. 1028 ¶ 37.) Figure 1, reproduced
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`below, depicts a tester 102 that tests components 106 such as semiconductors on a
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`wafer. (Ex. 1001 at Fig. 1.)
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`(Ex. 1001, Fig. 1)
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`10
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`U.S. Patent No. 6,792,373
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`The tester 102 used by the ‘373 Patent is described as “automatic test
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`equipment (ATE)” or “any test equipment that tests components 106 and generates
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`output data.” (Id. at 3:24-37.) A “Teradyne tester” is given as an example. (Id. at
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`3:37.) The tester 102 is described as operating in connection with a “computer
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`system 108 that receives tester data from the tester.” (Id. at 3:42-49.)
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`The computer implements a statistical engine (software) running on the
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`computer to analyze data received from the tester. (Id. at 3:45-51.) The software
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`includes a configuration element that configures the test system for testing
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`semiconductor devices. (Id. at 5:23-38.) Configuration data may be stored, for
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`example, in a “configuration file,” or “recipe file.” (Id. 5:64-6:18; Ex. 1028 ¶ 39.)
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`The ‘373 Patent states that, “[a]s the tester 102 generates the test results, the
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`output test data for each component . . . is analyzed by the tester 102 to classify the
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`performance of the component 106, for example by comparison to the upper and
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`lower test limits.” (Id. at 6:52-57.) “Each test generates at least one result for at
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`least one of the components,” and the “output test data for each component . . . is
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`stored by the tester 102 in a data file.” (Id. at 6:32-33, 52-54.) The data file is
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`transferred to the computer for analysis (by supplementary data analysis element
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`206). (Id. at 6:52-66.) The system, in some implementations, is configured such
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`that the transfer and analysis of the data may be performed within “seconds or
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`minutes following generation of the test data.” (Id. at 7:15-18; Ex. 1028 ¶ 40.)
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`The computer described by the ‘373 Patent is configured to identify outliers
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`in the test data received from the tester. (Ex. 1028 ¶ 41.) For example, the “output
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`test data may then be compared to the outlier threshold limits to identify and
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`classify the output test data as outliers.” (Ex. 1001 at 13:63-65; Ex. 1028 ¶ 41.)
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`The ‘373 Patent explains that these threshold limits may be defined by the
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`comparison of statistical relationships to a “reference point, such as the data mode,
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`mean, or median.” (Ex. 1001 at 13:55-60; Ex. 1028 ¶ 41.)
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`Figure 9 of the ‘373 Patent, reproduced below, is illustrative of how outlier
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`detection may be performed in the ‘373 Patent.
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`(Ex. 1001, Fig. 9)
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`Outliers
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`U.S. Patent No. 6,792,373
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`Parts
`identified
`as outliers
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`Each data point (e.g., along the x-axis) depicted in Figure 9 corresponds to a
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`“part” (i.e., component). (Ex. 1028 ¶ 43.) An outlier is shown as any part that
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`produces a test result beyond the set threshold, including parts identified as “Bin 1
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`Outlier” and failing parts identified as “Test Limit Failures / Outlier.” (Id.; Ex.
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`1001 Fig. 9.)
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`The ‘373 Patent further explains that the computer connected to the tester
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`may generate an output report. (Ex. 1028 ¶ 44.) The output is broadly defined by
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`the ‘373 Patent, which states that “[a]ny form, such as graphical, numerical,
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`textual, printed, or electronic form, may be used to present the output report for use
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`or subsequent analysis.” (Ex. 1001 at 18:2-4.) The ‘373 Patent also states that the
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`“output report may be provided in any suitable manner, for example output to a
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`local workstation, sent to a server, activation of an alarm, or any other appropriate
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`manner (step 712). In one embodiment, the output report may be provided off-line
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`such that the output does not affect the operation of the system.” (Id. at 18:57-62.)
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`V.
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`PERSON OF ORDINARY SKILL IN THE ART
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`A person of ordinary skill in the art in the field of developing the technology
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`of the ‘373 Patent would have a bachelor of science degree in combination with 1-
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`2 years training in semiconductor testing. (Ex. 1028 ¶ 25.) This description is
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`approximate, and a higher level of training or skill might make up for less
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`education, and vice-versa.
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`VI. CLAIM CONSTRUCTION (37 C.F.R. §§ 42.104(b)(3))
`For inter partes review, the challenged claims must be given their broadest
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`reasonable construction in light of the specification of the ʼ373 Patent. 37 C.F.R. §
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`42.100(b). Petitioner addresses the meaning of certain claim terms in the course of
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`comparing the claims to the prior art. Petitioner submits this manner of addressing
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`the scope of the claims is appropriate for this proceeding, as it identifies the basis
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`of Petitioner’s contentions why
`
`the claims,
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`in
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`their broadest reasonable
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`construction in view of the specification, are anticipated by or would have been
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`obvious in view of the prior art being discussed.
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`Without further limiting the claims to other than their broadest reasonable
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`construction, Petitioner submits the following constructions are relevant to the
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`instant petition.
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`“outlier”
`
`A.
`The term “outlier” should be construed as “any semiconductor device or part
`14
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`or data point associated with the device or part that on some measure falls above or
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`below a threshold value.” (Ex. 1028 ¶¶ 66-67.) This is consistent with the ‘373
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`Patent, which states that “output test data may then be compared to the outlier
`
`threshold limits to identify and classify the output test data as outliers.” (Id.; Ex.
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`1001 at 13:63-65.) Figure 9 of the ‘373 Patent also depicts identifying parts as
`
`outliers when data associated with the part is above a threshold limit, including
`
`parts identified as “Bin 1 Outlier” and failing parts identified as “Test Limit
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`Failures / Outlier.” (Ex. 1001 Fig. 9; Ex. 1028 ¶ 43.)
`
`“output report”
`
`B.
`The term “output report” should be construed as “any result of a test
`
`communicated or stored in any form.” (Ex. 1028 ¶ 44.) This is consistent with the
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`‘373 Patent, which states that “[a]ny form, such as graphical, numerical, textual,
`
`printed, or electronic form, may be used to present the output report for use or
`
`subsequent analysis.” (Id.; Ex. 1001 at 18:2-4.) The ‘373 Patent also states the
`
`“output report may be provided in any suitable manner,” including by “an
`
`activation of an alarm.” (Ex. 1001 at 18:57-62; Ex. 1028 ¶ 44.)
`
`“section group of components on a wafer”
`
`C.
`The term “section group of components on a wafer” should be construed as
`
`“a group of components (e.g., semiconductor circuits) in any section of a wafer.”
`
`(Ex. 1028 ¶ 99.) This is consistent with the ‘373 Patent, which states that “[e]ach
`
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`15
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`U.S. Patent No. 6,792,373
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`section group includes one or more section arrays, and each section array includes
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`one or more sections of the same section types,” and that “[s]ection types comprise
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`various sorts of component 106 groups positioned in predetermined areas of the
`
`wafer.” (Id.; Ex. 1001 at 8:2-7.) Also, in the Appeal Brief filed in the
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`Reexamination, the patent owner argued that the “test data in the present patent
`
`relates to sectioning components on a wafer, rather than sectioning the wafers from
`
`other wafers.” (Ex. 1012 at 19.)
`
`“recipe file”
`
`D.
`The term “recipe file” should be construed as a “configuration data of any
`
`kind that would assist in the testing of the device under test or in the analysis of the
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`test results.” (Ex. 1028 ¶ 85.) This is consistent with the ‘373 Patent, which states
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`that “configuration algorithms, parameters, and any other criteria may be stored in
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`a recipe file for easy access, correlation to specific products and/or tests, and for
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`traceability.” (Ex. 1001 at 6:15-18 (emphasis added).) Moreover, computer files
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`may exist as memory-resident files (e.g., library files) or on tangible storage
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`mediums (e.g., on a disk drive). (Ex. 1028 ¶86.)
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`“correlate the test data”
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`E.
`The phrase “correlate the test data” should be construed as “any means by
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`which test data may be associated, including being associated with a data point or
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`something else.” (Ex. 1028 ¶ 110.) This is consistent with the ‘373 Patent, which
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`16
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`U.S. Patent No. 6,792,373
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`recognizes correlating test data, for example to find similarities was not new when
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`the application was filed. (Id. ¶109.) For example, the ‘373 Patent states the test
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`system “applies conventional correlation techniques to the data, for example to
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`identify potentially redundant or related tests.” (Id.; Ex. 1001 at 13:37-39.)
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`“identify the outlier at run time”
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`F.
`The phrase “identify the outlier at run time” should be construed as
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`“identifying a part or data point falling above or below a given threshold value
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`within minutes of the test equipment measuring the component and producing the
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`data point based on the test, for example within minutes of the test equipment
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`performing the test and storing the results.” (Ex. 1028 ¶ 119.) This is consistent
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`with the ‘373 Patent, which states that the computer “performs the analysis at run
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`time, i.e., within a matter of . . . minutes following generation of the test data.”
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`(Ex. 1001 at 7:15-18.)
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`VII. IDENTIFICATION OF THE CHALLENGE (37 C.F.R. § 42.104(B))
`A. All Independent Claims are Unpatentable Based on O’Neill
`(a) O’Neill - U.S. Patent No. 6,366,108
`U.S. Patent 6,366,108 (“O’Neill”) (Ex. 1019) is directed to detecting defects
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`within an electrical circuit, such as a semiconductor device, by analyzing quiescent
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`current ( “IDDQ”) drawn by the device. (Ex. 1019, Title, 1:9-23 Ex. 1028 ¶ 45.)
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`O’Neill discloses using test system 10, including a computer (computer system 31
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`implementing software analyzer 22) configured to analyze data received from
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`semiconductor test equipment (i.e., state generator 15, power supply unit 17, and
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`current meter 18), to detect whether a device under test (circuit 14) is defective.
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`(Ex. 1028 ¶ 45.) Figure 1 of O’Neill is representative of the test system 10:
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`(Ex. 1019 FIG. 1)
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`The test system 10 tests complementary metal oxide silicon (CMOS)
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`integrated circuits 14 (i.e., a semiconductor device or component). (Ex. 1019 at
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`4:15-17; Ex. 1028 ¶ 46.) Using the state generator 15, input signals are transmitted
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`to the circuit and “can be adjusted to transition the circuit 14 into different states”
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`during a test. (Ex. 1019 at 4:15-22.) While in various test states, power supply
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`current is passed to the circuit 14 by the current meter 18, which also monitors the
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`current and provides a test signal to analyzer 22. (Id. at 4:28-39.) O’Neill explains
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`that the test signal may be a voltage signal or a “digital signal having a digital
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`value corresponding with the current value of IDDQ.” (Id. at 4:34-44.)
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`Analyzer 22 is described by O’Neill as “implemented in software” operating
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`U.S. Patent No. 6,792,373
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`on computer system 31 (see, e.g., id. at 4:49-51, Fig. 2; Ex. 1028 ¶ 47). “The
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`analyzer 22 is designed to receive the test signal and to detect defects in the circuit
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`14 based on the test signal.” (Ex. 1019 at 4:45-46.) The analyzer 22 detects defects
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`by comparing the value of the test signal to statistical reference or threshold values.
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`For instance, O’Neill states that the “analyzer 22 . . . is configured to calculate or
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`otherwise determine upper and lower threshold values for the test signal.” (Id. at
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`5:35-37.) Using the calculated threshold values, the analyzer 22 identifies outliers
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`in test data received from the test system 10. (Ex. 1028 ¶ 47.)
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`O’Neill calculates an upper threshold value by adding an “outlier margin
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`value” to a measured current signature for the circuit in a defect free state, and
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`calculates a lower threshold value by subtracting the outlier margin value. (Ex.
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`1019 at 5:46-6:7; Ex. 1028 ¶ 48.) In this regard, O’Neill calculates a standard
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`deviation of sample IDDQ data by performing an iterative linear regression
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`(removing outliers at each iteration) on a sample population of test data. (Ex. 1019
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`at 6:47-57; Ex. 1028 ¶ 48.) The result of the linear regression is a “fitted line” or
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`“curve” that represents a circuit’s “defect free behavio
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