(12) United States Patent
`Tabor
`
`111111111111111111111111111111111111111111111111111111111111111111111111111
`US006792373B2
`US 6,792,373 B2
`(10) Patent No.:
`Sep.14,2004
`(45) Date of Patent:
`
`(54) METHODS AND APPARATUS
`SEMICONDUCTOR
`TESTING
`
`FOR
`
`(75)
`
`Inventor:
`
`Eric Paul Tabor, Gilbert, AZ (US)
`
`(73) Assignee:
`
`Test Advantage,
`
`Inc., Tempe, AZ (US)
`
`( *) Notice:
`
`Subject
`patent
`U.S.c.
`
`the term of this
`to any disclaimer,
`is extended or adjusted under 35
`154(b) by 12 days.
`
`(21) Appl. No.: 10/154,627
`
`Filed:
`
`May 24, 2002
`
`Prior Publication Data
`us 2003/0014205 A1 Jan. 16,2003
`
`Related U.S. Application Data
`
`filed on
`
`Continuation-in-part of application No. 09/872,195,
`May 31, 2001, now abandoned.
`filed on May 24,
`Provisional application No. 60/293,577,
`2001, provisional application No. 60/295,188,
`filed on May
`31, 2001, and provisional application No. 60/374,328,
`filed
`on Apr. 21,2002.
`Int. CI?
`U.S. CI.
`
`...... ........ ........ G06F 19/00
`702/108; 702/117; 702/118;
`702/119; 702/120
`702/84, 108, 117,
`Field of Search
`702/118, 119, 120, 121, 122, 123, 124,
`125,179,182,183,187,189,190;
`714/721,
`724; 438/10, 14
`
`,J16
`
`SERVER
`
`114
`
`.I\.
`
`<
`
`DATA-
`BASE
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,668,745 A *
`9/1997 Day
`5,835,891 A * 11/1998 Stoneking
`6,184,048 B1 *
`2/2001 Ramon
`6,366,851 B1 *
`4/2002 Chojnacki et al.
`
`OTHER PUBLICATIONS
`
`702/121
`702/117
`438/14
`701/208
`
`Clauia Becker, Performance Criteria for Multivariate outlier
`Identification
`procedures,
`2000, University
`of Dortmund,
`Department of Statistics, Germany, 1page.*
`
`* cited by examiner
`
`Primary Examiner~ryan
`Bui
`(74) Attorney, Agent, or Firm-Noblitt & Gilmore, LLC.
`ABSTRACT
`(57)
`
`accord-
`A method and apparatus for testing semiconductors
`ing to various aspects of the present
`invention comprises
`a
`test
`system comprising
`an outlier
`identification
`element
`configured to identify significant data in a set of test results.
`The test system may be configured to provide the data in an
`output
`report. The outlier
`identification
`element
`suitably
`performs
`the analysis at run time. The outlier identification
`element may also operate in conjunction with a smoothing
`system to smooth the data and identify trends and departures
`from test result norms.
`
`20 Claims, 15 Drawing Sheets
`
`(22)
`
`(65)
`
`(63)
`
`(60)
`
`(51)
`(52)
`
`(58)
`
`IIIIIIIII I
`
`I
`I
`I
`I
`I
`I
`I
`I
`
`COMPONENTS
`
`:II
`
`:
`
`II
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
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`I
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`-----------------------~-------------,
`
`......
`
`-
`
`./
`
`100
`
`,I
`
`~ ;:..
`
`~7
`
`COMPUTER
`SYSTEM
`
`. ~10
`PROCESSOR A/
`_ ~12
`A/
`
`M~O~
`
`TESTER
`
`~04
`
`~--------~~
`
`DEVICE
`INTERFACE
`
`~-----------------------------------------
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 1 of 15
`
`US 6,792,373 B2
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`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 2 of 15
`
`US 6,792,373 B2
`
`0-
`
`02
`
`CONFIGURATION
`
`.h
`
`~r
`
`06
`
`Supplemental Data 0
`Analysis
`~----------------
`r3
`~----------------
`Scaling
`0
`
`10
`
`12
`
`Outlier
`Classification
`
`0
`
`08
`
`~ ,
`
`OUTPUT
`
`FIG.2
`
`

`
`u.s. Patent
`1iHl
`
`Sep.14,2004
`
`Sheet 3 of 15
`
`US 6,792,373 B2
`
`0°2
`
`START
`
`~Ir
`
`INITIALIZE
`
`~
`
`READ APPLICATION
`CONFIGURATION INFORMATION
`
`rJ
`
`04
`
`J06
`
`rJ°8
`
`Ir
`
`CONFIGURE SYSTEM
`
`GET TOOL
`IDENTIFICATION
`
`Ir
`END
`
`FIG. 3
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 4 of 15
`
`US 6,792,373 B2
`
`( START)
`
`COpy TESTER DATA FILE TO
`TOOL INPUT DIRECTORY
`
`READ LOGISTICS FROM TDF
`
`CREATE LOGISTICS INSTANCE
`WITH TOOL INFORMATION
`
`402
`
`404
`
`406
`
`LOOK UP TEST PROGRAM
`IDENTIFICATION IN MASTER DATABASE
`
`408
`
`YES
`
`CREATE TEST PROGRAM
`IDENTIFICATION AND ASSOCIATE
`WITH TOOL IDENTIFICATION
`
`GET WAFER TO
`ANALYZE INFORMATION
`
`412
`
`414
`
`FIG.4A
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 5 of 15
`
`US 6,792,373 B2
`
`418
`r./
`
`WAIT FOR NEXT WAFER
`
`NO
`
`420
`
`GET SECTION GROUP
`
`LOAD CONTROL LIMITS AND
`ENABLE FLAGS FOR TEST PROGRAM '
`FROM DATABASE
`
`422
`
`GET STATISTIC TYPES
`FROM SECTION GROUP
`
`MATCH SIGNATURE
`ANALYSIS ALGORITHMS
`
`MEMORY ALLOCATION
`
`423
`
`424
`
`426
`
`LOAD ALL RESULTS FOR ALL DIE
`TO DYNAMIC DATALOG FROM TDF
`
`428
`
`FIG. 48
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 6 of 15
`
`US 6,792,373 B2
`
`SMOOTH DATA
`
`CALCULATE STATISTICS
`
`SENSITIVITY CALIBRATION
`
`429
`
`430
`
`434
`
`432
`
`DEFINE OUTLIER THRESHOLDS
`
`COMPARE DATA TO
`OUTLIER THRESHOLDS
`
`438
`
`STORE STATISTICS AND OUTLIERS
`
`436
`
`440
`
`SIGNATURE ANALYSIS
`
`ASSIGN VALUE TO COMPONENT
`
`DATA CORRECTION
`
`442
`
`446
`
`444
`
`FIG.4C
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 7 of 15
`
`US 6,792,373 B2
`
`502
`
`FIG. 5
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 8 of 15
`
`US 6,792,373 B2
`
`GET POINT COUNT
`AND DIE COUNT
`
`602
`
`APPLY ALGORITHM TO
`SECTION DATA POINTS
`
`STORE TREND RESULTS
`AND SIGNATURE RESULTS
`
`604
`
`606
`
`NO
`
`NO
`
`NO
`
`FIG.6A
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 9 of 15
`
`US 6,792,373 B2
`
`RECORD ERRORLOG IN DATABASE
`
`RECORD TREND RESULTS IN
`DATABASE
`
`RECORD SIGNATURE RESULTS IN
`DATABASE
`
`614
`
`616
`
`618
`
`END
`
`FIG. 68
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 10 of 15
`
`US 6,792,373 B2
`
`(
`
`START )
`
`~
`
`READ SAMPLING RANGE
`
`READ OUTLIER INFORMATION
`
`rJO
`
`2
`
`r!/
`
`04
`
`,
`MERGE SAMPLING RANGE AND 0'
`
`06
`
`OUTLIER INFORMATION
`
`..
`STORE MERGED INFORMATION
`IN OUTPUT INFORMATION
`
`,
`
`CREATE OUTPUT REPORT
`
`~
`SEND OUTPUT REPORT
`TO DESTINATION
`
`0
`
`08
`
`0
`
`10
`
`712
`
`rJ
`
`iF
`END
`
`FIG. 7
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 11 of 15
`
`US 6,792,373 B2
`
`808
`
`GET NEXT R
`
`802
`
`YES
`
`BASIC SMOOTHING
`
`NO
`
`FIRST SUPPLEMENTARY SMOOTHING
`
`CALCULATE SLOPE
`
`NO
`
`SECOND SUPPLEMENTARY SMOOTHING
`
`FIG.8
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 12 of 15
`
`US 6,792,373 B2
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`u.s. Patent
`
`Sep.14,2004
`
`Sheet 13 of 15
`
`US 6,792,373 B2
`
`---
`
`9000
`
`11000
`
`RESISTIVITY PROFILE
`
`FIG. 10
`
`9000
`
`1100Q
`
`FIG. 11
`
`

`
`u.s. Patent
`
`Sep.14,2004
`
`Sheet 14 of 15
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`US 6,792,373 B2
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`Sep.14,2004
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`
`US 6,792,373 B2
`
`2
`resulting analysis cannot be fully complete and accurate. As
`a result, sampling degrades
`the complete understanding
`of
`the test results.
`In addition, acquiring the test data presents a complex and
`5 painstaking process. A test engineer prepares a test program
`to instruct
`the tester
`to generate
`the input signals
`to the
`component
`and receive
`the output
`signals. The program
`tends to be very complex to ensure full and proper operation
`of
`the component. Consequently,
`the test program for a
`10 moderately complex integrated circuit
`involves a large num-
`ber of tests and results. Preparing
`the program demands
`extensive design and modification to arrive at a satisfactory
`solution, and optimization
`of the program,
`for example to
`remove
`redundant
`tests or otherwise minimize
`test
`time,
`15 requires additional exertion.
`
`1
`FOR
`METHODS AND APPARATUS
`SEMICONDUCTOR
`TESTING
`
`TO RELATED
`CROSS-REFERENCES
`APPLICATIONS
`
`of U.S. patent
`This application is a continuation-in-part
`application Ser. No. 09/872,195,
`filed on May 31, 2001, now
`abandoned,
`entitled METHODS AND APPARATUS FOR
`DATA SMOOTHING,
`and claims the benefit of U.S. Pro-
`visional Patent Application No. 60/293,577,
`filed May 24,
`2001, entitled MEIRODS AND APPARATUS FOR DATA
`SMOOTHING; U.S. Provisional
`Patent Application No.
`60/295,188,
`filed May 31, 2001, entitled METHODS AND
`APPARATUS
`FOR TEST DATA CONTROL
`AND
`ANALYSIS;
`and U.S. Provisional Patent Application No.
`60/374,328,
`filed Apr. 21, 2002, entitled METHODS AND
`APPARATUS FOR TEST PROGRAM ANALYSIS AND
`ENHANCEMENT;
`and incorporates
`the disclosure of each
`application
`by reference. To the extent
`that
`the present
`disclosure
`conflicts with
`any referenced
`application,
`however,
`the present disclosure is to be given priority.
`
`FIELD OF THE INVENTION
`
`The invention relates to semiconductor
`
`testing.
`
`SUMMARY OF IRE INVENTION
`A method
`and apparatus
`for
`testing
`semiconductors
`according to various aspects of the present
`invention com-
`prises
`a test system comprising
`an outlier
`identification
`element configured to identify significant data in a set of test
`results. The test system may be configured to provide the
`data in an output
`report. The outlier
`identification element
`suitably
`performs
`the analysis
`at
`run time. The outlier
`identification element may also operate in conjunction with
`a smoothing system to smooth the data and identify trends
`and departures
`from test result norms.
`
`for operating the
`
`BRIEF DESCRIPTION OF THE DRAWING
`A more complete understanding
`of the present
`invention
`may be derived by referring to the detailed description and
`the claims when considered in connection with the following
`illustrative
`figures, which may not be to scale. Like refer-
`ence numbers
`refer
`to similar
`elements
`throughout
`the
`figures.
`FIG. 1 is a block diagram of a test system according to
`various
`aspects of
`the present
`invention
`and associated
`functional components;
`FIG. 2 is a block diagram of elements
`test system;
`FIG. 3 illustrates a flow chart for a configuration element;
`FIGS. 4A-C illustrate a flow chart for a supplemental data
`analysis element;
`FIG. 5 is a diagram of various sections of a wafer;
`FIGS. 6A-B further
`illustrate a flow chart for a supple-
`mental data analysis element;
`FIG. 7 illustrates a flow chart for an output element;
`FIG. 8 is a flow chart for operation of an exemplary data
`smoothing
`system according
`to various
`aspects
`of
`the
`present
`invention;
`FIG. 9 is a plot of
`components;
`of a wafer having multiple
`FIG. 10 is a representation
`devices and a resistivity profile for the wafer;
`FIG. 11 is a graph of resistance values for a population of
`resistors in the various devices of the wafer of FIG. 10; and
`FIGS. 12A-B are general and detailed plots, respectively,
`of raw test data and smoothed
`test data for
`the various
`devices of FIG. 10.
`Elements
`in the figures are illustrated for simplicity and
`clarity and have not necessarily been drawn to scale. For
`example,
`the connections
`and steps performed by some of
`the elements
`in the figures may be exaggerated or omitted
`relative to other elements to help to improve understanding
`of embodiments
`of the present
`invention.
`
`test data for a test of multiple
`
`20
`
`25
`
`30
`
`35
`
`BACKGROUND OF THE INVENTION
`Semiconductor
`companies
`test components
`to ensure that
`the components
`operate properly. The test data not only
`determine whether
`the components
`function properly, but
`also may indicate deficiencies in the manufacturing process.
`Accordingly, many semiconductor
`companies may analyze
`the collected
`data from several different
`components
`to
`identify problems and correct
`them. For example,
`the com-
`pany may gather test data for multiple chips on each wafer
`among several different
`lots. This data may be analyzed to
`identify
`common
`deficiencies
`or patterns
`of defects
`or
`identify parts
`that may exhibit quality and performance
`issues and to identify or classify user-defined "good parts".
`Steps may then be taken to correct
`the problems. Testing is 40
`typically performed before device packaging (at wafer level)
`as well as upon completion of assembly (final
`test).
`Gathering and analyzing test data is expensive
`and time
`consuming. Automatic
`testers apply signals to the compo-
`nents and read the corresponding output signals. The output
`signals may be analyzed to determine whether
`the compo-
`nent
`is operating properly. Each tester generates
`a large
`volume of data. For example, each tester may perform 200
`tests on a single component,
`and each of those tests may be 50
`repeated 10 times. Consequently,
`a test of a single compo-
`nent may yield 2000 results. Because each tester is testing
`100 or more components
`an hour and several
`testers may be
`connected to the same server, an enormous amount of data
`must be stored. Further,
`to process
`the data,
`the server
`typically stores the test data in a database to facilitate the
`manipulation and analysis of the data. Storage in a conven-
`tional database, however,
`requires
`further storage capacity
`as well as time to organize and store the data.
`The analysis of the gathered data is also difficult. The
`volume
`of
`the data may demand
`significant
`processing
`power and time. As a result,
`the data is not usually analyzed
`at product
`run time, but
`is instead
`typically
`analyzed
`between test runs or in other batches.
`To alleviate some of these burdens, some companies only 65
`sample
`the data from the testers
`and discard
`the rest.
`Analyzing less than all of the data, however, ensures that the
`
`45
`
`55
`
`60
`
`

`
`US 6,792,373 B2
`
`3
`DETAILED DESCRIPTION OF AN
`EXEMPLARY EMBODIMENT
`in terms of
`The present
`invention may be described
`functional
`block components
`and various process
`steps.
`Such functional blocks and steps may be realized by any
`number of hardware or software components
`configured to
`perform the specified functions. For example,
`the present
`invention may employ various
`testers, processors,
`storage
`systems, processes, and integrated circuit components,
`e.g.,
`statistical
`engines, memory
`elements,
`signal processing
`elements,
`logic elements, programs, and the like, which may
`carry out a variety of functions under the control of one or
`more testers, microprocessors,
`or other control devices.
`In
`addition,
`the present
`invention may be practiced in conjunc-
`tion with any number of test environments,
`and each system
`described is merely one exemplary application for the inven-
`tion. Further,
`the present
`invention may employ any number
`of conventional
`techniques
`for data analysis,
`component
`interfacing, data processing,
`component handling,
`and the
`like.
`Referring to FIG. 1, a method and apparatus according to
`various aspects of the present
`invention operate in conjunc-
`tion with a test system 100 having a tester 102, such as
`automatic test equipment
`(ATE) for testing semiconductors.
`the test system 100 comprises a
`In the present embodiment,
`tester 102 and a computer
`system 108. The test system 100
`may be configured for testing any components 106, such as
`semiconductor
`devices on a wafer, circuit boards, packaged
`devices, or other electrical or optical systems.
`In the present
`106 comprise multiple inte-
`embodiment,
`the components
`grated circuit dies formed on a wafer or packaged integrated
`circuits or devices.
`The tester 102 suitably comprises any test equipment
`that
`tests components 106 and generates output data relating to
`the testing. The tester 102 may comprise
`a conventional
`automatic
`tester,
`such as a Teradyne
`tester, and suitably
`operates in conjunction with other equipment
`for facilitating
`the testing. The tester 102 may be selected and configured
`106 to be tested
`according
`to the particular
`components
`and/or any other appropriate
`criteria.
`The tester 102 may operate
`in conjunction with the
`system 108 to, for example, program the tester
`computer
`102,
`load and/or execute
`the test program,
`collect data,
`to the tester 102, implement a statistical
`provide instructions
`engine, control
`tester parameters,
`and the like. In the present
`system 108 receives tester data
`embodiment,
`the computer
`from the tester 102 and performs
`various data analysis
`functions
`independently
`of the tester 102. The computer
`system 108 also implements
`a statistical engine to analyze
`system 108 may
`data from the tester 102. The computer
`comprise a separate computer, such as a personal computer
`or workstation,
`connected to or networked with the tester
`102 to exchange signals with the tester 102. In an alternative
`the computer system 108 may be omitted from
`embodiment,
`or integrated into other components of the test system 100
`and various
`functions
`may
`be performed
`by other
`components,
`such as the tester 102.
`The computer system 108 includes a processor 110 and a
`110 comprises
`memory
`112. The processor
`any suitable
`processor,
`such as a conventional
`Intel, Motorola,
`or
`Advanced Micro Devices processor, operating in conjunc-
`tion with any suitable operating system, such as Windows
`the memory 112
`98, Windows NT, Unix, or Linux. Similarly,
`may comprise
`any appropriate memory accessible
`to the
`processor 110, such as a random access memory (RAM) or
`other suitable storage system,
`for storing data. In particular,
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`the memory 112 of the present system includes a fast access
`memory for storing and receiving information
`and is suit-
`ably configured with sufficient
`capacity to facilitate
`the
`operation of the computer 108.
`112 includes
`the memory
`In the present
`embodiment,
`capacity for storing output
`results received from the tester
`102 and facilitating
`analysis of the output
`test data. The
`memory 112 is configured for fast storage and retrieval of
`test data for analysis. The memory 112 is suitably configured
`suitably com-
`10 to store the elements of a dynamic datalog,
`prising a set of information selected by the test system 100
`and/or the operator according to selected criteria and analy-
`sis based on the test results.
`the memory 112 suitably stores a compo-
`For example,
`for each component 106, such as x-y coor-
`identifier
`15 nent
`dinates corresponding to a position of the component 106 on
`a wafer map for the tested wafer. Each x-y coordinate in the
`memory 112 may be associated with a particular component
`106 at the corresponding
`x-y coordinate on the wafer map.
`identifier has one or more fields, and each
`20 Each component
`field corresponds,
`for example,
`to a particular
`test performed
`on the component 106 at the corresponding x-y position on
`the wafer, a statistic related to the corresponding component
`106, or other
`112 may be
`relevant
`data. The memory
`to include
`25 configured
`any data identified by the user as
`desired according to any criteria or rules.
`The computer 108 of the present embodiment
`also suit-
`ably has access to a storage system, such as another memory
`30 (or a portion of the memory 112), a hard drive array, an
`optical storage system, or other suitable storage system. The
`storage system may be local,
`like a hard drive dedicated to
`the computer 108 or the tester 102, or may be remote, such
`as a hard drive array associated with a server to which the
`test system 100 is connected. The storage system may store
`and/or data used by the computer 108 or other
`programs
`components
`of
`the
`test
`system 100.
`In the present
`a database 114
`embodiment,
`the storage system comprises
`available via a remote server 116 comprising,
`for example,
`for a manufacturing
`40 a main production server
`facility. The
`database 114 stores tester
`information,
`such as tester data
`files, master data files for operating the test system 100 and
`its components,
`test programs,
`downloadable
`instructions
`for the test system 100, and the like.
`The test system 100 may include additional equipment
`to
`the
`facilitate testing of the components
`106. For example,
`test system 100 includes a device interface 104, like
`present
`a conventional device interface board and/or a device han-
`to handle the components 106 and provide an
`dler or prober,
`106 and the tester 102.
`interface between the components
`The test system 100 may include or be connected to other
`components,
`equipment,
`software, and the like to facilitate
`106 according to the particular
`testing of the components
`configuration,
`application,
`environment
`of the test system
`55 100, or other relevant
`factors. For example,
`in the present
`the test system 100 is connected to an appro-
`embodiment,
`priate communication medium, such as a local area network,
`intranet, or global network like the internet,
`to transmit
`information to other systems, such as the remote server 116.
`The test system 100 may include one or more testers 102
`and one or more computers 108. For example, one computer
`108 may be connected to an appropriate number of, such as
`testers 102 according
`up to twenty or more,
`to various
`factors, such as the system's
`throughput
`and the configura-
`the computer 108 may be
`tion of the computer 108. Further,
`separate from the tester 102, or may be integrated into the
`tester 102, for example utilizing one or more processors,
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`memories, clock circuits, and the like of the tester 102 itself.
`In addition, various functions may be performed by different
`computers.
`For example,
`a first computer may perform
`various
`pre-analysis
`tasks,
`several
`computers may then
`receive the data and perform data analysis, and another set
`of computers may prepare the dynamic datalogs and/or other
`output
`reports.
`aspects of the
`A test system 100 according to various
`present
`invention tests the components
`106 and provides
`enhanced analysis and test results. For example,
`the supple-
`mental
`analysis may identify incorrect,
`questionable,
`or
`unusual
`results, repetitive tests, and/or tests with a relatively
`high probability of failure. The operator, such as the product
`engineer,
`test engineer, manufacturing
`engineer,
`device
`engineer, or other personnel using the test data, may then use
`the results to verify and/or improve the test system 100 and
`classify components 106.
`The test system 100 according to various aspects of the
`present
`invention
`executes
`an enhanced
`test process
`for
`testing the components 106 and collecting and analyzing test
`data. The test system 100 suitably operates
`in conjunction
`with a software application executed by the computer 108.
`Referring to FIG. 2, the software application of the present
`embodiment
`includes multiple elements
`for implementing
`the enhanced test process,
`including a configuration element
`202, a supplementary
`data analysis
`element 206, and an
`output element 208. Each element 202, 206, 208 suitably
`comprises a software module operating on the computer 108
`to perform various
`tasks. Generally,
`the configuration
`ele-
`ment 202 prepares
`the test system 100 for
`testing and
`analysis.
`In the supplementary
`data analysis element 206,
`output
`test data from the tester 102 is analyzed to generate
`supplementary
`test data, suitably at run time and automati-
`cally. The supplementary
`test data is then transmitted to the
`operator or another system by the output element 208.
`The configuration element 202 configures the test system
`100 for testing the components
`106 and analyzing the test
`data. The test system 100 suitably uses a predetermined
`set
`of initial parameters
`and,
`if desired,
`information
`from the 40
`operator
`to configure the test system 100. The test system
`100 is suitably initially configured with predetermined
`or
`default parameters
`to minimize operator attendance
`to the
`test system 100. Adjustments may be made to the configu-
`ration by the operator,
`if desired,
`for example
`via the 45
`computer 108.
`Referring to FIG. 3, an exemplary configuration process
`300 performed by the configuration element 202 begins with
`an initialization procedure (step 302) to set the computer 108
`in an initial
`state. The configuration
`element
`202 then 50
`obtains application configuration information (step 304), for
`example from the database 114, for the computer 108 and
`the tester 102. For example,
`the configuration element 202
`may access a master configuration file for the enhanced test
`process and/or a tool configuration file relating to the tester
`102. The master configuration file may contain data relating
`to the proper configuration for the computer 108 and other
`components of the test system 100 to execute the enhanced
`test process. Similarly,
`the tool configuration
`file suitably
`includes data relating to the tester 102 configuration,
`such as
`connection, directory,
`IP address,
`tester node identification,
`manufacturer,
`flags, prober
`identification, or any other per-
`tinent
`information for the tester 102.
`The configuration element 202 may then configure the test
`system 100 according to the data contained in the master
`configuration
`file and/or
`the tool configuration
`file (step
`306). In addition,
`the configuration element 202 may use the
`
`6
`information
`relevant
`data to retrieve further
`configuration
`from the database 114, such as the tester's
`102 identifier
`(step 308)
`for associating data like logistics
`instances
`for
`tester data with the tester 102. The test system 100 infor-
`5 mation also suitably includes one or more default parameters
`that may be accepted, declined, or adjusted by the operator.
`For example,
`the test system 100 information may include
`global statistical process control
`(SPC) rules and goals that
`are
`submitted
`to the
`operator
`upon
`installation,
`for
`10 configuration,
`power-up,
`or other
`appropriate
`time
`approval and/or modification. The test system 100 informa-
`tion may also include default wafer maps or other files that
`are suitably configured for each product, wafer, component
`106, or other item that may affect or be affected by the test
`algorithms, parameters,
`and
`15 system 100. The configuration
`any other criteria may be stored in a recipe file for easy
`access, correlation to specific products and/or tests, and for
`traceability.
`the
`is complete,
`process
`When the initial configuration
`in
`for example
`test system 100 commences
`a test
`run,
`conjunction with a conventional
`series of tests,
`in accor-
`dance with a test program. The tester 102 suitably executes
`the test program to apply signals
`to connections
`on the
`components 106 and read output
`test data from the compo-
`25 nents 106. The tester 102 may perform multiple tests on each
`component 106 on a wafer, and each test may be repeated
`several
`times on the same component 106. Test data from the
`tester 102 is stored for quick access
`and supplemental
`analysis as the test data is acquired. The data may also be
`analysis and
`30 stored in a long-term memory for subsequent
`use.
`Each test generates at least one result for at least one of
`the components. Referring to FIG. 9, an exemplary set of
`test results for a single test of multiple components
`com-
`prises a first set of test results having statistically similar
`values
`and a second set of
`test
`results
`characterized
`by
`values that stray from the first set. Each test result may be
`limit. If a
`compared to an upper
`test limit and a lower test
`particular
`result
`for a component
`exceeds either
`limit,
`the
`component may be classified as a "bad part".
`Some of the test results in the second set that stray from
`the first set may exceed the control
`limits, while others do
`not. For the present purposes,
`those test results that stray
`from the first set but do not exceed the control
`limits or
`otherwise fail to be detected are referred to as "outliers". The
`outliers in the test results may be identified and analyzed for
`any appropriate
`purpose,
`such as to identify potentially
`unreliable
`components. The outliers may also be used to
`identify various potential problems and/or improvements
`in
`the test and manufacturing
`processes.
`test
`the output
`As the tester 102 generates the test results,
`data for each component,
`test, and repetition is stored by the
`tester 102 in a tester data file. The output
`test data received
`from each component 106 is analyzed by the tester 102 to
`classify the performance of the component 106, for example
`by comparison
`to the upper and lower
`test
`limits, and the
`results of the classification are also stored in the tester data
`file. The tester data file may include additional
`information
`as well, such as logistics data and test program identification
`data. The tester data file is then provided to the computer 108
`in an output
`file, such as a standard tester data format
`(STDF)
`file, and stored in memory.
`the tester data file, the
`When the computer 108 receives
`supplementary
`data analysis element 206 analyzes the data
`to provide enhanced output results. The supplementary
`data
`analysis element 206 may provide any appropriate
`analysis
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`any suitable objective. For
`the tester data to achieve
`of
`example,
`the supplementary
`data analysis element 206 may
`implement
`a statistical engine for analyzing the output
`test
`data at run time and identifying data and characteristics
`of
`the data of interest
`to the operator. The data and character-
`istics identified may be stored, while data that
`is not iden-
`tified may be otherwise disposed of, such as discarded.
`The supplementary
`data analysis element 206 may, for
`example,
`calculate statistical
`figures according to the data
`and a set of statistical
`configuration
`data. The statistical
`configuration data may call for any suitable type of analysis
`according to the needs of the test system 100 and/or
`the
`operator, such as statistical process control, outlier identifi-
`cation and classification,
`signature analysis, and data corre-
`lation. Further,
`the supplementary data analysis element 206 15
`suitably performs
`the analysis
`at run time,
`i.e., within a
`matter of seconds or minutes following generation of the test
`data. The supplementary data analysis element 206 may also
`perform the analysis automatically with minimal
`interven-
`tion from the operator and/or test engineer.
`In the present
`test system 100, after the computer 108
`receives
`and stores the tester data file,
`the supplementary
`data analysis
`element 206 performs
`various preliminary
`tasks to prepare the computer 108 for analysis of the output
`test data and facilitate generation of supplementary
`data and 25
`preparation
`of an output
`report. Referring now to FIGS.
`4A-C,
`in the present embodiment,
`the supplementary
`data
`analysis element 206 initially copies the tester data file to a
`tool input directory corresponding to the relevant
`tester 102
`(step 402). The supplementary
`data analysis element 206 30
`also retrieves configuration data to prepare the computer 108
`for supplementary
`analysis of the output
`test data.
`The configuration data suitably includes a set of logistics
`data that may be retrieved from the tester data file (step 404).
`The supplementary
`data analysis element 206 also creates a 35
`logistics
`reference (step 406). The logistics
`reference may
`include tester 102 information,
`such as the tester 102 infor-
`mation derived from the tool configuration file. In addition,
`the logistics reference is assigned an identification.
`for
`The configuration data may also include an identifier
`the test program that generated the output
`test data. The test
`program may be identified in any suitable manner, such as
`looking it up in the database 114 (step 408), by association
`with the tester 102 identification,
`or reading it from the 45
`master configuration
`file. If no test program identification
`can be established (step 410), a test program identification
`may be created and associated with the tester identification
`(step 412).
`The configuration data further identifies the wafers in the 50
`test run to be processed by the supplementary
`data analysis
`element 206,
`if fewer than all of the wafers.
`In the present
`embodiment,
`the supplementary
`data analysis element 206
`accesses a file indicating which wafers are to be analyzed
`(step 414).
`If no indication is provided,
`the computer 108 55
`suitably defaults to analyzing all of the wafers in the test run.
`If the wafer for the current
`test data file is to be analyzed
`(step 416),
`the supplementary
`data analysis
`element 206
`proceeds with performing the supplementary
`data analysis
`on the test data file for the wafer. Otherwise,
`the supple-
`mentary data analysis element 206 waits for or accesses the
`next
`test data file (step 418).
`The supplementary
`data analysis element 206 may estab-
`lish one or more section groups
`to be analyzed for
`the
`various wafers
`to be tested (step 420). To identify the 65
`appropriate section group to apply to the output test data, the
`supplementary
`data analysis element 206 suitably identifies
`
`8
`for example accord-
`an appropriate section group definition,
`ing to the test program and/or the tester identification. Each
`section group includes one or more section arrays, and each
`section array includes one or more sections of the same
`section types.
`sorts of component 106
`Section types comprise various
`areas of the wafer. For
`groups positioned in predetermined
`example,
`referring to FIG. 5, a section type may include a
`row 502, a column 504, a stepper
`field 506, a circular band
`508, a radial zone 510, a quadrant 512, or any other desired
`grouping of components. Different
`section types may be
`used according to the configuration of the components,
`such
`as order of components processed,
`s