Patent No. 6,792,373
`Petition For Inter Partes Review
`
`
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Attorney Docket No.:
`002445-0079-651
`Customer No.: 28120
`
`Petitioner: Linear Technology
`Corporation
`
`§§§§§§§
`
`United States Patent No.: 6,792,373
`Inventor: Eric Paul Tabor
`Formerly Application No.: 10/154,627
`Issue Date: September 14, 2004
`Filing Date: May 24, 2002
`Former Group Art Unit: 2863
`Former Examiner: Bryan Bui
`
`
`For: METHODS AND APPARATUS FOR SEMICONDUCTOR TESTING
`
`MAIL STOP PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`Post Office Box 1450
`Alexandria, Virginia 22313-1450
`
`
`PETITION FOR INTER PARTES REVIEW OF
`
`UNITED STATES PATENT NO. 6,792,373
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`

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`Patent No. 6,792,373
`Petition For Inter Partes Review
`TABLE OF CONTENTS
`
`Page No.
`
`INTRODUCTORY STATEMENT ............................................................................. 1 
`MANDATORY NOTICE OF EACH REAL-PARTY-IN-INTEREST ...................... 1 
`MANDATORY NOTICE OF RELATED MATTERS ............................................... 1 
`MANDATORY NOTICE OF LEAD AND BACKUP COUNSEL ........................... 2 
`MANDATORY NOTICE OF SERVICE INFORMATION ....................................... 2 
`GROUNDS FOR STANDING .................................................................................... 2 
`STATEMENT OF PRECISE RELIEF REQUESTED ................................................ 3 
`THRESHOLD REQUIREMENT FOR INTER PARTES REVIEW .......................... 3 
`I. 
`INTRODUCTION ............................................................................................. 4 
`A.  Declaration of Dr. Jacob A. Abraham ....................................................... 4 
`B.  Relevant Timeframe ................................................................................... 4 
`C.  Technology Background ............................................................................ 4 
`THE ’373 PATENT ........................................................................................... 7 
`II. 
`III.  OVERVIEW OF THE PRIOR ART ................................................................. 10 
`A.  The Sun Patent ......................................................................................... 10 
`B.  The Madge Patent .................................................................................... 12 
`C.  The O’Donoghue Patent .......................................................................... 15 
`D.  The Friedman Patent ................................................................................ 18 
`IV.  OVERVIEW OF THE CLAIMS AND THEIR DEPENDENCIES ................. 19 
`V. 
`THE PERSON OF ORDINARY SKILL IN THE ART ................................... 21 
`VI.  CONSTRUCTION OF THE CLAIMS ............................................................. 21 
`A.  “outlier” .................................................................................................... 22 
`B.  “outlier identification element” ............................................................... 24 
`C.  “component” ............................................................................................ 24 
`D.  “semiconductor” ...................................................................................... 25 
`E.  “output report” ......................................................................................... 25 
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`F.  “section group of components on a wafer” .............................................. 26 
`G.  “recipe file” .............................................................................................. 26 
`H.  “correlate/correlating the test data” ......................................................... 26 
`I.  “identify the outlier at run time” .............................................................. 27 
`J.  “automatically calibrate a sensitivity … to the test data” ........................ 27 
`K.  “data smoothing element configured to receive the test data and smooth
`the test data” ........................................................................................ 27 
`VII.  CLAIM-BY-CLAIM EXPLANATION OF GROUNDS FOR
`UNPATENTABILITY................................................................................................. 28 
`Ground 1.  Claims 1, 2, 4, 5, 7-9, 11, 12, and 14 are anticipated under 35
`U.S.C. § 102 by U.S. Patent No. 6,240,329 (“Sun”). ........................................ 28 
`a. 
`Sun Anticipates Independent Claims 1 and 8 ............................... 28 
`b. 
`Sun Anticipates Dependent Claims 2, 4, 5, 7, 9, 12, and 14 ........ 32 
`Ground 2.  Claims 6, 13, 15, 16, and 18-20 are rendered obvious by Sun in
`view of O’Donoghue. ........................................................................................ 37 
`a. 
`One of skill in the art would have been motivated to combine
`Sun and O’Donoghue. ............................................................................. 37 
`b. 
`Sun, in combination with O’Donoghue, renders Claims 6, 13,
`15-16, and 18-20 obvious ........................................................................ 40 
`Ground 3.  Claims 3 and 10 are rendered obvious by Sun in view of U.S.
`Patent No. 5,240,866 to Friedman (“Friedman”). ............................................. 43 
`a. 
`One of skill in the art would have been motivated to combine
`Sun and Friedman. ................................................................................... 43 
`b. 
`Claims 3 and 10 are obvious over Sun in view of Friedman. ....... 44 
`Ground 4.  Claims 1-5, 7-12, and 14 are anticipated under 35 U.S.C. § 102
`by U.S. Patent No. 6,598,194, to Madge et al. (“Madge”). ............................... 45 
`a.  Madge anticipates independent claims 1 and 8. ........................... 45 
`Ground 5.  Claims 6, 13, and 15-20 are rendered obvious by Madge in
`view of U.S. Patent No. 5,497,381 to O’Donoghue et al. (“O’Donoghue”). .... 54 
`a. 
`One of skill in the art would have been motivated to combine
`Madge and O’Donoghue ......................................................................... 54 
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`b.  Madge, in combination with O’Donoghue, renders Claims 6,
`13, and 15-20 obvious ............................................................................. 57 
`CONCLUSION ............................................................................................................
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`60 
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`iii
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`TABLE OF AUTHORITIES
`
`
`CASES
`
`Page(s)
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`KSR Int'l Co. v. Teleflex, Inc.,
`550 U.S. 398 (2007) ................................................................................ 40, 44, 57
`
`SRI Int'l v. Matsushita Elec. Corp.,
`775 F.2d 1107 (Fed. Cir. 1985) (en banc) .......................................................... 23
`
`In re Zletz,
`893 F.2d 319 (Fed. Cir. 1989) ............................................................................ 22
`
`
`
`STATUTES
`
`35 U.S.C. § 102 .............................................................................................. 3, 29, 45
`
`35 U.S.C. § 314(a) ..................................................................................................... 4
`
`OTHER AUTHORITIES
`
`37 C.F.R. § 42.100(b) .............................................................................................. 22
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`iv
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`TABLE OF EXHIBITS
`
`Exhibit No.
`
`Exhibit Title
`
`1001
`
`1002
`
`1003
`
`U.S. Patent No. 6,792,373 to Tabor
`
`Declaration of Dr. Jacob Abraham
`
`Curriculum Vitae of Dr. Jacob Abraham
`
`1006
`
`1007
`
`1008
`
`1004 W. Ponik, “Teradyne's J957 VLSI Test System: Getting VLSI to the
`Market on Time,” IEEE DESIGN & TEST, December 1985, pp.
`57-62
`1005 W. Robert Daasch, Variance Reduction Using Wafer Patterns in
`IddQ Data, in International Test Conference 2000 Proceedings, at
`pages 189-198 (Oct. 3, 2000)
`A. Rao, A.P. Jayasumana, and Y.K. Malaiya, Optimal Clustering
`and Statistical Identification of Defective IC’s using IDDQ Test-
`ing, Defect Based Testing, 2000, Proceedings (IEEE), 30-35 (Apr.
`30, 2000)
`Automotive Electronics Council, “Guidelines for Part Average
`Testing,” AEC - Q001-Rev A, October 8, 1998
`Diane K. Michelson, Statistically Calculating Reject Limits at
`Parametric Test, 1997 IEEE/CPMT International Electronics
`Manufacturing Technology Symposium, pp. 172-177
`C. Michael Whitney and Leslie Fowler, Motorola's Engineering
`Data Analysis System: 10 Years of Analytical Techniques, Pro-
`ceedings of the Twenty-Fifth Annual SAS User's Group Interna-
`tional Conference, April 9-12, 2000, paper 44-25
`
`1009
`
`
`
`v
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`Exhibit No.
`
`Exhibit Title
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`Robert Trahan and Kevin Dean, A Comprehensive I.C. Yield Anal-
`ysis System in RS1, 1990 IEEE/SEMI Advanced Manufacturing
`Conference, pp. 99-103
`U.S. Patent No. 6,240,329 to Sun
`
`U.S. Patent No. 6,598,194 to Madge et al.
`
`U.S. Patent No. 5,497,381 to O’Donoghue et al.
`
`U.S. Patent No. 5,240,866 to Friedman et al.
`
`U.S. Patent No. 6,366,108 to O’Neill
`
`IEEE, The Authoritative Dictionary of IEEE Standards Terms (7th
`Ed. 2000)
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`vi
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`INTRODUCTORY STATEMENT
`
`Linear Technology Corporation (“Linear”) petitions for inter partes review
`
`of U.S. Patent 6,792,373 (“the’373 Patent”). The ’373 patent is the subject of a
`
`nearly identical petition filed by a different petitioner, Maxim Integrated Products
`
`Inc., in IPR2015-01627 (“Maxim Petition”). The only substantive difference in this
`
`petition is that the discussion regarding construction of “outlier” now reflects a
`
`construction of that term by the Board in connection with a decision denying an
`
`earlier Linear petition for inter partes review, IPR2015-00421. The sections on
`
`Real Party-In-Interest, Related Matters, and Counsel also have been appropriately
`
`updated. The Board has not yet determined whether to grant the Maxim Petition.
`
`As explained below, there is a reasonable likelihood that Linear will prevail
`
`in demonstrating unpatentability with respect to at least one of the Challenged
`
`Claims based on this petition. Linear respectfully submits that an inter partes re-
`
`view should be instituted, and that the Challenged Claims should be canceled as
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`unpatentable.
`
`MANDATORY NOTICE OF EACH REAL-PARTY-IN-INTEREST
`
`Linear Technology Corporation is the real party-in-interest.
`
`MANDATORY NOTICE OF RELATED MATTERS
`
`The ’373 Patent is owned by a Patent Assertion Entity, which has asserted it
`
`in five co-pending litigations: In-Depth Test LLC v. Intersil Corp., Case No. 1-14-
`
`
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`1
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`

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`Patent No. 6,792,373
`Petition For Inter Partes Review
`cv-00886 (D. Del. Jul. 8, 2014); In-Depth Test LLC v. Maxim Integrated Prods.,
`
`Inc., Case No. 1-14-cv-00887 (D. Del. Jul. 8, 2014); In-Depth Test LLC v. Vishay
`
`Inter-technology, Inc., Case No. 1-14-cv-00888 (D. Del. Jul. 8, 2014); In-Depth
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`Test LLC v. Fairchild Semiconductor Corp., Case No. 1-14-cv-01090 (D. Del.
`
`Aug. 22, 2014); In-Depth Test LLC v. Linear Tech. Corp., Case No. 1-14-cv-01091
`
`(D. Del. Aug. 22, 2014). The ’373 Patent had also been asserted in the U.S. District
`
`Court for the District of Arizona in case 2-05-cv-03392, filed on Oct. 25, 2005.
`
`The ’373 Patent is the subject of the following Petitions for Inter Partes Re-
`
`view: IPR2015-00421, IPR2015-01627. It also is the subject of the Petition for
`
`Covered Business Method Review with Case No. CBM2015-00060.
`
`MANDATORY NOTICE OF LEAD AND BACKUP COUNSEL
`
`Lead Counsel: J. Steven Baughman (Reg. No 47,414); Tel: 202-508-4600
`
`Backup Counsel: Mark Rowland (Reg. No. 32,077); Tel: 650-617-4000
`
`Mailing Address For All PTAB Correspondence: Ropes & Gray LLP, IPRM –
`
`Floor, 43, Prudential Tower, 800 Boylston Street, Boston, MA 02199-3600.
`
`MANDATORY NOTICE OF SERVICE INFORMATION
`
`Please address all correspondence to lead counsel at the address above.
`
`GROUNDS FOR STANDING
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`Petitioner certifies that the ’373 Patent is available for inter partes review
`
`and that Petitioner is not barred or estopped from requesting an inter partes review
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`challenging the patent claims on the grounds identified herein.
`
`STATEMENT OF PRECISE RELIEF REQUESTED
`
`The Petitioner requests that claims 1-20 of U.S. Patent No. 6,792,373 (“the
`
`’373 Patent”) (Ex. 1001) be canceled based on the following grounds of unpatenta-
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`bility:
`
`Ground 1. Claims 1, 2, 4, 5, 7, 8, 9, 12, and 14 are anticipated under 35
`
`U.S.C. § 102 by U.S. Patent No. 6,240,329 (“Sun”).
`
`Ground 2. Claims 6, 13, 15, 16, and 18-20 are rendered obvious by Sun in
`
`view of U.S. Patent No. 5,497,381 to O’Donoghue et al. (“O’Donoghue”).
`
`Ground 3. Claims 3 and 10 are rendered obvious by Sun in view of U.S. Pa-
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`tent No. 5,240,866 to Friedman (“Friedman”).
`
`Ground 4. Claims 1-5, 7-12, and 14 are anticipated under 35 U.S.C. § 102
`
`by U.S. Patent No. 6,598,194, to Madge et al. (“Madge”).
`
`Ground 5. Claims 6, 13, and 15-20 are rendered obvious by Madge in view
`
`of O’Donoghue.
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`THRESHOLD REQUIREMENT FOR INTER PARTES REVIEW
`
`A petition for inter partes review must demonstrate “a reasonable likelihood
`
`that the Petitioner would prevail with respect to at least one of the claims chal-
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`lenged in the petition.” 35 U.S.C. § 314(a). The current Petition meets this thresh-
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`old. Sun and Madge anticipate, or render obvious when combined with
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`O’Donoghue or Friedman, every claim of the ’373 Patent.
`
`I.
`
`INTRODUCTION
`
`A. Declaration of Dr. Jacob A. Abraham
`
`The declaration of Dr. Jacob A. Abraham is attached as Exhibit 1002.
`
`B. Relevant Timeframe
`
`The earliest possible filing date worldwide for the application leading to the
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`’373 Patent is May 24, 2001. (Ex. 1001, Face Sheet.) The period directly preceding
`
`May 24, 2001 is referred to here as the “relevant time frame.” (Ex. 1002 ¶ 28).
`
`C.
`
`Technology Background
`
`The ’373 Patent pertains broadly to the field of semiconductor testing. The
`
`’373 Patent concerns the characterization of wafer and chip test results to deter-
`
`mine whether the part is defective, good, or in a range in between. (Ex. 1002 ¶ 36.)
`
`In the relevant time frame, semiconductor manufacturers tested wafers and
`
`wafer-based devices at different stages of the manufacturing process. Tests includ-
`
`ed wafer electrical tests, completed integrated circuit (“IC”) probe tests, and pack-
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`aged IC final tests. (Id. ¶ 37.)
`
`One focus of the ’373 patent concerns the ability of semiconductor test
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`equipment to process data. The ’373 Patent discloses that data manipulation tech-
`
`niques are to be used in conjunction with a tester and a computer. The tester is de-
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`scribed as “automatic test equipment (ATE)” or “any test equipment that tests
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`components 106 and generates output data.” (Ex. 1001 at 3:24-37.) The specifica-
`
`tion refers to a “Teradyne tester” as an example of such an ATE. (Id. at 3:37.) The
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`tester is described as operating in connection with a “computer system 108 that re-
`
`ceives tester data from the tester.” (Id. at 3:42-49.)
`
`In the relevant time frame, semiconductor manufacturers used ATE that had
`
`extensive data processing capability. For example, one of the Teradyne systems re-
`
`ferred to in the ’373 patent, the Teradyne J957 contained both a test system com-
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`puter and a user computer. (See Ponik, Ex. 1004.) The computer allowed a user to
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`design tests protocols for the semiconductor devices. The computer also manipu-
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`lated test data, and allowed its communication to other systems. The Teradyne
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`J957 could accumulate test data from tests run on a series of devices, and calculate
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`statistics on that test data, including the number of times the test had occurred,
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`minimum and maximum parameter values and the difference between them, and
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`the mean, mode, and median parameter values. (Ex. 1002 ¶ 38)
`
`In the late 1990s, the semiconductor industry focused on increasing yield
`
`and decreasing testing time. Engineers sought ways to identify manufacturing pro-
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`cess defects earlier in the process, before die were cut and packaged. They also
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`sought ways to classify the likelihood of a given chip failing. Much of this work
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`was predictive, using statistical analyses to determine root causes of defects and
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`identify chips to forego additional testing or extensive burn-ins. (Id. ¶ 39.)
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`Techniques were developed to increase yield. For example, it was known
`
`that there could be differences in expected test results (i.e., parametric test varia-
`
`tions) between wafers in a lot or between different lots. It was understood that
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`these variations could be, e.g., background noise in the data that, when accounted
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`for statistically, still permitted high yield (by eliminating the effects of the noise on
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`the test results) while eliminating components with degraded reliability. (Id. ¶ 40.)
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`Thus, it was appreciated that reducing test result variance by calibrating the range
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`against which each set of components was tested, to account for noise or natural
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`variation across lots, would lead to greater yield. (Id. ¶¶ 41-42.)
`
`Another well-known technique was “part average testing” (PAT). (See Au-
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`tomotive Electronics Council, “Guidelines for Part Average Testing,” AEC -
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`Q001- Rev A, October 8, 1998, Ex. 1007.) With PAT, some parts that pass manu-
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`facturing tests but with parameters that deviate from the overall population are
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`known as “outliers.” PAT statistically determines parametric limits to discriminate
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`between two kinds of outliers: those likely to have reduced reliability, and those
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`that are not. PAT modified these limits continuously as more devices were sam-
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`pled. This technique is described, for example, in the article by Michelson (Ex.
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`1008). (Ex. 1002 ¶ 43.)
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`In the relevant time frame, commercial statistical tools were commonly used
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`to analyze test data. For example, using SAS tools were described in a 2000 paper
`
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`by Whitney and Fowler (Ex. 1009). Likewise, RS/1 was a commercial statistical
`
`package widely used to perform yield analysis, as discussed in a 1990 article by
`
`Trahan and Dean (Ex. 1010). (Ex. 1002 ¶ 44.) The RS/1 statistical package is ex-
`
`pressly mentioned in the Sun reference, discussed below. (Ex. 1011 at 7:35.)
`
`II. THE ’373 PATENT
`
`The ’373 Patent is directed to the testing of semiconductors (e.g., wafers,
`
`die, devices such as resistors, other circuitry formed thereon) or other components
`
`(e.g., packaged parts, circuit boards, electric or optical systems). (Ex. 1001 at 3:26-
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`30, 17:28-45). The ’373 Patent discloses identifying whether test results exceed a
`
`specification threshold, or are within such thresholds but deviate substantially from
`
`a desired range. (Id. at 6:32-51). The ’373 Patent discloses identifying whether test
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`results exceed a specification threshold, or are within such thresholds but deviate
`
`substantially from a desired range. (Id. at 6:32-51). The ’373 Patent refers to a de-
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`viant but in-spec result as an “outlier.” (Id. at Abstract; Fig. 1; 3:51-58; Ex. 1002 ¶
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`45).
`
`The ’373 Patent discloses using a tester and a computer. The tester is de-
`
`scribed as “automatic test equipment (ATE)” or “any test equipment that tests
`
`components 106 and generates output data.” (Ex. 1001 at 3:24-37.) The specifica-
`
`tion refers to a “Teradyne tester” as an example. (Id. at 3:37.) The tester is con-
`
`nected to a computer system that receives the tester data. (Id. at 3:42-49.)
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`Figure 1 shows the configuration of the subject system, which has a tester
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`102 that tests semiconductor components 106 on a wafer and that is connected to a
`
`computer system 108. (Id. at Fig. 1; Ex. 1002 ¶ 47.) The computer system 108 may
`
`comprise a separate computer or may be integrated with the tester. (Ex. 1001 at
`
`3:51-57; Ex. 1002 ¶ 48.)
`
`The computer analyzes test results using a statistical engine (software). (Ex.
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`1001 at 3:45-52.) This software may include a configuration element that config-
`
`ures the test system to address differences in the component being tested. (Id. at
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`5:23-38). The configuration may be stored in a database as a “configuration file” or
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`“recipe file.” (Id. at 5:64-6:18; Ex. 1002 ¶ 49.)
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`Upon testing a semiconductor component, the tester generates test results
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`and stores them in a database. (Ex. 1001 at 6:32-33; 6:52-57.) The stored test re-
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`sults are passed to the computer, which uses its statistical software engine (a “sup-
`
`plementary data analysis element”) to analyze the data to identify failed devices
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`and “outliers.” (Ex. 1001 at 6:52-66; Ex. 1002 ¶ 50.) In one place, the ’373 Patent
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`defines “outliers” as “those test results that stray from the first set [of test results]
`
`but do not exceed the control limits or otherwise fail to be detected.” (Id. at 6:44-
`
`46; Ex. 1002 ¶51). This definition is shown in Figure 9 as the “Bin 1 Outlier.”
`
`The ’373 Patent discloses that the analysis to identify outliers may be com-
`
`menced “at run time,” defined as “within a matter of . . . minutes following genera-
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`tion of the test data.” (Ex. 1001 at 7:15-18; Ex. 1002 ¶¶ 52, 123.) The ’373 Patent
`
`does not teach any specific technique for analyzing “at run time.” Rather it identi-
`
`fies only the desirability of doing so. (Ex. 1002 ¶ 52.).
`
`The ’373 Patent discloses that the system is to have a “recipe file, which
`
`may include configuration algorithms, parameters, or any other criteria to be used
`
`in testing.” (Ex. 1001 at 6:15-19.) Another type of “recipe file” disclosed is used
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`by a program in the computer to statistically analyze the test data. (Id. at 8:21-31.)
`
`The recipe file may also contain sensitivity parameters that can be used to identify
`
`critical, marginal, and good parts. (Id. at 17:1-3.) The parameters may be operator-
`
`defined or derived from statistical analysis. (Ex. 1002 ¶ 53).
`
`Threshold levels for defining outliers may be generated by a “smoothing
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`system” implemented by a computer program. (Ex. 1001 at 9:26-35.) “The initial
`
`smoothing process and coefficients may be selected according to any criteria and
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`configured in any manner.” (Id. at 10:42-44.) Technique examples include “ran-
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`dom, random walk, moving average, simple exponential, linear exponential, sea-
`
`sonal exponential, exponential weighted moving average, or any other appropriate
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`type of smoothing.” (Id. at 10:47-51; Ex. 1002 ¶ 53). The statistical program may
`
`also include a “scaling element,” which uses test data to automatically calibrate the
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`norm against which results are measured. (Ex. 1001 at 14:15-18.)
`
`The system may “correlate the output test data to provide information … re-
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`lating to the component 106 and the test system 100.” (Id. at 9:18-21; see also Id.
`
`at 13:31-39; 16:25-36.) Such data correlation information may be provided to the
`
`user in a report. (Id. at 18:46-48; Ex. 1002 ¶ 54)
`
`The ’373 Patent also describes the grouping of test data based on the relative
`
`positions of components on a wafer. The analysis program may analyze together
`
`the results from geographically proximate components, referred to as “section
`
`groups.” (Ex. 1001 at 7:63-64.) A section group may be defined by the location of
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`the device on the wafer, such as by row, column, stepper field, circular band, radial
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`zone, quadrant, or other desired grouping. (Id. at 8:8-10.) The analysis program us-
`
`es configuration data, such as statistics or calculations, associated with the section
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`group to analyze the set. (Id. at 8:26-36; Ex. 1002 ¶ 55.)
`
`III. OVERVIEW OF THE PRIOR ART
`
`A.
`
`The Sun Patent
`
`U.S. Patent No. 6,240,329, granted to Sun (“Sun”) (Ex. 1011) is directed to
`
`the automated testing of semiconductor wafers and devices formed thereon. (Id. at
`
`Abstract; Ex. 1002 ¶ 56.)
`
`Sun discloses using a tester to measure electrical parameters (e.g., threshold
`
`voltage, saturation current, resistivity) of semiconductor components on a wafer,
`
`such as transistor structures. (Id. at 3:1-29; 6: 63-67; Ex. 1002, ¶¶ 57-58). The
`
`tester, integrated with a computer, analyzes test results to identify any “out of
`
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`Patent No. 6,792,373
`Petition For Inter Partes Review
`spec.,” “out of control,” or invalid test results. Sun defines an “out of spec.” result
`
`as one that exceeds a lower or upper specification limit. The specification limits
`
`define thresholds for passing or failing. (Ex. 1011 at 3:47-51; Ex. 1002 ¶ 59) Nota-
`
`bly, Sun defines an “out of control” test result as one that is within the specifica-
`
`tion limits, but outside of lower and upper control limits, which delimit the pre-
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`ferred test result range. (Ex. 1011 at 3:40-45; Ex. 1002 ¶ 60). In other words, what
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`Sun calls an “out of control” test result is an “outlier” as that term is used in the
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`’373 Patent.
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`Sun teaches that the “out of control” analysis should be performed on an av-
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`erage of measurements taken at different wafer locations (Ex. 1011 at 3:6-11; 6:21-
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`30.) Sun uses an average of five or more data points for any particular measure-
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`ment. (Id. at 5:52-59; 6:21-30; Figs. 3A and 3B; Ex. 1002 ¶ 62)
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`Sun teaches that the tester creates summary tables for each wafer and for the
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`wafer lot, and stores these tables for further analysis. The summary tables identify
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`outliers and failures in the test results. (Ex. 1011 at 4:13-30; Figs. 3A-3D; Ex. 1002
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`¶ 65). In particular, upon analyzing the wafer data, the computer generates a report
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`identifying “out of spec,” “out of control,” or “invalid” results. Such results are
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`identified in the summary tables with the symbols “*”, “#” and “?” respectively.
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`(Ex. 1011 at 4:18-26.) Figure 3D is an example of such a report, and it identifies an
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`outlier by using the ‘#’ symbol, highlighted below:
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`The highlighted “AVG” is designated with a ‘#’ sign because it falls within
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`the upper and lower specification limits (USL and LSL), but goes below the lower
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`control limit (LCL) of 230.000000. In other words, the AVG result (221.009198) is
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`within spec (because it is above 220.0000) but out of a desired range (230.0000-
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`460.0000), and thus an “outlier.” (Ex. 1002 ¶ 63.)
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`Sun also discloses a computerized “expert system” that correlates test results
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`to identify the likelihood that a particular wafer suffers from a particular defect due
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`to a particular root cause. (Ex. 1011 at Fig. 1; Ex. 1002 ¶ 57.) Sun teaches compar-
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`ing different test results to determine the degree of failure for a wafer and its possi-
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`ble cause. (Ex. 1011 at 10:20-36; Ex. 1002 ¶ 66).
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`B.
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`The Madge Patent
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`U.S. Patent No. 6,598,194 to Madge et al. (“Madge”) is directed to testing
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`ICs on a semiconductor wafer. Madge is specifically directed to a method for clas-
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`sifying the graded ICs on a wafer according to their properties and physical posi-
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`tion on the wafer. (Ex. 1012 at Abstract; Ex. 1002 ¶ 68.)
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`Madge teaches using a wafer tester to test ICs. The wafer tester uses prede-
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`termined input vectors to test ICs with associated position designations. (Ex. 1012
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`at 2:23-26.) IC test results are recorded on a wafer map according to each IC’s po-
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`sition. (Id. at 2:26-29.) A computer, using instructions from files (“recipe files”),
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`retrieves the test data. (Id. at 9:49-67.) The computer then selects and mathemati-
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`cally manipulates the data for subsets of ICs to produce reference values. (Id. at
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`2:30-32.) The reference value is a smoothed value which, in the preferred embod-
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`iment, is the median value of the subset of circuits. (Id. at 7:10-29; Ex. 1002 ¶ 69.)
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`Madge further teaches comparing test data for each of the ICs in the selected
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`subset to the reference value to identify those test results that stray from the refer-
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`ence value by a given statistical amount. (Id. at 2:32-37.) In this way, Madge de-
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`fines an “outlier” by its statistical comparison to other test data within the set.
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`By using the smoothed data from the subset of circuits as a reference value,
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`Madge also teaches using the reference value from a subset of circuits to adjust the
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`sensitivity (i.e., reference ranges) used to determine whether an IC has failed,
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`based on the relative values for other ICs in the same region on the wafer. (Id. at
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`2:41-59; 7:65-8:1; Ex. 1002 ¶ 70.)
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`Madge teaches analyzing wafer test data to determine whether regional pat-
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`terns exist across its surface, as electrical characteristics may vary by region. (Ex.
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`1012 at 4:10-15). Madge discloses many regional group examples: concentric, lin-
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`ear band, wedge, crescent, stepper, irregular contiguous, and “nearest neighbor”
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`(i.e., surrounding ICs). (Id. at 4:19-6:48; Figs. 5A-5F). Madge teaches that analyz-
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`ing all ICs without regard to regional differences will falsely indicate a high degree
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`of variability (i.e., failure) within the overall group, even though there may be a
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`very low degree of variability within separate regions. (Id. at 4:36-42). Madge
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`teaches improving analysis by detecting regional differences and considering re-
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`gions separately. (Id. at 4:42-48; Ex. 1002 ¶ 71.) To do so, Madge teaches using
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`the median values for all ICs in a region as the testing reference range for each in-
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`dividual IC in that region. (Id. at 7:10-44.) Thus, Madge teaches analyzing test data
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`for subsets of ICs based on their location (i.e., “section groups”). (Ex. 1002 ¶ 72.)
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`Madge also teaches that the disclosed methods can be used to identify “out-
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`liers” by grading individual circuits. (Ex. 1012 at 9:30-48). Madge states:
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`“[T]he method and apparatus described herein can not only assign failure
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`codes as described, but can also assign a grade of passing code, where the grade of
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`the passing code assigned relates to the magnitude of the offset between the val-
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`ue of the sensed parameter for the IC and the reference value. For example, ICs
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`with relatively smaller offsets may be assigned a passing code indicating a higher
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`passing grade, where ICs with relatively larger offsets, but not so large as to be
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`classified as an outlier, may be assigned a passing code indicating a lower pass-
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`ing grade. This may be useful, for example, in applications where differing speeds
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`of ICs are desired.”
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`(Id. at 9:35-48) (emphasis added). Thus, Madge distinguishes between failed
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`devices and “outliers,” as that term is used in the ’373 Patent. (Ex. 1002 ¶ 73.)
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`Note that Madge uses the word “outlier” in a manner different than Patent
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`Owner’s proposed construction of the term. Madge, however, also teaches the
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`identification of specific data that matches Patent Owner’s construction of “outli-
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`er,” namely “ICs with relatively larger offsets, but not so large as to be classified as
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`an outlier.” Madge uses this different terminology for the ’373 Patent’s concept of
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`“outlier”; Madge uses the verbiage “outlier” to mean what the ’373 Patent would
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`call out of spec, or a failed test result. Despite the difference in labels, Madge
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`teaches the identification of an “outlier” as that term is used in the ’373 Patent.
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`This distinction is important lest one be misled into thinking that Madge discusses
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`only “failures” and not “outliers” as defined in the ’373 Patent.
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`After ICs are classified, Madge teaches creating a wafer map showing each
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`IC’s grade. This map is sent to a “pick and place” unit that appropriately bins ICs
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`for packaging or subsequent testing. (Ex. 1012 at 2:37-40; 9:13-26; Ex. 1002 ¶ 74.)
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`C.
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`The O’Donoghue Patent
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`U.S. Patent No. 5,497,381 to O’Donoghue et al. (“O’Donoghue”) is directed
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`to analyzing IC devices on a wafer to identify defects in real time. (Ex. 1013 at
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`Abstrac