®
`
`3C90x and 3C90xB NICs
`Technical Reference
`
`3Com
`
`®
`
` EtherLink
`
`®
`
` XL and Fast EtherLink XL PCI network interface cards
`
`http://www.3com.com/
`
`Part Number: 89-0766-000
`Published August 1998
`
`PALO ALTO NETWORKS Exhibit 1014 Page 1
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`3Com Corporation
`5400 Bayfront Plaza
`Santa Clara, California
`95052-8145
`
` 3Com Corporation, 1998.
` All rights reserved. No part of this documentation may be
`Copyright ©
`reproduced in any form or by any means or used to make any derivative work (such as translation,
`transformation, or adaptation) without permission from 3Com Corporation.
`
`3Com Corporation reserves the right to revise this documentation and to make changes in content from
`time to time without obligation on the part of 3Com Corporation to provide notification of such revision
`or change.
`
`3Com Corporation provides this documentation without warranty of any kind, either implied or expressed,
`including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.
`3Com may make improvements or changes in the product(s) and/or the program(s) described in this
`documentation at any time.
`
`UNITED STATES GOVERNMENT LEGENDS:
`If you are a United States government agency, then this documentation and the software described herein
`are provided to you subject to the following restricted rights:
`
`For units of the Department of Defense:
`Restricted Rights Legend:
` Use, duplication, or disclosure by the Government is subject to restrictions as set
`forth in subparagraph (c) (1) (ii) for Restricted Rights in Technical Data and Computer Software Clause at
`48 C.F.R. 52.227-7013. 3Com Corporation, 5400 Bayfront Plaza, Santa Clara, California 95052-8145.
`
`For civilian agencies:
`Restricted Rights Legend:
` Use, reproduction, or disclosure is subject to restrictions set forth in subparagraph
`(a) through (d) of the Commercial Computer Software – Restricted Rights Clause at 48 C.F.R. 52.227-19 and
`the limitations set forth in 3Com Corporation’s standard commercial agreement for the software.
`Unpublished rights reserved under the copyright laws of the United States.
`
`If there is any software on removable media described in this documentation, it is furnished under a license
`agreement included with the product as a separate document, in the hard copy documentation, or on the
`removable media in a directory file named LICENSE.TXT. If you are unable to locate a copy, please contact
`3Com and a copy will be provided to you.
`
`Unless otherwise indicated, 3Com registered trademarks are registered in the United States and may or
`may not be registered in other countries.
`
`3Com and EtherLink are registered trademarks of 3Com Corporation. Lanworks is a trademark of
`3Com Corporation.
`
`Magic Packet is a trademark of Advanced Micro Devices, Inc. Atmel is a trademark of Atmel Corporation.
`Broadcom is a trademark of Broadcom Corporation. Dell is a registered trademark of Dell Computer
`Corporation. IBM is a registered trademark of International Business Machines Corporation. Lucent
`Technologies is a trademark of Lucent Technologies, Inc. National Semiconductor is a registered
`trademark of National Semiconductor Corporation.
`
`Other brand and product names may be registered trademarks or trademarks of their respective holders.
`
`PALO ALTO NETWORKS Exhibit 1014 Page 2
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`1
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`C
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`ONTENTS
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`I
`NTRODUCTION
`3C90x NIC Features 18
`3C90xB NIC Features 18
`About This Technical Reference 19
`Decimal, Binary, and Hexadecimal Numbers 19
`Terms and Acronyms 19
`Register Bit Maps 20
`
`A
`RCHITECTURE
`3C90x NICs Block Diagrams 21
`3C90xB NICs Block Diagrams 23
`ASICs 27
`Hardware Identification 28
`Software Identification 28
`3C90x NICs ASIC Diagram 28
`3C90xB NICs ASIC Diagrams 28
`ASIC Block Descriptions 30
`PCI Bus Controller 30
`Upload and Download Engines 31
`Transmit and Receive FIFOs 31
`10/100 Mbps Ethernet MAC 31
`Management Statistics 31
`Auto-Negotiation 31
`10BASE-T/AUI Interface 31
`100 Mbps Signaling 32
`10/100 Mbps PHY 32
`MII Control Logic 32
`Other NIC Devices 32
`BIOS ROM 32
`Serial EEPROM 32
`External Media Transceivers 32
`Host Registers 33
`Bit Widths of Register Accesses 33
`Command Register 33
`Interrupt Status Register 33
`3C90x NICs Register Layout 34
`3C90xB NICs Register Layout 36
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`PALO ALTO NETWORKS Exhibit 1014 Page 3
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`3
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`O
`PERATION
`Data Structure Lists 39
`PCI Bus Master Operation 39
`PCI Memory Commands 39
`PCI Bus Request Control 40
`Download 41
`Upload 41
`IEEE 802.3x Flow Control 41
`VLAN Support 42
`IEEE 802.1Q VLANs 42
`3Com VLT 42
`Power Management 43
`Power Management Registers 43
`Power States 43
`Remote Wake-Up 44
`Wake-up Packets 45
`Downloading Wake-up Frame Patterns 45
`Wake-up Frame Patterns 45
`Magic Packet Technology 46
`Change of Link State 47
`Programming Remote Wake-Up Events 47
`Power Down 47
`Wake-Up 48
`TCP/IP Checksum Support 48
`
`C
`ONFIGURATION
`System Reset 51
`Serial EEPROM 51
`NIC Configuration 52
`Forced Configuration 53
`Support for Signaling Standards 54
`10 Mbps Signaling 57
`100BASE-X Signaling 57
`Media-Independent Interface/100BASE-T4 57
`Auto-Negotiation 58
`BIOS ROM 58
`InternalConfig 59
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`PALO ALTO NETWORKS Exhibit 1014 Page 4
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`NIC Initialization 63
`Selecting the Media Port 63
`Selection Through EEPROM 63
`AutoSelect 63
`MediaOptions 64
`AutoSelect Sequence 64
`Auto-Negotiation 64
`MII/100BASE-T4 65
`100BASE-FX 65
`AUI 66
`10BASE2 66
`Manual Testing of 10BASE-T and 100BASE-TX 66
`Setting the Receive Filter 66
`Station Address 66
`Broadcast Packets 67
`Multicast Packets 67
`Multicast Address Hash Filter 67
`Promiscuous Mode 67
`Capabilities Word 67
`MacControl 67
`Setting the Duplex Mode 67
`3C90x NICs 67
`3C90xB NICs 68
`PCI Configuration Registers 68
`VendorId 69
`DeviceId 69
`PciCommand 70
`PciStatus 70
`RevisionId 71
`ClassCode 72
`CacheLineSize 72
`LatencyTimer 72
`HeaderType 73
`IoBaseAddress 73
`MemBaseAddress 73
`SubsystemVendorId 74
`SubsystemId 74
`BiosRomControl 74
`CapPtr 74
`InterruptLine 75
`InterruptPin 75
`MinGnt 75
`MaxLat 75
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`PALO ALTO NETWORKS Exhibit 1014 Page 5
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`5
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`Power Management 75
`CapID 75
`NextPtr 75
`PowerMgmtCap 76
`PowerMgmtCtrl 76
`PowerMgmtEvent 77
`
`EEPROM
`Data Format 79
`3Com Node Address 81
`DeviceId 81
`Manufacturing Data 81
`Date 81
`Division 81
`Product Code 81
`ManufacturerId 82
`RomInfo 82
`PciParm 82
`OEM Node Address 83
`Software Information 83
`Compatibility Word 84
`Capabilities Word 84
`InternalConfig 86
`AnalogDiagnostic 86
`Software Information 2 86
`Software Information 3 87
`Lanworks Data 87
`SubsystemVendorId 87
`SubsystemId 88
`MediaOptions 88
`Checksum 88
`EepromCommand 88
`EepromData 90
`
`6
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`D
` T
`RANSMISSION
`OWNLOAD
`AND
`Packet Download Model 91
`DPD Data Structure 92
`Down Next Pointer 93
`Frame Start Header 93
`Schedule Time 95
`Down Fragment Address 96
`Down Fragment Length 96
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`PALO ALTO NETWORKS Exhibit 1014 Page 6
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`Packet Download 97
`Simple Packet Download 97
`Packet Length Round Up 97
`3C90x NICs 97
`3C90xB NICs 98
`Download Scheduling 98
`Download Completion 98
`Multipacket Lists 99
`Adding DPDs to the End of the Downlist 99
`Inserting a DPD Near the Head of the Downlist 99
`Inserting a DPD in Front of a Scheduled DPD 100
`Polling on DnNextPtr 100
`NIC Download Sequence 101
`3C90x NICs 101
`3C90xB NICs 101
`Packet Transmission 102
`Enabling Transmission 102
`Transmit Errors 102
`Underrun Recovery 103
`Reclaiming Transmit FIFO Space 103
`Transmit Mechanism 104
`Limiting dnComplete Interrupts 104
`Using CountDown Timer Instead of dnComplete 104
`DmaCtrl 104
`DnBurstThresh 107
`DnListPtr 107
`DnMaxBurst 109
`DnPoll 109
`DnPriorityThresh 109
`TxFree 110
`TxFreeThresh 110
`TxPktId 111
`TxReclaimThresh 112
`TxStartThresh 112
`TxStatus 113
`
`7
`
` U
`
`R
`PLOAD
`AND
`ECEPTION
`Packet Upload Model 115
`UPD Data Structure 116
`Up Next Pointer 116
`Up Pkt Status 116
`Up Fragment Address 118
`Up Fragment Length 119
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`PALO ALTO NETWORKS Exhibit 1014 Page 7
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`Packet Reception 119
`Enabling Reception 119
`Simple Packet Upload 119
`Upload Eligibility 120
`Packet Upload Completion 120
`Multipacket Lists 120
`Early Receive Interrupts 121
`Parallel Tasking of Receive Uploads 121
`NIC Upload Sequence 121
`DmaCtrl 122
`MaxPktSize 122
`RxEarlyThresh 122
`RxError 124
`RxFilter 124
`RxFree 125
`RxStatus 126
`StationAddress 127
`StationMask 127
`UpBurstThresh 128
`UpListPtr 128
`UpMaxBurst 129
`UpPktStatus 129
`UpPoll 131
`UpPriorityThresh 132
`VlanMask 132
`
` I
`
`I
`NDICATIONS
`AND
`NTERRUPTS
`IndicationEnable 134
`InterruptEnable 134
`IntStatus 135
`IntStatusAuto 137
`
`IAGNOSTICS
`
` D
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`S
`AND
`TATISTICS
`BadSSD 140
`BytesRcvdOk 140
`BytesXmittedOk 141
`CarrierLost 141
`FramesDeferred 142
`FramesRcvdOk 142
`FramesXmittedOk 143
`LateCollisions 143
`MultipleCollisions 144
`RxOverruns 144
`SingleCollisions 145
`SqeErrors 145
`UpperBytesOk 146
`UpperFramesOk 147
`
`8
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`9
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`PALO ALTO NETWORKS Exhibit 1014 Page 8
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`10
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`C
`EGISTER
`OMMAND
`Reset Commands 151
`GlobalReset 151
`RxReset 152
`TxReset 152
`Transmit Commands 153
`DnStall 153
`DnUnstall 154
`SetTxReclaimThresh 154
`SetTxStartThresh 154
`TxDisable 154
`TxEnable 154
`Receive Commands 155
`RxDisable 155
`RxEnable 155
`SetHashFilterBit 155
`SetRxEarlyThresh 156
`SetRxFilter 157
`UpStall 157
`UpUnStall 157
`Interrupt Commands 158
`AcknowledgeInterrupt 158
`RequestInterrupt 158
`SetIndicationEnable 158
`SetInterruptEnable 159
`Other Commands 159
`DisableDcConverter 159
`EnableDcConverter 159
`SelectRegisterWindow 159
`StatisticsDisable 160
`StatisticsEnable 160
`
`11
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`EGISTERS
`
` MII R
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`-N
`A
`AND
`EGOTIATION
`UTO
`3C90xB NICs Auto-Negotiation 161
`40-0502-00x ASIC Auto-Negotiation Registers 162
`AutoNegAbility 162
`AutoNegAdvert 163
`AutoNegControl 164
`AutoNegExpansion 165
`AutoNegPhyId1 and AutoNegPhyId2 166
`AutoNegStatus 166
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`PALO ALTO NETWORKS Exhibit 1014 Page 9
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`40-0476-001 ASIC Auto-Negotiation Registers 168
`10BASE-T Auxiliary Error and General Status 169
`100BASE-X Auxiliary Control 170
`100BASE-X Auxiliary Status 171
`100BASE-X Disconnect Counter 172
`100BASE-X False Carrier Sense Counter 172
`100BASE-X Receive Error Counter 172
`Auto-Negotiation Advertise 173
`Auto-Negotiation Expansion 174
`Auxiliary Control/Status 175
`Auxiliary Mode 176
`Auxiliary Multiple PHY 177
`Auxiliary Status Summary 179
`Control 180
`Link Partner Ability 182
`PHYID High 183
`PHYID Low 183
`Status 184
`TX Equalizer Coefficient Control 185
`TX Equalizer Coefficient Read/Write 185
`40-0483-00x ASIC Auto-Negotiation Registers 185
`MR0 Control 186
`MR1 Status 187
`MR2 PHY Identification 188
`MR3 PHY Identification 188
`MR4 Auto-Negotiation Advertisement 188
`MR5 Auto-Negotiation Link Partner Ability 189
`MR6 Auto-Negotiation Expansion 189
`MR7 Next Page Transmit 190
`MR28 Device-specific Register 1 191
`MR29 Device-specific Register 2 191
`MR30 Device-specific Register 3 192
`
`12
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` R
`O
`EGISTERS
`THER
`BiosRomAddr 193
`BiosRomData 194
`DebugControl 194
`DebugData 195
`FifoDiagnostic 195
`Media 197
`MacControl 197
`MediaOptions 199
`MediaStatus 201
`NetworkDiagnostic 203
`PhysicalMgmt 205
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`PALO ALTO NETWORKS Exhibit 1014 Page 10
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`A
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`ResetOptions 206
`3C90x NICs 206
`3C90xB NICs 207
`Timers and Counters 209
`Countdown 209
`FreeTimer 210
`RealTimeCnt 211
`Timer 211
`VlanEtherType 212
`
` C
` P
`S
`A
`SEUDO
`ELECT
`UTO
`AutoSelect Sequence 213
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`ODE
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`I
`NTERFACE
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`P
` MII M
`ANAGEMENT
`ROGRAMMING
`THE
`Management Frame Formats 217
`Read Frame 217
`Write Frame 218
`Read Cycle 218
`Write Cycle 218
`Z Cycle 218
`
` F
`F
`ORMATS
`RAME
`IEEE 802.3 MAC Frame Format 219
`IEEE 802.3x PAUSE Frame Format 220
`IEEE 802.1q Frame Format 221
`3Com VLT Frame Format 222
`
` S
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` L
`E
`AND
`IST
`RRATA
`3C90x NICs 223
`3C90xB NICs 224
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`OFTWARE
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`S
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`OLUTIONS
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`I
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`NDEX
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`NDEX
`OF
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`EGISTERS
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`I
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`NDEX
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`OF
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`ITS
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`F
`IGURES
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`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
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`3C900-TPO System Architecture 21
`3C900-COMBO System Architecture 22
`3C905-TX System Architecture 22
`3C905-T4 System Architecture 23
`3C900B-TPO System Architecture 23
`3C900B-TPC System Architecture 24
`3C900B-COMBO System Architecture 24
`3C905B-TX with 40-0502-00x ASIC System Architecture 25
`3C905B-TX with 40-0476-001 or 40-0483-00x ASIC System Architecture 25
`3C905B-TX-NM System Architecture 26
`3C900B-FL System Architecture 26
`3C905B-FX System Architecture 27
`3C90x NICs ASIC Block Diagram 28
`3C900B NICs ASIC Block Diagram 28
`3C905B-TX NIC—40-0502-00x ASIC Block Diagram 29
`3C905B-TX NIC—40-0476-001 ASIC Block Diagram 29
`3C905B-TX NIC—40-0483-00x ASIC Block Diagram 29
`3C900B-FL NIC ASIC Block Diagram 30
`3C905B-FX NIC ASIC Block Diagram 30
`3C90xB NICs Bus Request Structure 40
`3C90x NICs (40-0336-00x ASIC) Media Port Architecture 54
`3C900B NICs (40-0456-004 ASIC) Media Port Architecture 55
`3C90xB NICs (40-0502-00x ASIC) Media Port Architecture 56
`3C905B-TX NICs (40-0476-001 or 40-0483-00x ASIC) Media Port Architecture 56
`Downlist 91
`Type 0 DPD Format 92
`Type 1 DPD Format 92
`Uplist 115
`UPD Format 116
`IEEE 802.3 MAC Frame Format 219
`IEEE 802.3x PAUSE Frame Format 220
`IEEE 802.1q Frame Format 221
`3Com VLT Frame Format 222
`
`PALO ALTO NETWORKS Exhibit 1014 Page 13
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`

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`PALO ALTO NETWORKS Exhibit 1014 Page 14
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`

`
`TABLES
`
`1
`3C90x NICs 17
`2
`3C90xB NICs 17
`3
`ASICs Summary 27
`4
`3C90x NICs Register Layout 34
`5
`3C90x NICs Register Window Layout 35
`6
`3C90xB NICs Register Layout 36
`7
`3C90xB NICs Register Window Layout 37
`8
`3C90x NICs PCI Memory Commands 39
`9
`3C90xB NICs PCI Memory Commands 40
`10
`3C90xB NICs Power States 43
`11
`EEPROM Data Locations 51
`12
`PCI Registers Set During Configuration 53
`13
`3C90x NIC ramPartition Values 61
`14
`Summary of 3C90x NICs PCI Configuration Registers 68
`15
`Summary of 3C90xB NICs PCI Configuration Registers 69
`16
`3C90x NICs EEPROM Contents 79
`17
`3C90xB NICs EEPROM Contents 80
`18
`3C90x NICs Summary of Capabilities 84
`19
`3C90xB NICs Summary of Capabilities 85
`20
`DPD Format Bit Combinations 92
`21 Minimum Frame Size for RxError 124
`22
`Interrupt-specific Actions 133
`23
`Summary of Transmit Statistics 139
`24
`Summary of Receive Statistics 140
`25
`Command Summary 150
`26
`Summary of 40-0502-00x ASIC Auto-Negotiation Registers 162
`27
`Summary of 40-0476-001 ASIC Auto-Negotiation and MII Registers 168
`28
`Summary of 40-0483-00x ASIC Auto-Negotiation and MII Registers 185
`29
`Loopback Modes 205
`30 Management Frame Formats 217
`31
`3C90x NICs (40-0336-00x ASIC) Anomalies 223
`32
`3C90xB NICs (40-0502-00x ASIC) Anomaly 224
`33
`3C90xB NICs (40-0483-00x ASIC) Anomalies 224
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`PALO ALTO NETWORKS Exhibit 1014 Page 15
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`PALO ALTO NETWORKS Exhibit 1014 Page 16
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`

`
`1
`
`INTRODUCTION
`
`This technical reference describes the basic architecture and defines the
`programming interface of 3Com® EtherLink® XL and Fast EtherLink XL
`network interface cards (NICs). The NIC models are listed in Table 1 and Table 2.
`
`Table 1 3C90x NICs
`
`Model
`3C900-TPO
`3C900-COMBO
`
`Speed
`10 Mbps
`10 Mbps
`
`3C905-TX
`
`10 /100 Mbps
`
`3C905-T4
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`10/100 Mbps
`
`Table 2 3C90xB NICs
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`Model
`3C900B-TPO
`3C900B-TPC
`
`Speed
`10 Mbps
`10 Mbps
`
`3C900B-COMBO
`
`10 Mbps
`
`3C905B-TX
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`10/100 Mbps
`
`3C905B-TX-NM
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`10/100 Mbps
`
`3C900B-FL
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`10 Mbps
`
`Media Type
`10BASE-T
`10BASE-T
`10BASE-5
`10BASE-2
`10BASE-T/
`100BASE-TX
`10BASE-T/
`100BASE-T4
`
`Media Type
`10BASE-T
`10BASE-T
`10BASE-2
`10BASE-T
`10BASE-5
`10BASE-2
`10BASE-T/
`100BASE-TX
`10BASE-T/
`100BASE-TX
`10BASE-FL
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`3C905B-FX
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`100 Mbps
`
`100BASE-FX
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`Cable
`Two-pair Category 3, 4, or 5 UTP
`Two-pair Category 3, 4, or 5 UTP
`Thick Ethernet coaxial
`Thin Ethernet coaxial
`Two-pair Category 3, 4, or 5 UTP/
`Two-pair Category 5 UTP
`Two-pair Category 3, 4, or 5 UTP/
`Four-pair Category 5 UTP
`
`Cable
`Two-pair Category 3, 4, or 5 UTP
`Two-pair Category 3, 4, or 5 UTP
`Thin Ethernet coaxial
`Two-pair Category 3, 4, or 5 UTP
`Thick Ethernet coaxial
`Thin Ethernet coaxial
`Two-pair Category 5 UTP, or STP
`
`Connector
`RJ-45
`RJ-45
`AUI
`BNC
`RJ-45
`
`RJ-45
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`Connector
`RJ-45
`RJ-45
`BNC
`RJ-45
`AUI
`BNC
`RJ-45
`
`Two-pair Category 5 UTP, or STP
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`RJ-45
`
`Short-wavelength fiber-optic (850 nm):
`50 m
`/125 m
` and 62.5 m
`/125 m
`
`multimode fiber
`Long-wavelength fiber-optic (1300 nm):
`50 m
`/125 m
` and 62.5 m
`/125 m
`
`multimode fiber
`
`ST
`
`SC
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`PALO ALTO NETWORKS Exhibit 1014 Page 17
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`

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`18
`
`CHAPTER 1: INTRODUCTION
`
`3C90x NIC Features
`
`3C90xB NIC Features
`
`3C90x NICs have these features:
`n Multipacket, multifragment scatter operations for uploads
`n Multipacket, multifragment gather operations for downloads
`n Simultaneous upload and download operations
`n On-chip RAM that can be used instead of external RAM
`
`3C90xB NICs have these additional features:
`n 2 KB transmit FIFO and 2 KB receive FIFO.
`n True dual-channel DMA engine.
`n Enhanced scatter-gather engines that reduce the number of I/O operations
`required to support data transfers.
`n A download-scheduling mechanism that allows a packet to be downloaded at
`some specific future time. For example, download scheduling can be used to
`support video or audio streams over a LAN, or to avoid overflowing a switch’s
`buffers when the switch is communicating with a lower-speed device.
`n A hash filter that provides better multicast packet handling.
`n Support for VLANs and IEEE 802.3x flow control functions.
`n Support for IEEE 802.3u auto-negotiation (10BASE-T and 100BASE-TX).
`n Support for PC ‘97 guidelines, including ACPI Power Management.
`n Support for wake-up events (except 3C900B and 3C905B-TX-NM NICs).
`Improved bus master efficiency through use of optimal PCI memory commands
`and support of larger burst lengths.
`n TCP/IP checksum features.
`n Reduced I/O operations.
`n Direct register access to BIOS ROM.
`n An integrated 100 Mbps PHY that eliminates the need for an external
`100 Mbps transceiver (40-0476-001 and 40-0483-00x ASICs only).
`
`n
`
`There are three different versions of the ASIC on the 3C905B-TX NIC. These three
`ASICs function identically except for the PHY portion, which is proprietary to each
`ASIC. As a result, the MII register layouts differ on the three ASICs. See Chapter 11
`for information on the MII register layouts of each ASIC.
`
`For more information on the ASICs, see “ASICs” in Chapter 2.
`
`PALO ALTO NETWORKS Exhibit 1014 Page 18
`
`

`
`About This Technical Reference
`
`19
`
`About This
`Technical Reference
`
`This technical reference contains information that software engineers, independent
`software developers, and test engineers can use when writing device drivers,
`diagnostic programs, and production test software for 3C90x and 3C90xB NICs.
`
`Decimal, Binary, and
`Hexadecimal Numbers
`
`Specifications in this technical reference apply to all 3C90x and 3C90xB NICs
`unless the text designates a specific model or type (for example, 3C900 NIC or
`3C90xB NIC).
`
`Unless otherwise indicated in the text, all values are decimal. The following
`are exceptions:
`n Binary values are indicated with the character “b” appended to the value
`(for example, 234b).
`n Hexadecimal values are indicated with the character “h” appended to the
`value (for example, 234h).
`
`Terms and Acronyms
`
`The following terms and acronyms are used in this reference:
`
`Term or Acronym
`
`Meaning
`
`BIST
`
`Byte
`
`Built-in self test.
`
`An 8-bit wide quantity of data.
`
`Double word (dword)
`
`A 32-bit wide quantity of data (4 bytes).
`
`Download
`
`DPD
`
`FLP
`
`FSH
`
`Indication
`
`Interrupt
`
`MII
`
`NIC
`
`NOS
`
`PEROM
`
`PHY
`
`The process of transferring transmit data from system memory to
`the NIC.
`
`Download packet descriptor.
`
`Fast link pulse.
`
`Frame start header.
`
`The reporting of any interesting event on the NIC. Any indication
`may be configured to cause an interrupt.
`
`The actual assertion of the host machine’s interrupt signal.
`
`Media-Independent Interface.
`
`Network interface card.
`
`Network operating system.
`
`Programmable and erasable read-only memory.
`
`IEEE designation for Physical layer.
`
`Remote Wake-Up
`
`The ability to power on a networked PC that is in standby or
`suspend mode using a wake-up event.
`
`UDP
`
`UPD
`
`Upload
`
`WOL
`
`Word
`
`User datagram protocol.
`
`Upload packet descriptor.
`
`The process of transferring receive data from the NIC to
`system memory.
`
`Wake on LAN (also known as Remote Wake-Up).
`
`A 16-bit wide quantity of data (2 bytes).
`
`PALO ALTO NETWORKS Exhibit 1014 Page 19
`
`

`
`20
`
`CHAPTER 1: INTRODUCTION
`
`Register Bit Maps
`
`The register descriptions in this technical reference include register bit maps.
`For example:
`
`Most-significant word
`
`Most-significant byte
`
`Least-significant word
`
` Least-significant byte
`
`31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
`
`9
`
`8
`
`7
`
`6
`
`5
`
`4
`
`3
`
`2
`
`1
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`0
`
`The first row of a bit map shows the bit numbers.
`
`The second row of a bit map indicates the following information:
`n Shaded areas indicate active register bits. The functions of these bits are
`described in the register descriptions.
`n Unshaded areas in a register bit map indicate bits that disregard data written
`to them and return zeros when read. To ensure compatibility with future
`hardware, drivers should write zeros to these bits.
`n Vertical lines mark the boundaries of fields of bits (for example, [12:0]).
`
`PALO ALTO NETWORKS Exhibit 1014 Page 20
`
`

`
`2
`
`ARCHITECTURE
`
`This chapter describes the NIC system architectures and ASIC block diagrams,
`and summarizes the layout of the host registers and windows.
`
`3C90x NICs
`Block Diagrams
`
`The block diagrams for the 3C90x NICs are shown in Figure 1 through Figure 4.
`The NIC devices are described at the end of this chapter.
`
`Figure 1 3C900-TPO System Architecture
`
`Serial
`EEPROM
`
`Upload/
`download
`engine
`
`Mgmt.
`statistics
`
`10BASE-T
`
`10BASE-T/AUI
`interface
`
`100 Mbps
`signaling
`
`MII
`control
`
`40-0336-00x ASIC
`
`3C900-TPO NIC
`
`PCI
`bus
`controller
`
`Transmit/
`receive
`FIFO
`control
`
`10/100
`Mbps
`Ethernet
`MAC
`
`PCI bus
`
`External memory interface
`
`BIOS ROM
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`PALO ALTO NETWORKS Exhibit 1014 Page 21
`
`

`
`22
`
`CHAPTER 2: ARCHITECTURE
`
`Figure 2 3C900-COMBO System Architecture
`
`AUI
`
`10BASE2
`
`10BASE2
`transceiver
`
`10BASE-T
`
`10BASE-T/AUI
`interface
`
`100 Mbps
`signaling
`
`MII
`control
`
`40-0336-00x ASIC
`
`3C900-COMBO NIC
`
`10BASE-T/AUI
`interface
`
`100 Mbps
`signaling
`
`MII
`control
`
`40-0336-00x ASIC
`
`RJ-45
`
`DP83840
`PHY
`
`3C905-TX NIC
`
`Serial
`EEPROM
`
`Upload/
`download
`engine
`
`Mgmt.
`statistics
`
`PCI
`bus
`controller
`
`Transmit/
`receive
`FIFO
`control
`
`10/100
`Mbps
`Ethernet
`MAC
`
`External memory interface
`
`BIOS ROM
`
`Figure 3 3C905-TX System Architecture
`
`Serial
`EEPROM
`
`Upload/
`download
`engine
`
`Mgmt.
`statistics
`
`PCI
`bus
`controller
`
`Transmit/
`receive
`FIFO
`control
`
`10/100
`Mbps
`Ethernet
`MAC
`
`External memory interface
`
`BIOS ROM
`
`PCI bus
`
`PCI bus
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`PALO ALTO NETWORKS Exhibit 1014 Page 22
`
`

`
`3C90xB NICs Block Diagrams
`
`23
`
`Figure 4 3C905-T4 System Architecture
`
`Serial
`EEPROM
`
`Upload/
`download
`engine
`
`Mgmt.
`statistics
`
`10BASE-T/AUI
`interface
`
`100 Mbps
`signaling
`
`MII
`control
`
`40-0336-00x ASIC
`
`RJ-45
`
`100BASE-T4
`PHY
`
`3C905-T4 NIC
`
`PCI
`bus
`controller
`
`Transmit/
`receive
`FIFO
`control
`
`10/100
`Mbps
`Ethernet
`MAC
`
`PCI bus
`
`External memory interface
`
`BIOS ROM
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`3C90xB NICs
`Block Diagrams
`
`The block diagrams for the 3C90xB NICs are shown in Figure 5 through Figure 12.
`The NIC devices are described at the end of this chapter.
`
`Figure 5 3C900B-TPO System Architecture
`
`Serial
`EEPROM
`
`Mgmt.
`statistics
`
`10 Mbps
`Ethernet
`MAC
`
`Auto-
`negotiation
`
`RJ-45
`
`10BASE-T/AUI
`interface
`
`40-0456-004 ASIC
`
`Download
`engine
`
`Transmit
`FIFO
`
`Upload
`engine
`
`Receive
`FIFO
`
`PCI
`bus
`controller
`
`PCI bus
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`BIOS ROM
`
`3C900B-TPO NIC
`
`PALO ALTO NETWORKS Exhibit 1014 Page 23
`
`

`
`24
`
`CHAPTER 2: ARCHITECTURE
`
`Figure 6 3C900B-TPC System Architecture
`
`Serial
`EEPROM
`
`10BASE2
`
`Mgmt.
`statistics
`
`Auto-
`negotiation
`
`10BASE-2
`transceiver
`
`10 Mbps
`Ethernet
`MAC
`
`10BASE-T/AUI
`interface
`
`RJ-45
`
`40-0456-004 ASIC
`
`Download
`engine
`
`Transmit
`FIFO
`
`Upload
`engine
`
`Receive
`FIFO
`
`PCI
`bus
`controller
`
`PCI bus
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`BIOS ROM
`
`3C900B-TPC NIC
`
`Figure 7 3C900B-COMBO System Architecture
`
`Serial
`EEPROM
`
`AUI
`
`10BASE2
`
`Mgmt.
`statistics
`
`Auto-
`negotiation
`
`10BASE-2
`transceiver
`
`10 Mbps
`Ethernet
`MAC
`
`10BASE-T/AUI
`interface
`
`RJ-45
`
`40-0456-004 ASIC
`
`Download
`engine
`
`Transmit
`FIFO
`
`Upload
`engine
`
`Receive
`FIFO
`
`PCI
`bus
`controller
`
`PCI bus
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`BIOS ROM
`
`3C900B-COMBO NIC
`
`PALO ALTO NETWORKS Exhibit 1014 Page 24
`
`

`
`3C90xB NICs Block Diagrams
`
`25
`
`Figure 8 3C905B-TX with 40-0502-00x ASIC System Architecture
`
`3-pin Remote Wake-Up
`connector
`
`10BASE-T/AUI
`interface
`
`100 Mbps
`signaling
`
`MII
`control
`
`40-0502-00x ASIC
`
`RJ-45
`
`100BASE-TX
`transceiver
`
`3C905B-TX NIC
`
`Serial
`EEPROM
`
`Mgmt.
`statistics
`
`Auto-
`negotiation
`
`Download
`engine
`
`Transmit
`FIFO
`
`Upload
`engine
`
`Receive
`FIFO
`
`10/100
`Mbps
`Ethernet
`MAC
`
`PCI
`bus
`controller
`
`PCI bus
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`BIOS ROM
`
`Figure 9 3C905B-TX with 40-0476-001 or 40-0483-00x ASIC System Architecture
`
`Serial
`EEPROM
`
`3-pin Remote Wake-Up
`connector
`
`Mgmt.
`statistics
`
`MII
`
`10/100
`Mbps
`Ethernet
`MAC
`
`Auto-
`negotiation
`
`10/100 Mbps
`PHY
`
`RJ-45
`
`Download
`engine
`
`Transmit
`FIFO
`
`Upload
`engine
`
`Receive
`FIFO
`
`PCI
`bus
`controller
`
`PCI bus
`
`40-0476-001 or 40-0483-00x ASIC
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`BIOS ROM
`
`3C905B-TX NIC
`
`PALO ALTO NETWORKS Exhibit 1014 Page 25
`
`

`
`26
`
`CHAPTER 2: ARCHITECTURE
`
`Figure 10 3C905B-TX-NM System Architecture
`
`Serial
`EEPROM
`
`Mgmt.
`statistics
`
`10/100
`Mbps
`Ethernet
`MAC
`
`Auto-
`negotiation
`
`10/100 Mbps
`PHY
`
`RJ-45
`
`MII interface
`(optional)
`
`40-0483-001, -004, or -005 ASIC
`
`Download
`engine
`
`Transmit
`FIFO
`
`Upload
`engine
`
`Receive
`FIFO
`
`PCI
`bus
`controller
`
`PCI bus
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`BIOS ROM
`
`3C905B-TX-NM NIC
`
`3-pin Remote Wake-Up
`connector
`
`10BASE-T/AUI
`interface
`
`10BASE-FL
`transceiver
`
`100 Mbps
`signaling
`
`MII
`control
`
`40-0502-004 ASIC
`
`10BASE-FL
`
`3C900B-FL NIC
`
`Figure 11 3C900B-FL System Architecture
`
`Serial
`EEPROM
`
`Mgmt.
`statistics
`
`Auto-
`negotiation
`
`Download
`engine
`
`Transmit
`FIFO
`
`Upload
`engine
`
`Receive
`FIFO
`
`10/100
`Mbps
`Ethernet
`MAC
`
`PCI
`bus
`controller
`
`PCI bus
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Host
`CPU
`
`BIOS ROM
`
`PALO ALTO NETWORKS Exhibit 1014 Page 26
`
`

`
`ASICs
`
`27
`
`Figure 12 3C905B-FX System Architecture
`
`Serial
`EEPROM
`
`3-pin Remote Wake-Up
`connector
`
`Mgmt.
`statistics
`
`Auto-
`negotiation
`
`100BASE-FX
`
`10BASE-T/AUI
`interface
`
`100 Mbps
`signaling
`
`MII
`control
`
`40-0502-004 ASIC
`
`100BASE-FX
`transceiver
`
`3C905B-FX NIC
`
`System board
`
`System
`RAM
`Download
`packet
`descriptors
`
`TX buffer
`TX buffer
`TX buffer
`TX buffer
`
`Upload
`packet
`descriptors
`
`RX buffer
`RX buffer
`RX buffer
`RX buffer
`
`Download
`engine
`
`Transmit
`FIFO
`
`Upload
`engine
`
`Receive
`FIFO
`
`10/100
`Mbps
`Ethernet
`MAC
`
`PCI
`bus
`controller
`
`PCI bus
`
`Host
`CPU
`
`BIOS ROM
`
`ASICs
`
`The ASIC used by each NIC is listed in Table 3.
`
`Table 3 ASICs Summary
`
`NIC
`
`3C90x NICs
`3C900-TPO
`3C900-COMBO
`3C905-TX
`3C905-T4
`
`3C90xB NICs
`3C900B-TPO
`3C900B-TPC
`3C900B-COMBO
`3C905B-TX
`
`3C905B-TX-NM
`3C900B-FL
`3C905B-FX
`
`ASIC Number(s)
`
`40-0336-000, -001, -002, -003, or -004
`40-0336-000, -001, -002, -003, or -004
`40-0336-000, -001, -002, -003, or -004
`40-0336-000, -001, -002, -003, or -004
`
`40-0456-004
`40-0456-004
`40-0456-004
`40-0502-001, -002, -003, or -004
`40-0476-001
`40-0483-001, -002, -004, or -005
`40-0483-001, -004, or -005
`40-0502-004
`40-0502-004
`
`There are three different versions of the ASIC on the 3C905B-TX NIC. These three
`ASICs function identically except for the PHY portion, which is proprietary to each
`ASIC. As a result, the MII register layouts differ on the three ASICs. See Chapter 11
`for information on the MII register layouts of each ASIC.
`
`PALO ALTO NETWORKS Exhibit 1014 Page 27
`
`

`
`28
`
`CHAPTER 2: ARCHITECTURE
`
`Hardware Identification
`
`The ASIC on a 3C90x or 3C90xB NIC can be identified by the number that is
`inscribed on the ASIC. See Table 3 for a list of ASIC numbers.
`
`Software Identification
`
`The ASIC on a 3C90xB NIC can be identified through software by viewing the
`chip/Vendor bit in the RevisionId register.
`
`The following values in the chip/Vendor bit identify the ASIC on the NIC:
`
`chip/Vendor Bit Value
`000
`001
`011
`
`ASIC
`3C90xB NICs with the 40-0502-00x ASIC
`3C90xB NICs with the 40-0483-00x ASIC
`3C90xB NICs with the 40-0476-001 ASIC
`
`For more information on the RevisionId register, see “RevisionId” in Chapter 4.
`
`3C90x NICs
`ASIC Diagram
`
`The ASIC used on the 3C90x NICs is shown in Figure 13.
`
`Figure 13 3C90x NICs ASIC Block Diagram
`
`Upload/
`download
`engine
`
`TX/RX
`FIFO block
`
`Mgmt.
`statistics
`
`PCI
`bus
`controller
`
`Transmit/
`receive
`FIFO
`control
`
`10/100
`Mbps
`Ethernet
`MAC
`
`10BASE-T/AUI
`interface
`
`100 Mbps
`signaling
`
`MII
`control
`
`External memory interface
`
`40-0336-00x ASIC
`
`3C90xB NICs
`ASIC Diagrams
`
`The ASICs used by the 3C90xB NICs are shown in Figure 14 through Figure 19.
`
`Figure 14 3C900B NICs ASIC Block Diagram
`
`PCI
`bus
`controller
`
`Download
`engine
`
`Transmit
`FIFO
`
`Upload
`engine
`
`Receive
`FIFO
`
`Mgmt.
`statistics
`
`10 Mbps
`Ethernet
`MAC
`
`Auto-
`negotiation
`
`10BASE-T/AUI
`interface
`
`40-0456-004 ASIC
`
`PALO ALTO NETWORKS Exhibit 1014 Page 28
`
`

`
`ASICs
`
`29
`
`Figure 15 3C905B-TX NIC—40-0502-00x ASIC Block Diagram
`
`Mgmt.
`statistics
`
`Auto-
`negotiation
`
`PCI
`bus
`controller
`
`Download
`engine
`
`Transmit
`FIFO
`
`Upload
`engine
`
`Receive
`FIFO
`
`10/100
`Mbps
`Ethernet
`MAC
`
`10BASE-T/AUI
`interface
`
`100 Mbps
`signaling
`
`MII
`control
`
`40-0502-00x ASIC
`
`Figure 16 3C905B-TX NIC—40-0476-001 AS