_ \
`U
`A
`
`sPTo 38
`5611/2502
`
`PTO/SB/05 (09414)
`’
`Approved for use through 07/31/2006. OMB 0651-0032
`US. Patent and Trademark Office, U.S. DEPARTMENT OF COMMERCE
`Under the Paerwork Reduction Act of 1995 no ersons are reuired to resend to a collection of information unless it disla s a valid OMB control number.
`Unmy
`PATENT APPLICATION 0
`I I
`Partial Block Data Programming...
`(Only fornew nonprovisicnal applications under 37 CFR 1.53(b))
`EV55355-'3274US
`
`
`
`O.Lci"shZavoz
`
`_
`
`Expmss Ma,-I Labe, Na
`
`APPLICATION ELEMENTS
`See MPEP chapter 600 concerning utility patent application contents.
`
`ADDRESS TO:
`
`§f3"?';‘i'°;fl‘:"s?."°' Paws
`Alexandria VA 223134459
`
`.
`Fee Transmittal Form (e.g.. PTOISBI17)
`1.
`(Submit an original and a duplicate forlee processing)
`2. D A licant claims small enti
`status.
`S2: 37 CFR 127’
`ty
`21
`Specification
`[Total Pages
`Both the claims and abstract must start on a new page
`(For inlarmation an the preferred arrangement, see MPEP 603. D1(a))
`Drawing(s) (35 U.S.C. 113)
`[Total Sheets
`9
`
`3.
`
`4.
`
`1:
`
`Acc0MpANY|NG App|_|cAT|oN pART3
`_
`9. D Assignment Papers (cover sheet & documeni(s))
`
`1
`
`Name °f Assignee
`
`;5
`
`[Total Sheets4 1o_ 5 37 CFR 313(5) sgagemeng
`_ Oath or Declaration
`3- - N9W'Y Execuied (Original Oi COPY)
`(when there is an assignee)
`b.
`A copy from a prior application (37 CFR 1.63(d))
`for continuation/divisional with Box 18 completed)
`DELETION OF lNVENTORlS|
`name int e prior application, see 37 C
`Signed Siaiemeni ailached de|E"'19 inV*;T;°T(5)
`1'63(d)(2)and1'33(b)'
`
`Dpower of
`Attorney
`
`11_ |:] English Translation Document (if applicable)
`
`12.
`
`-
`-
`-
`infogtion Disclosure Statement (PTOISBIO8 or PTO-1449)
`Copies of citations attached
`
`i
`
`Application Data Sheet. See 37 CFR1.76
`6.
`7. D CD-ROM or CD-R in duplicate, large table or
`I
`P
`A
`d
`.
`p-;ine1rScar§eg;aarg:e(°p;(J:e)n ix)
`
`8. Nucleotide andlor Amino Acid Sequence Submission
`(if ap licable, items a. - c. are required)
`a.
`Computer Readable Form (CRF)
`A
`
`CD-ROM or CD-R (2 copies); or
`i. E]
`i,‘ D papa,
`.
`
`.
`
`13’ [:1 Preliminary Amendment"
`
`14.
`
`.
`.
`.
`Return Receipt Postcard (MPEP 503)
`(Should be speclficallyltemized)
`-
`
`.
`
`F."'i°"i.W D0?-Umemlsl
`15 CI Celflifiecl COP)’
`(’f f°’e’9’7 p"°"iy '5 c’3'”79d)
`_
`_
`
`_
`
`D
`
`17. D Other:
`
`c. D Statements verifying identity of above copies
`18.-If a CONTINUING APPLICATION. check appmpriate box, and supply the requisite information below and in the first sentence of the
`specification following the title, or in an Application Data Sheet under 37 CFR 1.76:
`
`Continuation
`Prior application inlonnation:
`
`Z Continuation-in-part(ClP)
`D Divisional
`Biaminer Dinh, Ngoc V.
`
`ot pnorappilcation No.:10/841,33.5.................
`Art Unit: 2187
`
`19. CORRESPON DENCE ADDRESS
`
`The address associated with Customer Number:
`
`36257
`
`OR B Correspondence address below
`
`I We —
`Te'eP“°“e —
`
`WN
`
`Registration No.
`Amme /Aem 24,455
`Gerald P. Parsons
`This collection of information is required by 37 CFR ‘l.53(b). The information is required to obtain or retain a benefit by the public which is to file (and by the
`USPTO to process) an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.11 and 1.14. This collection is estimated to take 12 minutes to
`complete, including gathering, preparing, and submitting the completed application torTn to the USPTO. Time will vary depending upon the Individual case. Any
`comments on the amount of time you require to complete this form andlor suggestions tor reducing this burden, should be sent to the Chief information Officer,
`US. Patent and Trademark Office, US. Department of Commerce, PO. Box 1450, Alexandria, VA 22313-1450. DO NOT SEND FEES OR COMPLETED
`FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.0. Box 1450, Alexandria, VA 22313-1450.
`-
`if you need assistance in completing the form, call 1-800-PTO-9199 and select option 2.
`
`ame
`
`APPLE INC.
`EXHIBIT 1202 - PAGE 0001
`
`

`
`Under the Panervvnrk Redtintinn Ar.tnt19.€l5
`
`PTO/SBI17 (12-04v2)
`Approved for use through 07/31/2006. OMB D651-0032
`.
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`nn nersnns: are rennirsirt in rr-iiznnnrl In a nnllentinn nf infnrmatinn unless it disnlavs a valid OMB nnntml numhr-er
`
`Effective on 12/03/2004.
`Fees pursuant to the Consolidated ADDroon'ations Act. 2005 (HR. 4818).
`FEE TRANSMITTAL ’.:.".‘;'::,‘;‘::““““"“
`First Named Inventor Kevin M, Conle
`. Examiner Name
`_
`Art Unit
`
`_
`D Applicant claims small entity status. See 37 CFR 1.27
`
`Complete if Known
`
`TOTAL AMOUNT 0" PAYMENT
`
`($)
`
`1,000.00
`
`Attomey Docket No.
`
`SNDK.156US2
`
`METHOD OF PAYMENT check all that appl
`
`D Check l:l Credit Card lj Money Order B None flOther (please identify):
`Deposit Account Deposit Account Number: 502554
`Deposit Account Name; Parsons Hsue & de Ftuntz
`For the above-identified deposit account, the Director is hereby authorized to: (check all that apply)
`
`El Charge tee(s) indicated below, except for the filing fee
`Chargé feels) l“dl°3led b°l°W
`Charge any additional Iee(s) or underpayments of fee(s) / C ed-‘
`1
`under 37 CFR1.1G and 1.17 _
`r
`I any Ovemaymen S
`WARNING: Information on this form may become public. Credit card information should not be included on this form. Provide credit card
`information and authorization on PTO-2038.
`-
`
`FEE CALCULATION
`
`1. BASIC FILING, SEARCH, AND EXAMINATION FEES
`FILING FEES
`SEARCH FEES
`Small Entit
`S
`ll E T
` .F_e9_l.tt :“¥t=ae(5)
`.F.ee_lfl geet;"i'
`Utility
`300
`150
`500 -
`250
`Design
`200
`100
`100
`so
`Plant
`200
`100
`300
`150
`Reissue
`300
`150
`500
`250
`
`EXAMINATION FEES
`3
`ll E 12'
`
`Fifi) ?t"msaeet;"t'
`200
`100
`130
`65
`150
`go
`600
`
`its
`1 ooo_oo
`
`200
`
`100
`
`Provisional
`2. EXCESS CLAIM FEES
`Fee Description
`Each claim over 20 (including Reissues)
`Each independent claim over 3 (including Reissues)
`Multiple dependent claims
`Fee (§[
`Total Claims
`Extra Claims
`5.0
`X
`__.___3 - 20 Or HP =
`0.
`HP = highest number oftotal claims paid for, if greater than 20.
`Indep. Claims
`Extra Claims
`Fee (§)
`=
`2
`- 3 or HP =
`0
`X
`2_Q0
`HP = highest number of independent claims paid for, it greater than 3.
`
`Fee Paid l§)_
`0.00
`
`Fee Paid (§)
`Q00
`
`o
`
`A
`
`o
`
`0
`
`A
`
`o
`
`
`Fee (§|
`Fglfil
`25
`50
`100
`200
`180
`3 60
`Multiple Dependent Claims
`Zlilliee l
`360
`0.00
`
`.
`_
`3. APPLICATION SIZE FEE
`If the specification and drawings exceed 100 sheets of paper (excluding electronically filed sequence or computer
`listings under 37 CFR l.52(e)), the application size fee clue is $250 ($125 for small entity) for each additional 50
`sheets or fraction thereof. See 35 USC. 4l(a)(l)(G) and 37 CFR l.l6(s).
`Total Sheets
`Extra Sheets
`Number of each additional 50 or fraction thereof
`30
`0
`Q
`(round up to a whole number)
`x
`
`- 100 =
`
`I 50 =
`
`Fee t§)_
`250
`
`Fee Paid Q)
`0,00
`
`4. OTHER FEE(S)
`$130 fee (no small entity discount)
`Non—English Specification,
`Other (e.g., late filing surcharge):
`SUBMITTED BY
`N .
`t"
`R ‘
`'-
` A?i%':‘5A2n.° was
`Date October 13. 2005
`Name (Pun/Type) Gerald P. Parsons
`This collection of information is required by 37 CFR 1.136. The information is required to obtain or retain a benefit by the public which is to tile (and by the
`USPTO to process) an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.14. This collection is estimated to take 30 minutes to complete.
`including gathering, preparing, and submitting the completed application fonn to the USPTO. Time will vary depending upon the individual case, Any comments
`on the amount of time you require to complete this fomi and/or suggestions for reducing this burden. should be sent to the Chief Information Officer, U.S. Patent
`and Trademark Office, U.S. Department of Commerce, P.O. Box 1450, Alexandria, VA 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS
`ADDRESS. SEND TO: Commissioner for Patents, P.0. Box 1450, Alexandria, VA 22313-1450.
`If you need assistance in completing the form, call 1-800-PTO-9199 and select option 2.
`
`P ‘d (Q
`ease‘;
`0,00
`
`F
`
`APPLE INC.
`EXHIBIT 1202 - PAGE 0002
`
`

`
`_ \
`U
`A
`
`sPTo 38
`5611/2502
`
`PTO/SB/05 (09414)
`’
`Approved for use through 07/31/2006. OMB 0651-0032
`US. Patent and Trademark Office, U.S. DEPARTMENT OF COMMERCE
`Under the Paerwork Reduction Act of 1995 no ersons are reuired to resend to a collection of information unless it disla s a valid OMB control number.
`Unmy
`PATENT APPLICATION 0
`I I
`Partial Block Data Programming...
`(Only fornew nonprovisicnal applications under 37 CFR 1.53(b))
`EV55355-'3274US
`
`
`
`O.Lci"shZavoz
`
`_
`
`Expmss Ma,-I Labe, Na
`
`APPLICATION ELEMENTS
`See MPEP chapter 600 concerning utility patent application contents.
`
`ADDRESS TO:
`
`§f3"?';‘i'°;fl‘:"s?."°' Paws
`Alexandria VA 223134459
`
`.
`Fee Transmittal Form (e.g.. PTOISBI17)
`1.
`(Submit an original and a duplicate forlee processing)
`2. D A licant claims small enti
`status.
`S2: 37 CFR 127’
`ty
`21
`Specification
`[Total Pages
`Both the claims and abstract must start on a new page
`(For inlarmation an the preferred arrangement, see MPEP 603. D1(a))
`Drawing(s) (35 U.S.C. 113)
`[Total Sheets
`9
`
`3.
`
`4.
`
`1:
`
`Acc0MpANY|NG App|_|cAT|oN pART3
`_
`9. D Assignment Papers (cover sheet & documeni(s))
`
`1
`
`Name °f Assignee
`
`;5
`
`[Total Sheets4 1o_ 5 37 CFR 313(5) sgagemeng
`_ Oath or Declaration
`3- - N9W'Y Execuied (Original Oi COPY)
`(when there is an assignee)
`b.
`A copy from a prior application (37 CFR 1.63(d))
`for continuation/divisional with Box 18 completed)
`DELETION OF lNVENTORlS|
`name int e prior application, see 37 C
`Signed Siaiemeni ailached de|E"'19 inV*;T;°T(5)
`1'63(d)(2)and1'33(b)'
`
`Dpower of
`Attorney
`
`11_ |:] English Translation Document (if applicable)
`
`12.
`
`-
`-
`-
`infogtion Disclosure Statement (PTOISBIO8 or PTO-1449)
`Copies of citations attached
`
`i
`
`Application Data Sheet. See 37 CFR1.76
`6.
`7. D CD-ROM or CD-R in duplicate, large table or
`I
`P
`A
`d
`.
`p-;ine1rScar§eg;aarg:e(°p;(J:e)n ix)
`
`8. Nucleotide andlor Amino Acid Sequence Submission
`(if ap licable, items a. - c. are required)
`a.
`Computer Readable Form (CRF)
`A
`
`CD-ROM or CD-R (2 copies); or
`i. E]
`i,‘ D papa,
`.
`
`.
`
`13’ [:1 Preliminary Amendment"
`
`14.
`
`.
`.
`.
`Return Receipt Postcard (MPEP 503)
`(Should be speclficallyltemized)
`-
`
`.
`
`F."'i°"i.W D0?-Umemlsl
`15 CI Celflifiecl COP)’
`(’f f°’e’9’7 p"°"iy '5 c’3'”79d)
`_
`_
`
`_
`
`D
`
`17. D Other:
`
`c. D Statements verifying identity of above copies
`18.-If a CONTINUING APPLICATION. check appmpriate box, and supply the requisite information below and in the first sentence of the
`specification following the title, or in an Application Data Sheet under 37 CFR 1.76:
`
`Continuation
`Prior application inlonnation:
`
`Z Continuation-in-part(ClP)
`D Divisional
`Biaminer Dinh, Ngoc V.
`
`ot pnorappilcation No.:10/841,33.5.................
`Art Unit: 2187
`
`19. CORRESPON DENCE ADDRESS
`
`The address associated with Customer Number:
`
`36257
`
`OR B Correspondence address below
`
`I We —
`Te'eP“°“e —
`
`WN
`
`Registration No.
`Amme /Aem 24,455
`Gerald P. Parsons
`This collection of information is required by 37 CFR ‘l.53(b). The information is required to obtain or retain a benefit by the public which is to file (and by the
`USPTO to process) an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.11 and 1.14. This collection is estimated to take 12 minutes to
`complete, including gathering, preparing, and submitting the completed application torTn to the USPTO. Time will vary depending upon the Individual case. Any
`comments on the amount of time you require to complete this form andlor suggestions tor reducing this burden, should be sent to the Chief information Officer,
`US. Patent and Trademark Office, US. Department of Commerce, PO. Box 1450, Alexandria, VA 22313-1450. DO NOT SEND FEES OR COMPLETED
`FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.0. Box 1450, Alexandria, VA 22313-1450.
`-
`if you need assistance in completing the form, call 1-800-PTO-9199 and select option 2.
`
`ame
`
`APPLE INC.
`EXHIBIT 1202 - PAGE 0003
`
`

`
`Under the Panervvnrk Redtintinn Ar.tnt19.€l5
`
`PTO/SBI17 (12-04v2)
`Approved for use through 07/31/2006. OMB D651-0032
`.
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`nn nersnns: are rennirsirt in rr-iiznnnrl In a nnllentinn nf infnrmatinn unless it disnlavs a valid OMB nnntml numhr-er
`
`Effective on 12/03/2004.
`Fees pursuant to the Consolidated ADDroon'ations Act. 2005 (HR. 4818).
`FEE TRANSMITTAL ’.:.".‘;'::,‘;‘::““““"“
`First Named Inventor Kevin M, Conle
`. Examiner Name
`_
`Art Unit
`
`_
`D Applicant claims small entity status. See 37 CFR 1.27
`
`Complete if Known
`
`TOTAL AMOUNT 0" PAYMENT
`
`($)
`
`1,000.00
`
`Attomey Docket No.
`
`SNDK.156US2
`
`METHOD OF PAYMENT check all that appl
`
`D Check l:l Credit Card lj Money Order B None flOther (please identify):
`Deposit Account Deposit Account Number: 502554
`Deposit Account Name; Parsons Hsue & de Ftuntz
`For the above-identified deposit account, the Director is hereby authorized to: (check all that apply)
`
`El Charge tee(s) indicated below, except for the filing fee
`Chargé feels) l“dl°3led b°l°W
`Charge any additional Iee(s) or underpayments of fee(s) / C ed-‘
`1
`under 37 CFR1.1G and 1.17 _
`r
`I any Ovemaymen S
`WARNING: Information on this form may become public. Credit card information should not be included on this form. Provide credit card
`information and authorization on PTO-2038.
`-
`
`FEE CALCULATION
`
`1. BASIC FILING, SEARCH, AND EXAMINATION FEES
`FILING FEES
`SEARCH FEES
`Small Entit
`S
`ll E T
` .F_e9_l.tt :“¥t=ae(5)
`.F.ee_lfl geet;"i'
`Utility
`300
`150
`500 -
`250
`Design
`200
`100
`100
`so
`Plant
`200
`100
`300
`150
`Reissue
`300
`150
`500
`250
`
`EXAMINATION FEES
`3
`ll E 12'
`
`Fifi) ?t"msaeet;"t'
`200
`100
`130
`65
`150
`go
`600
`
`its
`1 ooo_oo
`
`200
`
`100
`
`Provisional
`2. EXCESS CLAIM FEES
`Fee Description
`Each claim over 20 (including Reissues)
`Each independent claim over 3 (including Reissues)
`Multiple dependent claims
`Fee (§[
`Total Claims
`Extra Claims
`5.0
`X
`__.___3 - 20 Or HP =
`0.
`HP = highest number oftotal claims paid for, if greater than 20.
`Indep. Claims
`Extra Claims
`Fee (§)
`=
`2
`- 3 or HP =
`0
`X
`2_Q0
`HP = highest number of independent claims paid for, it greater than 3.
`
`Fee Paid l§)_
`0.00
`
`Fee Paid (§)
`Q00
`
`o
`
`A
`
`o
`
`0
`
`A
`
`o
`
`
`Fee (§|
`Fglfil
`25
`50
`100
`200
`180
`3 60
`Multiple Dependent Claims
`Zlilliee l
`360
`0.00
`
`.
`_
`3. APPLICATION SIZE FEE
`If the specification and drawings exceed 100 sheets of paper (excluding electronically filed sequence or computer
`listings under 37 CFR l.52(e)), the application size fee clue is $250 ($125 for small entity) for each additional 50
`sheets or fraction thereof. See 35 USC. 4l(a)(l)(G) and 37 CFR l.l6(s).
`Total Sheets
`Extra Sheets
`Number of each additional 50 or fraction thereof
`30
`0
`Q
`(round up to a whole number)
`x
`
`- 100 =
`
`I 50 =
`
`Fee t§)_
`250
`
`Fee Paid Q)
`0,00
`
`4. OTHER FEE(S)
`$130 fee (no small entity discount)
`Non—English Specification,
`Other (e.g., late filing surcharge):
`SUBMITTED BY
`N .
`t"
`R ‘
`'-
` A?i%':‘5A2n.° was
`Date October 13. 2005
`Name (Pun/Type) Gerald P. Parsons
`This collection of information is required by 37 CFR 1.136. The information is required to obtain or retain a benefit by the public which is to tile (and by the
`USPTO to process) an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.14. This collection is estimated to take 30 minutes to complete.
`including gathering, preparing, and submitting the completed application fonn to the USPTO. Time will vary depending upon the individual case, Any comments
`on the amount of time you require to complete this fomi and/or suggestions for reducing this burden. should be sent to the Chief Information Officer, U.S. Patent
`and Trademark Office, U.S. Department of Commerce, P.O. Box 1450, Alexandria, VA 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS
`ADDRESS. SEND TO: Commissioner for Patents, P.0. Box 1450, Alexandria, VA 22313-1450.
`If you need assistance in completing the form, call 1-800-PTO-9199 and select option 2.
`
`P ‘d (Q
`ease‘;
`0,00
`
`F
`
`APPLE INC.
`EXHIBIT 1202 - PAGE 0004
`
`

`
`PARTIAL BLOCK DATA PROGRAMMING AND READING
`OPERATIONS IN A NON—VOLATILE MEMORY
`
`Inventorzi
`
`Kevin M. Conley
`
`CROSS-REFERENCE TO RELATED APPLICATION
`
`[0001]
`
`This application is a continuation of application serial no. 10/841,388, filed May
`
`7, 2004, which in turn is a continuation of application serial no. 09/766,436, filed January '19,
`
`2001, now patent no. 6,763,424, which applications are incorporated herein in their entirety by
`
`this reference.
`
`BACKGROUND OF THE INVENTION
`
`[0002]
`
`This invention pertains to the field of semiconductor non-volatile data storage
`
`system architectures and their methods of operation, and has application to data storage systems
`
`based on flash electrically erasable and programmable read—only memories (EEPROMS).
`
`[0003]
`
`A common application of flash EEPROM devices is as a mass data storage
`
`subsystem for electronic devices.
`
`Such subsystems are commonly implemented as either
`
`removable memory cards that can be inserted into multiple host systems or as non-removable
`
`embedded storage within the host system.
`
`In both implementations, the subsystem includes one
`
`or more flash devices and often a subsystem controller.
`
`. [0004]
`
`Flash EEPROM devices are composed of one or more arrays of transistor cells,
`
`each cell capable of non-volatile storage of one or more bits of data. Thus flash memory does.
`
`not require power to retain the data programmed therein. Once programmed however, a cell
`
`must be erased before it can be reprogrammed with a new data value. These arrays of cells are
`
`partitioned into groups to provide for efficient implementation of read, program and erase
`
`functions. A typical flash memory architecture for mass storage arranges large groups of cells
`
`into erasable blocks, wherein a block contains the smallest number of cells (unit of erase) that are
`
`erasable at one time.
`
`Attorney Docket No.: SNDK.156US2
`
`Express Mail No.2 EV663653274US
`
`APPLE INC.
`EXHIBIT 1202 - PAGE 0005
`
`

`
`[0005]
`
`In one commercial form, each block contains enough cells to store one sectorof
`
`user data plus some overhead data related to the user data and/or to the block in which it is
`
`stored. The amount of user data included in a sector is the standard 512 bytes in one class of
`
`such memory systems but can be of some other size. Because the isolation of individual blocks
`
`of cells from one another that is required to make them individually erasable takes space on the
`
`integrated circuit chip, another class of flash memories makes the blocks significantly larger so
`
`there is less space required for such isolation. But since it is also desired to handle user data in
`
`much smaller sectors, ‘each large block is often further partitioned into individually addressable
`
`pages that are thebasic [unit for reading and programming user data (unit of programming and/or
`reading). Each page usually stores one sector of user data, but a page may store a partial sector
`
`or multiple sectors. A “sector” is used herein to refer to an amount of user data that is transferred
`
`to and from the host as a unit.
`
`[0006]
`
`The subsystem controller in a large block system perfonns a number of functions
`
`including the translation between logical addresses (LBAs) received by the memory sub-system
`from a host, and physical block numbers (PBNS) and page addresses within the memory cell
`
`array. This translation often involves use of intermediate terms for a logical block number
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`(LBN) and logical page. The controller also manages the low level flash circuit operation
`
`through a series of commands that it issues to the flash memory devices via an interface bus.
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`Another function the controller performs is to maintain the integrity of data stored to the
`
`subsystem through various means, such as by using an error correction code (ECC).
`
`[0007]
`
`In an ideal case, the datain all the pages of a block are usually updated together
`
`by, writing the updated data to the pages within an unassigned, erased block, and a logical—t0—
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`physical block number table is updated with the new address The original block is then available
`
`to be erased. However, it is more typical that the data stored in a number of pages less than all of
`
`the pages within a given block must be updated. The data stored in the remaining pages of the
`
`given block remains unchanged. The probability of this occurring is higher in systems where the
`number of sectors of data stored per block is higher. One technique now used to accomplish
`
`such a partial block update is to write the data of the pages to be updated into a corresponding
`
`number of the pages of an unused erased block and then copy the unchanged pages from the
`original block into pages of the new block. The original block may then be erased and added to
`
`Attorney Docket No.: SNDK.156US2
`
`Express Mail No.: EV663653274US
`
`APPLE INC.
`EXHIBIT 1202 - PAGE 0006
`
`

`
`an inventory of unused blocks in which data may later be programmed. Another technique
`
`similarly writes the updated pages to a new block but eliminates the need to copy the other pages
`
`of data into the new block by changing the flags of the pages in the original block which are
`
`being updated to indicate they contain obsolete data. Then‘ when the data are read, the updated
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`data read from pages of the new block are combined with the unchanged data read from pages of
`the original block that are not flagged as obsolete.
`
`SUMMARY OF THE INVENTION
`
`[0008]
`
`According to one principal aspect of the present invention, briefly and generally,
`
`both the copying of unchanged data from the original to the new blocks and the need to update
`
`flags within the original block are avoided when the data of fewer than all of the pages within a
`
`block are being updated. This is accomplished by maintaining both the superceded data pages
`and the updated pages of data with a common logical address. The original and updated pages of ,
`
`data are then distinguished by the relative order in which they were programmed. During
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`reading, the most recent data stored in the pages having the same logical address are combined
`
`with the unchanged pages of data while data in the original versions of the updated pages are
`
`ignored. The updated data can be written to either pages within a different block than the
`original data, or
`to available unused pages within the same block.
`In one ‘specific
`
`implementation, a form of time stamp is stored with each page of data that allows determining
`
`the relative order that pages with the same logical address were written.
`
`In another specific
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`implementation, in a system where pages are programmed in a particular order within the blocks,
`
`a form of time stamp is stored with each block of data, and the most recent copy of a page within
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`a block is established byits physical location within the block.
`
`[0009]
`
`These techniques avoid both the necessity for copying unchanged data from the
`
`original to new block and the need to change a flag or other data in the pages of the original
`
`block whose data have been updated. By not having to change a flag or other data in the
`
`superceded pages, a potential of disturbing the previously written data in adjacent pages of that
`same block that can occur from such a writing operation is eliminated. Also, a performance
`
`penalty of the additional program operation is avoided.
`
`Attorney Docket No.: SNDK.l56US2
`
`Express Mail No.2 EV663653274US
`
`APPLE INC.
`EXHIBIT 1202 - PAGE 0007
`
`

`
`[0010]
`
`A further operational feature, which may be used in conjunction with the above
`
`summarized techniques, keeps track of the logical offset of individual pages of data within the
`
`individual memory cell blocks, so that the updated data need not be stored with the same
`
`physical page offset as the superceded data. This allows more efficient use of the pages of new
`
`blocks, and even allows the updated data to be stored in any erasedpages of the same block as
`
`the superceded data.
`
`_
`
`[0011]
`
`0
`
`Another principal aspect of the present invention groups together two or more
`
`blocks positioned in separate units of the memory array .(also termed “sub-arrays”)
`
`for
`
`programming and reading together as part of a single operation. Such a multiple block group is
`referenced herein as a ”metablock.” Its component blocks may be either all located on a single
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`memory integrated circuit chip, or, in systems using more than one such‘ chip, -located on two or
`
`more different chips. When data in fewer than all of the pages of one of these blocks is updated,
`
`the use of another block in that same unit is normally required.
`
`Indeed, the techniques described
`
`above, or others, may be employed separately with each block of the metablock. Therefore,
`
`when data within pages of more than one block of the metablock are updated, pages within more
`than one additional block are required to be used.
`If there are four blocks of four different
`
`memory units that form the metablock, for example, there is some probability that up to an
`
`additional four blocks, one in each of the units, will be used to store updated pages of the original
`blocks. One update block is potentially required in each unit for each block of the original
`
`metablock.
`
`In addition, according. to’ the present invention, updated data from pages of more
`
`than one of the-blocks in the metablock can be stored in pages of a common block in only one of
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`the units. This significantly reduces the number of unused erased blocks that are needed to store
`
`updated data, thereby making more efficient use of the available memory cell blocks to store
`
`data. This technique is particularly useful when the memory system frequently updates single
`
`pages from a metablock.
`
`[0012]
`
`Additional aspects, features and advantages of the present invention are included
`
`in the following description of exemplary embodiments, which description should be read in
`
`conjunction with the accompanying drawings.
`
`Attorney Docket No.2 SNDK.l 56US2
`
`Express Mail No.: EV663653274US
`
`APPLE INC.
`EXHIBIT 1202 - PAGE 0008
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`

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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0013]
`
`Figure 1 is a block diagram of a typical prior art flash EEPROM memory array
`
`with memory control logic, data and address registers;
`
`[0014]
`
`Figure 2 illustrates an architecture utilizing memories of Figure l with a system
`
`controller;
`
`[0015]
`Figure 3 is a timing diagram showing a typical copy operation of the memory
`system of Figure .2;
`0
`
`[0016]
`
`.
`
`Figure 4 illustrates an existing process of updating data in less than all of the
`
`pages of a multi-paged block;
`
`[0017]
`
`Figures 5A and 5B are tables of corresponding logical and physical block
`
`addresses for each of the original and new blocks of Figure 4, respectively;
`
`[0018]
`
`Figure 6 illustrates another existing process of updating data in less than all of the
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`pages of a multi-paged block;
`
`[0019]
`
`Figures 7A and 7B are tables of corresponding logical and physical page
`
`addresses for the original and new blocks of Figure 6, respectively;
`
`[0020]
`
`Figure 8] illustrates an example of an improved process of updating data in less
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`than all of the pages of a multi-paged block;
`
`‘[0021]
`
`Figure 9 is a table of corresponding logical and physical page numbers for the
`
`new block ofFigure 8;
`
`[0022] 7
`
`Figure 10 provides an example of a layout of the data in a page shown in Figure
`
`8;
`
`V
`
`[0023]
`
`Figure 11 illustrates a further development of the example of Figure 8;
`
`[0024]
`
`Figure 12 is a table of corresponding logical and physical page numbers for the
`
`new block of Figure 11;
`
`Attorney Docket No.: SNDK.l56US2
`
`Express Mail No.: EV663653274US
`
`APPLE INC.
`EXHIBIT 1202 - PAGE 0009
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`

`
`[0025]
`
`Figure 13 illustrates one way to read the updated data in the blocks of Figure l 1;
`
`[0026]
`
`Figure 14 is a flow diagram of a processof programming data into a memory
`
`system organized as illustrated in Figures 8 and 9;
`
`[0027]
`
`Figure 15 illustrates an existing multi—unit memory with blocks from the
`
`individual units being linked together into a metablock and
`
`[0028]
`
`Figure 16‘i11ustrates an improved method of updating data of a metablock in the
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`multi-unit memory of Figure 12 when the amount of updated data is much less that the data
`
`storage capacity of the metablock.
`
`DESCRIPTION OF EXISTING LARGE BLOCK MANAGEMENT TECHNIQUES
`
`[0029]
`
`Figure 1 shows a typical flash memory device internal architecture. The primary
`
`features include an input/output (I/O) bus 411 and control signals 412 to interface to an external
`
`controller, a memory control circuit 450 to control internal memory operations with registers for
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`command, address and status signals. One or more arrays 400 of flash EEPROM cells are
`
`included, each array having its own row decoder (XDEC) 401 and column decoder (YDEC) 402,
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`a group of sense amplifiers and program control circuitry (SA/PROG) 454 and a data register
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`404. Presently,
`
`the memory cells usually include one or more conductive floating gates as
`
`storage elements but other long term electron charge storage elements may be used instead. The
`
`memory cell array may be operated with two levels of charge defined for each storage element to
`therefore store one bit of data with each element. Alternatively, more than two storage states
`
`may be defined for each storage element, in which case more than one bit of data is stored in
`
`each element.
`
`[0030]
`
`If desired, a plurality of arrays 400, together with related X decoders, Y decoders,
`
`prograrn/verified circuitry, data registers, and the like are provided, for example as taught by
`
`U.S. Patent 5,890,192, issued ,March 30, 1999, and assigned to Sandisk Corporation, the assignee
`of this application, which is hereby incorporated by this reference. Related memory system
`
`features are described in co-pending patent application serial no. 09/505,555, filed February 17,
`
`Attorney Docket No.: SNDK.156US2
`
`Express Mail No.: EV663653274US
`
`APPLE INC.
`EXHIBIT 1202 - PAGE 0010
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`

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`2000 by Kevin Conley et ‘al., which application is expressly incorporated herein by this
`
`reference.
`
`[0031]
`
`The external
`
`interface I/O bus 411 and control signals 412 can include the
`
`following:
`
`CS - Chip Select.
`
`Used to activate flash memory interface.
`
`RS - Read Strobe.
`
`Used to indicate the I/O bus is being used to transfer data
`
`.
`
`from the memory array.
`
`WS - Write Strobe.
`
`Used to indicate the I/O bus is being used to transfer data to
`
`the memory array.
`
`AS — Address Strobe.
`
`Indicates that the I/O bus is being used to transfer address
`
`information.
`
`AD[7:0] _— Address/Data Bus This I/O bus is used to transfer data between controller and
`
`the flash memory command, address and data registers of
`
`the memory control 450.
`
`[0032]
`
`This interface is given only as an example as other signal configurations can be
`
`used to give the same functionality. Figure 1 shows only one flash memory array 400 with its
`
`related components, but a multiplicity of such arrays can exist on a single flash memory chip that
`
`share a common interface and memory control circuitry but have separate XDEC, YDEC,
`
`SA/PROG and DATA REG circuitry in order to allow parallel read and program operations.
`
`[0033]
`
`Data is transferred from the memory array through the data register 404 to an
`
`external controller via the data registers’ coupling to the I/O bus AD[7:0] 41 l. The data register
`
`404 is also coupled the sense amplifier/programming circuit 454. The number of elements of the
`data register coupled to each sense amplifier/programming circuit element may depend on/the
`number of bits stored in each storage element of the memory cells, flash EEPROM cells each
`
`containing one or more floating gates as the storage elements. Each storage element may store a
`
`plurality of bits, such as 2 or 4, if the memory cells are operated in a multi-state mode.
`
`Alternatively, the memory cells may be operated in a binary mode to store one bit of data per
`
`storage element.
`
`Attorney Docket No.: SNDK.l56US2
`
`Express Mail No.: EV663653274US
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`APPLE INC.
`EXHIBIT 1202 - PAGE 0011
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`

`
`The row decoder 401 decodes row addresses for the array 400 in order to select
`[0034]
`the physical page to be accessed. The row decoder 401 receives row addresses via internal row
`
`address lines 419 from the memory control logic 450. A column decoder 402 receives column
`addresses via internal column address lines 429 from the memory control logic 450.
`
`[0035]
`
`Figure 2 shows an architecture of a typical non-volatile data storage system, in
`
`In one form, this system is
`this case employing flash memory cells as the storage media.
`encapsulated within a removable card having an electrical connector extending along one side to
`
`provide the host interface when inserted into a receptacle of a host. Alternatively, the system of
`Figure 2 may be embedded into a host system in the form of a permanently installed embedded
`
`circuit or otherwise. The system utilizes a single controller 301 that performs high level host and
`
`memory control functions. The flash memory media is composed of one or more flash memory
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`devices, each such device often formed on its own integrated circuit chip. The system control