UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_______________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_______________
`
`
`
`
`
`APPLE INC.
`Petitioner
`
`v.
`
`LONGITUDE FLASH MEMORY SYSTEMS S.A.R.L.
`Patent Owner
`
`_______________
`
`Case IPR2015-01949
`Patent 7,818,490
`
`_______________
`
`
`
`PATENT OWNER LONGITUDE FLASH MEMORY SYSTEMS S.A.R.L.
`AND EXCLUSIVE LICENSEE LONGITUDE LICENSING LTD.’S
`PRELIMINARY RESPONSE
` 
`
` 
`
`

`
`Table of Contents
`
`A. 
`B. 
`
`
`I. 
`Introduction ...................................................................................................... 1 
`II.  Background ....................................................................................................... 2 
`A.  About U.S. Patent No. 7,818,490 (the “‘490 patent”) .................................. 2 
`B. 
`Petitioner’s Grounds of Challenge ................................................................ 9 
`III.  Claim Construction ......................................................................................... 11 
`A. 
`Petitioner’s Proposed Construction Is Unsupported ................................... 11 
`IV.  The Petitioner Does Not Demonstrate That It Is More Likely Than Not to
`Prevail On Any Challenged Claim on the ‘490 Patent .................................. 13 
`Petitioner Improperly Circumvents the Board’s Page Limit Rule .............. 13 
`Petitioner Fails to Demonstrate That Niijima Anticipates Claims 34-38, 40,
`41, 43-45, 50-57, and 59-64 or Renders Those Claims Obvious in View of
`the Knowledge of a Person of Ordinary Skill in the Art (Ground 1) ......... 17 
`  Petitioner Improperly Conflates Multiple Embodiments in Niijima .......... 18 1.
`
`
`  The Petitioner Fails To Demonstrate That Niijima in View of the 2.
`Knowledge of a Person of Ordinary Skill in the Art Discloses
`Programming Individual Ones of a Second Plurality of Pages in a Second
`Block with Updated Data as Required by Independent Claims 34 and 52 . 22 
`
`  The Petitioner Fails To Demonstrate That Niijima in View of the 3.
`Knowledge of a Person of Ordinary Skill in the Art Discloses
`“programming the updated version of the original data in those of the
`second plurality of pages that have different offset positions within the
`second block than the offset positions of the first plurality of pages within
`said at least the first block,” As Recited In Independent Claims 34 and 52
` ..................................................................................................................... 25 
`
`  The Petitioner Fails To Demonstrate That Niijima in View of the 4.
`Knowledge of a Person of Ordinary Skill in the Art Discloses the
`“organizing” Required By Claims 34-36 and 52-54 ................................... 28 
`
`  The Petitioner Fails To Demonstrate That Niijima in View of the 5.
`Knowledge of a Person of Ordinary Skill in the Art Discloses
`
`ii
` 
`
`

`
`“programming the individual pages with an indication of a relative time of
`programming the data therein,” As Recited In Claim 37 ........................... 32 
`
`  The Petitioner Fails To Demonstrate That Niijima in View of the 6.
`Knowledge of a Person of Ordinary Skill in the Art Discloses That The
`Logical Addresses Include a Logical Block Number and a Logical Page
`Offset, As Required By Claims 40, 56, 60, and 62 ..................................... 34 
`
`  The Petitioner Fails To Demonstrate That Niijima in View of the 7.
`Knowledge of a Person of Ordinary Skill in the Art Discloses
`Programming Logical Addresses Within Pages In Which the Pages of
`Updated or Original Data Are Programmed, As Required By Claims 41
`and 57 .......................................................................................................... 36 
`
`  The Petitioner Fails To Demonstrate That Niijima in View of the 8.
`Knowledge of a Person of Ordinary Skill in the Art Discloses “wherein
`organizing pages of the read data comprises writing the pages of read data
`into a volatile memory within the memory system,” As Recited In Claims
`45, 51, and 64 .............................................................................................. 38 
`The Petitioner Fails To Demonstrate That Niijima in View of Wells
`Renders Obvious Claims 42 and 58 (Ground 2) ......................................... 40 
`
`  The Petitioner Fails To Demonstrate That Niijima in View of Wells 1.
`Discloses That “units are physically separate groupings of blocks of charge
`storage elements in which programming operations may be performed
`independently,” As Recited In Claims 42 and 58. ...................................... 40 
`
`  The Petitioner Fails To Demonstrate That Niijima in View of Wells 2.
`Discloses “linking the first and third blocks together as a metablock,” As
`Recited In Claims 42 and 58. ...................................................................... 42 
`D.  The Petitioner Fails To Demonstrate That Niijima and the Admitted Prior
`Art or Cappelletti Renders Obvious Claims 46 and 47 (Ground 3) ........... 43 
`E.  Grounds 4 and 5 .......................................................................................... 45 
`F. 
`The Petitioner Fails To Demonstrate That Niijima and Wells, and the
`Knowledge of One of Ordinary Skill in the Art, Hazen, or Dipert, Render
`Obvious Claims 42 and 58 (Ground 6) ....................................................... 45 
`G.  Reservation of Argument Regarding Other Deficiencies ........................... 46 
`
`C. 
`
`iii
` 
`
`

`
`V.  Conclusion ...................................................................................................... 47 
`
`Conclusion .................................................................................................... ..47
`
`V.
`
`iv
`iv
` 
`
`
`
`
`
`

`
`
`Cases 
`
`Table of Authorities
`
`Continental Can Co. v. Monsanto Co., 948 F.2d 1264 (Fed. Cir. 1991) ................ 27
`Corning Incorporated v. DSM IP Assets B.V., IPR 2013-00048, paper 94 (PTAB
`5/9/2014) ............................................................................................................... 28
`Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966) ............................. 18
`In re Oelrich, 666 F.2d 578 (CCPA 1981) .............................................................. 27
`In re Rijckaert, 9 F.3d 1531 (Fed. Cir. 1993) .......................................................... 27
`In re Translogic Tech., Inc., 504 F.3d 1249 (Fed. Cir. 2007) ................................. 11
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007) ................................................ 18
`MEHL/Biophile Int’l Corp. v. Milgraum, 192 F.3d 1362 (Fed. Cir. 1999) ............. 27
`Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359 (Fed. Cir. 2008) ........ 17, 19, 20
`Nvidia Corp. v. Samsung Electronics Co., Ltd., IPR2015-01318, paper 8 (PTAB
`12/7/2015) ...................................................................................................... 19, 20
`OSRAM Sylvania, Inc. v. Am. Induction Techs., Inc., 701 F.3d 698 (Fed. Cir. 2012)
` ............................................................................................................................... 18
`SanDisk Corp. v. Kingston Tech. Co., 2011 U.S. Dist. LEXIS 27696 (W.D. Wis.
`Mar. 15, 2011) ................................................................................................ vii, 21
`SanDisk Corp. v. Kingston Tech. Co., 695 F.3d 1348 (Fed. Cir. 2012) .................. 33
`Verdegaal Bros. v. Union Oil Co. of California, 814 F.2d 628 (Fed. Cir. 1987) .... 17
`VMware, Inc. v. Electronics and Telecommunications Research Institute, IPR2014-
`00901, paper 7 (PTAB 7/14/2014) ....................................................................... 14
`Statutes 
`
`35 U.S.C. § 102(b) ..................................................................................................... 9
`35 U.S.C. § 103(a) ................................................................................................... 10
`35 U.S.C. § 314(a) ........................................................................................ 1, 13, 47
`Other Authorities 
`
`M.P.E.P. § 2112 (IV) ............................................................................................... 26
`M.P.E.P. § 2131 ....................................................................................................... 17
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48756 (Aug. 14, 2012) ............... 11
`
`v
` 
`
`

`
`Rules 
`
`37 C.F.R. § 42.22(a)(2) .............................................................................................. 2
`37 C.F.R. § 42.24(a)(1) ............................................................................................ 17
`37 C.F.R. § 42.65(a) ............................................................................................ 1, 28
`35 U.S.C. § 102 ................................................................................................... 9, 17
`37 C.F.R. § 42.100(b) .............................................................................................. 11
`37 C.F.R. § 42.104(b)(4) ............................................................................................ 2
`37 C.F.R. § 42.104(b)(5) ............................................................................................ 2
`Fed. R. Evid. 705 ..................................................................................................... 28
`
`
`
`
`
`vi
` 
`
`

`
`LIST OF PATENT OWNER’S EXHIBITS
`
`
`
`Description
`
`Claim Construction Opinion and Order, SanDisk Corp. v.
`Kingston Tech. Co., 2011 U.S. Dist. LEXIS 27696 (W.D. Wis.
`Mar. 15, 2011)
`
`
`
`
`Exhibit
`
`2001
`
`
`
`vii
` 
`
`

`
`I.
`
`Introduction
`
`The Petition for inter partes review of U.S. Patent No. 7,818,490 (“the ’490
`
`patent”) should be denied and no trial instituted because there is no “reasonable
`
`likelihood that the petitioner would prevail with respect to at least one of the
`
`claims challenged in the petition.” 35 U.S.C. § 314(a).
`
`The Petition presents grounds for challenge against claims 34-38 and 40-64
`
`of the ‘490 patent based on anticipation and/or obviousness. But many of these
`
`grounds improperly rely on the doctrine of inherency without factual support for
`
`Petitioner’s allegations. Additionally, the Petitioner’s obviousness-based
`
`challenges not only fail to reach every feature of the challenged claims, they also
`
`lack sufficient rationale for why a person of ordinary skill in the art would have
`
`modified the prior art to disclose or suggest the challenged claims. And Petitioner’s
`
`expert testimony often fails to “disclose the underlying facts or data” on which it is
`
`based, in violation of 37 C.F.R. § 42.65(a), and instead simply repeats unsupported
`
`attorney argument and conclusions presented by Petitioner. Moreover, Petitioner
`
`habitually and improperly points to separate embodiments in a single reference,
`
`neither of which discloses all claim elements as arranged in the claim, to support
`
`allegations of anticipation. Petitioner similarly conflates different embodiments in
`
`the same reference to support obviousness allegations. But those allegations are
`
`void of support or evidence for combining the separate embodiments. As such,
`
` 
`
`1
`
`

`
`Petitioner does not meet its burden in establishing a reasonable likelihood of
`
`success.
`
`Further, the Petition is in violation of the Board’s governing requirements,
`
`including those set forth in 37 C.F.R. §§ 42.22(a)(2), 42.104(b)(4), and
`
`42.104(b)(5). Under these requirements, the Petition must include a detailed
`
`explanation of the significance and relevance of the evidence; and the Petition
`
`must specify where each element of the challenged claims is found in the prior art.
`
`II. Background
`
`A. About U.S. Patent No. 7,818,490 (the “‘490 patent”)
`
`The ‘490 patent is entitled “PARTIAL BLOCK DATA PROGRAMMING
`
`AND READING OPERATIONS IN A NON-VOLATILE MEMORY,” and it
`
`discloses techniques for updating data in less than all of the pages of a non-volatile
`
`memory block by programming new data in unused pages of either the same or
`
`another block. Ex. 1101 at Abstract. The ‘490 patent was filed as U.S. Patent
`
`Application No. 11/250,238 on October 13, 2005 and was issued on October 19,
`
`2010. The ‘490 patent claims priority to and the benefit of U.S. Patent Application
`
`No. 09/766,436, filed on January 19, 2001, now U.S. Patent No. 6,763,424.
`
`Flash memory devices comprise one or more arrays of transistor cells, each
`
`cell capable of non-volatile storage of one or more bits of data so that power is not
`
`required to retain the data programmed therein. Ex. 1101 at 1:29-32. Once a cell is
`
`2
` 
`
`

`
`programmed, it must be erased before it can be reprogrammed with new data. Id. at
`
`1:33-34. Typical flash memory arranges large groups of cells into erasable blocks,
`
`wherein a block contains the smallest number of cells that are erasable at one time.
`
`Id. at 1:36-40. Blocks are often partitioned into individually addressable pages that
`
`are the basic unit for programming user data. Id. at 1:51-55.
`
`Ideally, the data in all of the pages in a block are updated together by
`
`programming the updated data into the pages of an erased block. Ex. 1101 at 2:4-7.
`
`However, it is more typical that data in less than all of the pages in a block are
`
`updated while the data in the remaining pages of that block remain unchanged. Id.
`
`at 2:8-12. This typical update is sometimes referred to as a partial block update. Id.
`
`at 2:14-18.
`
`The ‘490 patent describes two prior art techniques for performing partial
`
`block updates. Ex. 1101 at 2:14-28. In the first prior art technique, data of the
`
`pages to be updated are written into a corresponding number of pages in an unused
`
`erased block. Id. at 2:14-20. The unchanged pages from the original block are then
`
`copied into pages of the new block (e.g., the previously unused erased block). Id.
`
`The original block may then be erased. Id. at 2:18-20. This first prior art technique
`
`has problems. Notably, copying unchanged pages from the original block to the
`
`new block greatly reduces the write performance and usable lifetime of the storage
`
`system. Id. at 5:67-6:5.
`
`3
` 
`
`

`
`In the second prior art technique described by the ‘490 patent, updated pages
`
`are also written to a new block, but the need to copy unchanged pages of the
`
`original block into the new block is eliminated. Ex. 1101 at 2:20-25. This need is
`
`eliminated through the use of flags associated with each page. Id. When updated
`
`data is written to a new block, the flags of pages in the original block which
`
`correspond to the updated data are updated to indicate that they now contain
`
`obsolete (invalid) data. Id. This second prior art technique suffers from limitations
`
`as well. To program obsolete flags in pages where the data has been superceded
`
`requires that a page support multiple programming cycles. Id. at 6:61-63. And in
`
`some cases, memory systems do not permit additional cycles. Id. at 7:4-7.
`
`Moreover, blocks in a system that uses obsolete flags must support the ability to
`
`program a page when other pages in the block with higher offsets or addresses
`
`have already been programmed. Id. at 6:66-7:1. However, a limitation of some
`
`flash memories prevents the usage of obsolete flags by specifying that the pages in
`
`a block can only be programmed in a physically sequential manner. Id. at 7:1-4.
`
`One additional problem with some systems that use obsolete flags is that
`
`allowing those flags to be written in pages whose data is being superceded can
`
`disturb data in other pages of the same block that remain current. Id. at 7:23-26.
`
`NAND type flash memory is particularly susceptible to such disturbs when being
`
`4
` 
`
`

`
`operated in a multi-state mode to store more than one bit of data in each cell. Id. at
`
`7:31-34.
`
`The ‘490 patent presents several solutions to the problems of the prior art. In
`
`these solutions, pages containing updated data are assigned the same logical
`
`address as the pages whose data has been superceded. Ex. 1101 at 7:55-58. Rather
`
`than using obsolete flags to tag the pages whose data has been superceded, the
`
`memory controller distinguishes the pages with updated data from those with
`
`superceded data by keeping track of the order in which the page having the same
`
`logical address were written. Id. at 7:58-67. The controller can do so, for example,
`
`using a counter or time stamp. Id. at 7:58-67, 8:34-55. Alternatively, when pages
`
`are written in order within blocks from the lowest to highest physical page address,
`
`the controller can identify the most recent copy of data by checking the physical
`
`addresses of the pages that contain the updated and superceded data. Id. at 7:58-67.
`
`In this case, the higher physical address contains the most recent copy of the data.
`
`Id.
`
`FIG. 8 of the ‘490 shows an exemplary implementation.
`
`5
` 
`
`

`
`
`
`In this example, new data 37 for each of pages 3-5 of block 35 is written into
`
`three pages (0-2) of a new block 39 that has been previously erased. Ex. 1101 at
`
`8:10-13, FIG. 8. Pages 3-5 from block 35 is thus now superceded by pages 0-2
`
`from new block 39. Pages 3-5 from block 35 also have the same logical address as
`
`pages 0-2 from new block 39. Id. at 8:13-16. In order for the memory controller to
`
`determine whether pages 3-5 from block 35 or pages 0-2 from new block 39
`
`contains the updated data, each page contains an overhead field 43 that provides an
`
`indication of its relative time of programming. Id. at 8:26-33. The memory
`
`6
` 
`
`

`
`controller can thus use the overhead field when called upon to read the data, and
`
`assemble data from the identified new pages in new block 39 along with original
`
`data that has not been updated from block 35. Id. at 8:56-63.
`
`The example of FIG. 8 also shows that the pages with the updated data are
`
`stored in the first three pages (0-2) of new block 39, rather than in the same pages
`
`(3-5) as in block 35. Id. at 8:64-67. In other words, the respective pages have
`
`different offset positions. This is made possible by keeping track of the individual
`
`logical page numbers. Id. at 8:67-9:3. Pages of updated data can also be written to
`
`erased pages of the same block as the page of data being superceded. Id. at 9:4-5.
`
`The ‘490 patent also discloses the use of metablocks to improve
`
`performance by reducing programming time. Ex. 1101 at 11:53-55. One
`
`implementation divides the memory array into largely independent sub-arrays or
`
`units. Id. at 11:55-59. Each unit is divided into a large number of blocks, where
`
`each block is the smallest erasable group of the memory array. Id. at 11:55-59,
`
`12:1-6. Fig. 16 depicts one embodiment of a metablock operation in the ‘490
`
`patent.
`
`7
` 
`
`

`
`
`
`In Fig. 16, blocks 85-88 in a plurality of sub-arrays (units) 80-83 comprise a
`
`metablock. Ex. 1101 at 11:55-59, 11:67-12:1, 12:6-11. A programming operation
`
`of the metablock may include simultaneously programming data into at least one
`
`page of each of the blocks 85-88. Id. at 12:6-11. Partial block updates of a
`
`metablock can be done for individual blocks of a metablock in the same manner
`
`described above with respect to Fig. 8. Id. at 12:13-18.
`
`In the embodiment of Fig. 16, in order to reduce the number of blocks
`
`required for partial block updates, updates to pages of data within this metablock
`
`are made to a single block 90 that is not part of the metablock but within one of the
`
`sub-arrays. Id. at 12:27-32.
`
`Other embodiments disclosed in the specification describe performing
`
`partial block updates by programming updated data to multiple blocks in different
`
`sub-arrays within a metablock. Id. at 3:17-25, 12:13-26. Fig 15 provides an
`
`exemplary depiction of this operation.
`
`8
` 
`
`

`
`
`
`B.
`
`Petitioner’s Grounds of Challenge
`
`The Petitioner challenges the validity of claims 34-38 and 40-64 of the ‘490
`
`patent. Notwithstanding the Petitioner’s insufficient allegations of inherency and
`
`unsupported combinations of references, the cited art fails to disclose many of the
`
`features recited in the claims. The asserted grounds identified in the Petition rely
`
`upon seven prior art references, including so-called Admitted Prior Art identified
`
`in the ‘490 patent. The Petitioner also relies upon the Declaration of Dr. Vivek
`
`Subramanian (“Subramanian Decl.”) (Ex. 1103).
`
`The asserted grounds of rejection are as follows:
`
`Ground Basis
`
`Reference
`
`1
`
`Anticipation under 35
`U.S.C. § 102(b) or
`Obviousness under
`U.S.C. § 103(a) of
`Claims 34-38, 40, 41,
`43-45, 50-57 and 59-64
`
`U.S. Patent No. 5,457,658 to Niijima (Ex.
`1106) (“Niijima”) + Knowledge of a Person
`of Ordinary Skill in the Art
`
`9
` 
`
`

`
`2
`
`3
`
`4
`
`5
`
`6
`
`
`
`Obviousness under 35
`U.S.C. § 103(a) of
`Claims 42 and 58
`Obviousness under 35
`U.S.C. § 103(a) of
`Claims 46 and 47
`Obviousness under 35
`U.S.C. § 103(a) of Claim
`48
`Obviousness under 35
`U.S.C. § 103(a) of Claim
`49
`Obviousness under 35
`U.S.C. § 103(a) of
`Claims 42 and 58
`
`Niijima + U.S. Patent No. 5,822,781 to Wells
`(Ex. 1105) (“Wells”)
`
`Niijima + Admitted Prior Art + “Flash
`Memories,” edited by Cappelletti et al. (Ex.
`1108) (“Cappelletti”)
`Niijima + Admitted Prior Art + Cappelletti
`
`Niijima + Admitted Prior Art + PC Card
`Standard, Volumes 1 and 3 (Ex. 1109) (“PC
`Card Standard”)
`Niijima + Wells + Knowledge of a Person of
`Ordinary Skill in the Art + WO 99/35650
`(Ex. 1110) (“Hazen”) + “Designing with
`Flash Memory,” Dipert et al. (Ex. 1111)
`(“Dipert”)
`
`Throughout this Preliminary Response, for ease of understanding, the Patent
`
`Owner will refer to these prior art references by the names indicated above.1 These
`
`prior art references are described below at Section IV, in conjunction with the
`
`arguments presented in this Preliminary Response.2
`
`                                                            
`1 Patent Owner notes that Niijima and Wells were considered by the U.S. Patent
`
`Office (“PTO”) during the prosecution of the ‘490 patent. The PTO was right to
`
`allow the ‘490 patent over these references.
`
`2
`
` Patent Owner reserves its right to present further argument and evidence related
`
`to these prior art references and the content of the Petition and supporting Exhibits
`
`10
` 
`
`

`
`III. Claim Construction
`
`The standard for construing claim terms in this proceeding is not in dispute.
`
`Since the ‘490 patent is not expired, the Board will interpret claims using the
`
`broadest reasonable interpretation as understood by one of ordinary skill in the art
`
`and consistent with the disclosure (“BRI”). See Office Patent Trial Practice Guide,
`
`77 Fed. Reg. 48756, 48766 (Aug. 14, 2012) (“Office Patent Trial Practice Guide”);
`
`37 C.F.R. § 42.100(b). Under the BRI analysis, claim terms are given their
`
`ordinary and customary meaning, as would be understood by one of ordinary skill
`
`in the art at the time of the invention. In re Translogic Tech., Inc., 504 F.3d 1249,
`
`1257 (Fed. Cir. 2007).
`
` 
`
`A.
`
`Petitioner’s Proposed Construction Is Unsupported
`
`The Petitioner proposes that the term “metablock” be construed to mean “set
`
`of blocks associated together such that during operation they are programmed,
`
`read, or erased together as a unit.” Petition at 10. The Petitioner, however, does not
`
`provide any support whatsoever for its construction. Id. The Petitioner’s
`
`unsupported construction is inconsistent with the BRI for that term. Instead, Patent
`
`Owner believes that “metablock” should be construed to mean “two or more
`                                                                                                                                                                                                
`later in this proceeding, consistent with the Board’s Rules and practice. No waiver
`
`is intended by any argument withheld by Patent Owner at this stage of the
`
`proceeding.
`
`11
` 
`
`

`
`blocks positioned in separate units of one or more memory chips for programming
`
`and reading together in parallel as part of a single operation.”
`
`Patent Owner’s proposed construction adopts the inventor’s lexicography for
`
`a “metablock” as expressly stated in the Summary of the Invention:
`
`Another principal aspect of the present invention groups together two
`or more blocks positioned in separate units of the memory array
`(also termed “sub-arrays”) for programming and reading together
`as part of a single operation. Such a multiple block group is
`referenced herein as a “metablock.”
`Ex. 1101 at 3:5-9 (emphasis added). As defined by the inventor, a “metablock” is
`
`two or more blocks: (1) positioned in separate units of the memory array; and (2)
`
`grouped for programming and reading together as part of a single operation.
`
`Additionally, the goal of the metablock aspect of the ‘490 patent is described as “to
`
`program as many cells in parallel as can reasonably be done without incurring
`
`other penalties.” Id. at 11:53-55 (emphasis added). The ‘490 patent further explains
`
`that the metablock innovation could be implemented with the metablock units
`
`located on the same memory chip, or where the units forming the metablock are
`
`found on multiple memory chips. Id. at 11:55-64. Accordingly, the BRI for
`
`“metablock” is “two or more blocks positioned in separate units of one or more
`
`12
` 
`
`

`
`memory chips for programming and reading together in parallel as part of a single
`
`operation.” 3
`
`IV. The Petitioner Does Not Demonstrate That It Is More Likely Than Not
`to Prevail On Any Challenged Claim on the ‘490 Patent
`
` 
`
`The institution of an inter partes review requires Petitioner to establish that
`
`there is a “reasonable likelihood that the petitioner would prevail with respect to at
`
`least one of the claims challenged in the petition.” 35 U.S.C. § 314(a). None of
`
`Petitioner’s challenges meet this threshold, and the Board should deny the Petition
`
`and deny institution of the inter partes review.
`
` 
`
`A.
`
`Petitioner Improperly Circumvents the Board’s Page Limit Rule
`
`The Petitioner’s inclusion in the Petition of approximately 20 pages of
`
`improper single-spaced claim charts replete with argument effectively allows the
`
`Petitioner to exceed the requisite page limit. The Petitioner uses extensive claim
`
`charts which include arguments that explain how the applied references disclose or
`
`teach different claim limitations. The Board has previously held that including
`
`such argument in a claim chart is improper. “If there is any need to explain how a
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`                                                            
`3
` Patent Owner, like Petitioner, notes that the standards of construction applied in
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`this proceeding are different from the standards applied in the related litigation.
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`Patent Owner also reserves the right to present evidence to the Board regarding
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`claim construction in its Response, should one be necessary. 
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`13
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`reference discloses or teaches a limitation, that explanation must be elsewhere in
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`the petition—not in a claim chart.” VMware, Inc. v. Electronics and
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`Telecommunications Research Institute, IPR2014-00901, paper 7 (PTAB
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`7/14/2014) (Order to Correct Non-Compliant Petition by APJ Quinn, for a panel
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`consisting of APJs McNamara, Quinn, and Anderson).
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`The Petition’s claim charts include precisely the kind of argument that the
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`Board does not allow. In the aforementioned VMware case, the Board provided an
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`example of what it considered to be improper argument included in a claim chart:
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`In addition, Hathorn Fig. 5 discloses shadowing data across multiple
`disks to create a remote dual copy, which is a RAID architecture
`commonly known as RAID 1.
`Id. The Board found that this language constituted a conclusion reached by a
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`declarant and therefore constituted argument. The current Petition includes many
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`similar conclusions, a couple of which are reproduced below.
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`14
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`
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`
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`Petition at 15. Here, the Petitioner writes in its claim chart that “[t]herefore,
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`Niijima discloses a non-volatile memory system having a plurality of blocks of
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`memory storage elements (i.e., ‘clusters’ and/or ‘blocks’) that are erasable together
`
`as a unit, the blocks individually organized into a plurality of pages of memory
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`storage elements (i.e., ‘sectors’ and/or ‘pages’) that are programmable together.”
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`Id. This is at least an argument by the Petitioner that “clusters” in Niijima
`
`correspond to the claimed blocks of memory storage elements, and that “sectors”
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`15
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`in Niijima correspond to the claimed pages of memory storage elements. Per
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`VMWare, this argument does not belong in a claim chart.
`
`Another example is provided below:
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`
`Petition at 39. The highlighted portion above shows an additional example of the
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`
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`Petitioner’s improper use of argument in claim charts. This is at least an argument
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`by the Petitioner that “block 80” in Niijima corresponds to the claimed metablock.
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`This argument does not belong in a claim chart.
`
`The charts replicated above are only a small portion of the claim charts
`
`included in the Petition, most of which include similar improper arguments. For
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`example, the Petitioner includes claim charts in the Petition on pages 15, 17-32,
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`16
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`35-42, and 45-46. All told, it appears that Petitioner uses 20+ pages of these single-
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`spaced claim charts. A petition requesting inter partes review can be no longer
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`than 60 pages. 37 C.F.R. § 42.24(a)(1). Claim charts included, the Petition is 55
`
`pages. If the Petitioner’s improper arguments were removed from the claim charts
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`and inserted into the body of the Petition, it appears that the page limit would be
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`exceeded. The Petition should therefore be denied for failing to comply with the
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`Board’s page limits and for improper use of claim charts.
`
`B.
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`Petitioner Fails to Demonstrate That Niijima Anticipates Claims
`34-38, 40, 41, 43-45, 50-57, and 59-64 or Renders Those Claims
`Obvious in View of the Knowledge of a Person of Ordinary Skill
`in the Art (Ground 1)
`
`A finding of invalidity under 35 U.S.C. § 102 requires a showing that a
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` 
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`single reference teaches every limitation of the claim. “A claim is anticipated only
`
`if each and every element as set forth in the claim is found, either expressly or
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`inherently described, in a single prior art reference.” M.P.E.P. § 2131, quoting
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`Verdegaal Bros. v. Union Oil Co. of California, 814 F.2d 628, 631 (Fed. Cir.
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`1987). Furthermore, an anticipatory reference must not only “disclose all elements
`
`of the claim within the four corners of the document,” it must disclose those
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`elements “arranged as in the claim.” Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d
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`1359, 1369 (Fed. Cir. 2008). The Petitioner in this case fails to establish that any
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`claim of the ‘490 patent is anticipated by Niijima because it fails to show that
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`Niijima discloses all the limitations of any challenged claim.
`17
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`The question of obviousness is resolved on the basis of underlying factual
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`determinations including (1) the scope and content of the prior art, (2) any
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`differences between the claimed subject matter and the prior art, and (3) the level
`
`of skill in the art. Graham v. John Deere Co., 383 U.S. 1, 17-18, 148 USPQ 459,
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`467 (1966); see also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 399 (2007)
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`(“While the sequence of these questions might be reordered in any particular case,
`
`the [Graham] factors define the controlling inquiry.”) A petitioner seeking to
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`invalidate a patent as obvious must demonstrate that a “skilled artisan would have
`
`been motivated to combine the teachings of the prior art references to achieve the
`
`claimed invention, and that the skill artisan would have had a reasonable
`
`expectation of success in doing so.” OSRAM Sylvania, Inc. v. Am. Induction
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`Techs., Inc., 701 F.3d 698, 706 (Fed. Cir. 2012). The Petitioner in this case also
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`fails to meet these requirements.
`
`
`1.
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`Petitioner Improperly Conflates Multiple Embodiments in
`Niijima
`
`In arguing that certain claims are anticipated by Niijima, the Petitioner
`
`repeatedly relies on two different embodiments to attempt to cobble together an
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`argument that the reference discloses each of the claimed features. But that is
`
`improper. Where a prior art reference discloses two embodiments, neither of which
`
`discloses all elements of a claim as arranged in the claim, those embodiments
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`18
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`

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`cannot be combined for anticipation purposes. See Net MoneyIN, Inc. v. Verisign,
`
`Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008); Nvidia Corp. v. Samsung Electronics
`
`Co., Ltd., IPR2015-0131