5,303,378
`[11] Patent Number:
`
`
`
`United States Patent
`
`
`
`
`
`
`
`[45] Date of Patent: Apr. 12, 1994
`
`Cohen
`
`llllllllllllll||l|||||||||l|ll||llllllllllllllllllll|||||||l|l|||||l|||||||
`USO05303378A
`
`
`[19]
`
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`
`
`[54] REENTRANT PROTECTED MODE KERNEL
`USING VIRTUAL 8086 MODE INTERRUPT
`
`
`
`
`
`SERVICE ROUTINES
`
`
`
`
`
`
`
`Leonardo Cohen, Spring, Tex.
`
`
`
`Inventor:
`[75]
`
`
`
`
`[73] Assignee: Compaq Computer Corporation,
`Houston, Tex.
`'
`
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`
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`
`
`[21] Appl. No.: 703,499
`
`
`[22] Filed:
`
`
`
`
`May 21, 1991
`
`
`
`Int. Cl.5 ............................................ .. G06F 12/00
`[51]
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`
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`[52] U.S. Cl. .................................. .. 395/700; 395/400;
`
`
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`
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`364/280.8; 364/280.9; 364/DIG. 1
`
`
`
`[58] Field of Search ............. .. 395/425, 650, 700, 400;
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`364/200, 900
`
`
`
`
`[56]
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`
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`
`
`4,779,187 10/1988 Letwin .............................. .. 395/$50
`
`
`
`
`
`5/1990 Stimac et al.
`4.926,322
`......... ..
`395/500
`
`
`
`
`
`
`395/700
`4,928,237
`5/1990 Bealkowski et al.
`
`
`
`
`
`395/650
`4,974,159 11/1990 Hargrove et al.
`.... ..
`
`
`
`
`
`
`. . . .. 395/400
`6/1991 Letwin . . . . . . . . . . . . . . . .
`5,027,273
`395/425
`6/1992 Randell
`5,125,087
`
`
`
`
`9/1992 Cepulis .............................. .. 395/700
`5,144,551
`
`
`
`
`
`OTHER PUBLICATIONS
`
`
`
`
`
`
`
`John Uffenbeck, Microcomputers and Microproces-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PM DATA
`
`
`SEGMENTS
`
`
`VM DATA
`
`
`SEGMENTS
`
`
`VMSS
`
`VMESP
`
`
`VM EFLAGS
`
`
`TF, IF CLEARED
`
`
`CS OF V86 ISR
`RING 0 STACK PTR
`
`
`
`
`
`
`
`SP
`EIP OF V86 ISR
`
`
`
`
`
`
`TSS
`
`
`
`
`
`
`
`
`
`
`
`Page 1 of 42
`
`Samsung Exhibit 1040
`
`sors: The 8080, 8085, and Z—80 Programming, Interfac-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ing, and Troubleshooting, 1985, pp. 257-273.
`
`
`
`
`
`
`James Turley, “Advanced 80386 Programming Tech-
`
`
`
`
`
`niques”, McGraw-Hill, 1988, pp. 283-315.
`
`
`
`Primary Examiner—Gareth D. Shaw
`Assistant Exam1'ner——Dennis M. Butler
`
`
`
`
`
`
`
`
`
`Attorney, Agent, or Ft'rm—Pravel, Hewitt, Kimball &
`
`Krieger
`
`
`ABSTRACT
`[57]
`
`
`
`
`
`
`
`
`to
`A method for allowing a protected mode kernel
`service,
`in virtual 8086 mode, hardware interrupts
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`which occur during execution of ring 0 protected mode
`code. When an interrupt occurs during execution of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ring 0 code, the microprocessor copies the state of the
`last virtual 8086 environment on the top of the ring 0
`
`
`
`
`
`
`
`
`stack and modifies this state to begin execution of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`appropriate interrupt service routine in virtual 8086
`mode. The kernel utilizes a secondary stack to keep
`
`
`
`
`
`
`
`
`track of the last virtual 8086 environment saved on the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ring 0 stack and updates the ring 0 stack pointer in the
`
`
`
`
`
`
`
`
`respective task’s task state segment to the new begin-
`
`
`
`
`
`
`
`
`
`ning of the ring 0 stack each time a ring transition oc-
`
`
`
`
`
`
`
`
`curs from ring 3 V86 mode to ring 0 protected mode.
`
`
`
`
`
`
`
`
`
`By manipulating the ring 0 stack and utilizing the sec-
`
`
`
`
`
`
`
`ondary stack to keep track of interrupted V86 environ-
`ments,
`the kernel can allow interrupts to be nested
`
`
`
`
`
`
`
`
`
`down multiple levels.
`
`
`
`
`16 Claims, 18 Drawing Sheets
`
`
`
`
`
`
`
`
`
`
`
`
`POINTER 1
`
`VMFS
`
`
`
`RING O STACK
`
`
`VM DATA
`
`
`SEGMENTS
`
`
`
`
`
`
`
`-
`
`
`VM ESP
`
`
`VM EFLAGS
`
`
`CS OF VM TASK
`
`INTERRUPTED
`EIP OF VM TASK
`
`
`INTERRUPTED
`
`N VARIABLES
`
`
`PM EFLAGS
`
`PM CS
`
`
`
`
`
`
`
`
`VMTF #1
`
`
`PMTF
`
`
`MODIFIED
`
`VMTF
`
`
`
`.
`
`
`
`Samsung Exhibit 1040
`
`Page 1 of 42
`
`

`
`U.S. Patent
`
`
`
`Apr. 12, 1994
`
`
`
`
`
`Sheet 1 of 18
`
`
`
`- 5,303,378
`
`
`
`
`LINEAR ADDRESS
`
`
`
`
`(As SEEN By
`
`PROGRAM)
`4GB ------------------------------------
`
`
`.
`
`
`80386
`
`
`PAGING
`MECHANISM
`
`
`
`
`
`PHYSICAL
`
`MEMORY PAGES
`4GB
`
`
`
`
`4GB
`
`
`
`PROGRAMT j
`CODER S
`“D
`S
`Mj S
`
`
`
`0
`
`......................................_. T
`
`
`1711533 I
`PRIOR ART
`
`
`
`ATTRIBUTES
`
`
`
`PRESENT
`RIGHTS
`PRIVILEGE
`ACCESSED
`DIRTY
`
`
`
`JAJ
`
`
`
`
`
`(USER DEFINED)
`
`
`PAGE ADDRESS
`
`
`
`
`
`E‘!/G79 J
`PRIOR ART
`
`
`
`Page 2 of 42
`
`Page 2 of 42
`
`

`
`U.S. Patent
`
`
`
`Apr. 12, 1994
`
`
`
`
`Sheet 2 of 18
`
`
`‘ 5,303,378
`
`
`
`LINEAR ADDRESS
`
`
`
`4GB
`
`
`
`31
`
`
`DIRECTORY
`
`21
`
`
`
`
`
`
`11
`
`0
`
`PAGE
`
`
`OFFSET
`
`
`
`
`
`
`
`PHYSICAL
`
`ADDRESS
`
`
`4K3
`
`PAGE
`
`u
`.
`.
`.
`.
`1
`-
`.
`
`.
`0
`.
`.
`u
`n
`u
`u
`
`PHYSICAL
`ADDRESS
`
`
`
`SPACE
`
`
`
`
`EM» 5‘
`
`PRIOR ART
`
`
`
`
`
`
`
`
`
`
`'
`
`
`
`PAGE TABLES
`
`
`(1024 ENTRIES
`EACH)
`
`E11632
`PRIOR ART
`
`
`
`
`
`
`
`
`
`(PAGE TABLE
`
`DIRECTORY
`
`
`
`BASE)
`
`
`
`
`
`PAGE TABLE
`
`
`DIRECTORY
`
`(1024 ENTRIES)
`
`
`
`USER **%~\
`
`
`
`OEM SERVICES
`:
`0S SERVICES
`
`
`
`
`
`USER
`
`oS
`
`
`
`KERNEL
`
`
`
`2
`
`
`
`
`
`OS
`
`
`AND USERS
`
`
`
`
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`
`
`
`
`
`IUSER
`
`
`
`
`
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`
`
`
`
`
`
`
`
`
`
`FOUR LEVELS OF PROTECTION
`(PROTECTED MODE)
`
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`
`
`UNPROTECTED SYSTEM
`
`
`(REAL MODE)
`
`
`
`Page 3 of 42
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`Page 3 of 42
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`

`
`U.S. Patent
`
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`. Apr. 12, 1994
`
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`Sheet 3 of 13
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`5,303,378
`
`
`
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`
`
`
`
`
`
`LOGICAL ADDRESS
`
`
`
`
`PAGING
`
`
`DISABLED
`
`
`LINEAR ADDRESS
`
`
`
`
`SEGMENT
`TRANSLATION
`
`
`
`
`
`
`
`
`
`
`
`DESCRIPTOR
`
`
`
`
`
`PAGING ENABLED
`
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`LINEAR ADDRESS
`
`
`PHYSICAL ADDRESS
`
`
`
`
`
`
`
`
`
`
`
`
`HIE» Q)
`PRIOR ART
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`. T891363 I
`I
`I
`
`
`
`OPERATING
`SYSTEM I
`
`
`
`
`
`
`
`
`PHYSICAL
`
`MEMORY
`
`
`
`
`
`
`
`
`pAGE D|REc'roRY
`
`TASK 1
`
`
`
`
`v|R‘ruAL
`
`3035 TASK
`
`
`
`
`
`
`
`
`
`e:Ieoe5
`
`‘OPERATING
`
`I SYSTEM’ :
`
`
`
`
`
`.‘r4\sI< 2; !
`
`PAQE'TABLE
`
`
`PAGE DIRECTORY
`
`TASK 2
`
`
`
`
`VIRTUAL
`
`8086 TASK
`
`
`
`
`
`[:1 TASK 1 MEMORY
`
`
`
`
`8086 OPERATING SYSTEM MEMORY
`
`
`
`|:| TASK 2 MEMORY
`
`
`
`
`
`
`
`
`
`
`
`80386 OPERATING SYSTEM MEMORY
`
`
`
`
`
`
`
`J-4"ljfi,‘,, Q)
`
`
`
`PRIORART
`
`
`
`Page 4 of 42
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`Page 4 of 42
`
`

`
`
`U.S. Patent
`
`
`
`
`
`Apr. 12, 1994
`
`
`
`.Sheet 4 of 18
`
`
`5,303,378
`
`
`
`
`Ellfig I
`
`
`PRIOR ART
`
`
`
`
`
`
`<- SS:ESP (NO ERROR CODE) INTERRUPT
`
`
`
`
`RING O STACK
`
`
`
`
`
`VM DATA
`
`
`SEGMENTS
`
`VM SS
`
`
`
`
`
`
`VM ESP
`
`
`
`
`
`VM EFLAGS
`
`
`CS OF VM TASK
`INTERRUPTED
`
`
`
`
`
`EIP OF VM TASK
`
`INTERRUPTED
`
`
`
`
`
`ERROR CODE
`
`
`
`
`
`
`<— SS:ESP (WITH ERROR CODE) EXCEPTION
`
`
`
`
`£115)» .83
`PRIOR ART
`
`
`
`
`E1167» 9)
`PRIOR ART
`
`
`
`
`
`
`FLAGS
`
`
`
`
`
`
`
`CS OF REAL MODE
`
`APP
`IP OF REAL MODE
`
`
`APP
`
`
`
`
`
`
`
`
`
`
`
`
`
`RING O STACK
`
`
`
`VM DATA '
`
`
`
`SEGMENTS
`
`VM SS
`
`VM ESP
`
`
`
`VM EFLAGS
`
`
`
`
`
`CS OF VM TASK
`INTERRUPTED
`
`
`
`
`
`EIP OF VM TASK
`
`INTERRUPTED
`
`
`
`
`
`
`VMTF
`
`RMTF
`
`
`
`
`VMTF
`
`Page 5 of 42
`
`Page 5 of 42
`
`

`
`
`U.S. Patent
`
`
`
`
`
`Apr. 12, 1994
`
`
`
`
`
`Sheet 5 of 18
`
`5,303,378
`
`
`
`RING 3 STACK
`
`
`
`RING O STACK
`
`
`
`
`VMTF
`
`
`
`VMTF
`
`
`
`
`
`VM DATA
`
`
`SEGMENTS
`
`VM SS
`
`
`
`
`
`VM ESP
`
`
`
`
`VM EFLAGS
`
`
`
`
`VM EFLAGS
`
`
`BEFORE INT
`
`
`CS OF VM TASK
`INTERRUPTED
`
`
`
`
`
`EIP OF VM TASK
`
`
`INTERRUPTED
`
`
`
`CS OF VM TASK
`INTERRUPTED
`EIP OF VM TASK
`
`
`INTERRUPTED
`
`
`
`
`
`
`
`
`E‘!/G7» 1/O
`PRIOR ART
`
`
`
`
`
`RING 3 STACK
`
`
`
`
`RING O STACK
`
`
`
`
`VM DATA
`
`
`SEGMENTS
`
`
`
`VMSS
`
`
`
`HANDLER
`
`
`
`NEW VM ESP
`
`
`
`
`(OLD ESP-6)
`EFLAGS
`
`
`(IF + TF CLEARED)
`CS OF VM
`
`INTERRUPT
`
`HANDLER
`
`EIP OF VM
`
`INTERRUPT
`
`
`
`VMTF
`
`
`
`
`HIE» I/J
`
`
`
`' VM EFLAGS
`
`
`
`BEFORE INT
`
`CS OF VM TASK
`
`INTERRUPTED
`
`
`
`INTERRUPTED
`
`EIP OF VM TASK
`
`
`
`
`E1169 I/Z
`
`PRIOR ART
`
`
`
`RING O STACK
`
`
`
`VM DATA
`
`
`SEGMENTS
`
`
`
`VM SS
`
`
`VM ESP
`
`
`
`
`VM EFLAGS
`
`
`
`
`
`
`
`
`
`RMTF
`
`RMTF
`
`
`
`Page 6 of 42
`
`
`
`CS OF VM TASK
`
`INTERRUPTED
`
`
`
`
`
`EIP OF VM TASK
`
`
`
`INTERRUPTED
`
`
`
`Page 6 of 42
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`

`
`U.S. Patent
`
`
`
`Apr. 12, 1994
`
`
`
`
`Sheet 6 of 18
`
`
`5,303,378
`
`
`
` V86 TASK
`
`
`
`
`
`EXECUTING
`
`
`
`
`
`
`
`
`
` V86 TASK
`ExcEPTIoNAL
`
`
`COMPLETED?
`CONDITION?
`
`
`
`
`
`
`
`
`PROCESSOR TRANSITIONS
`
`
`FROM RING 3 V86 MODE TO
`
`
`
`
`
`
`
`RING o PROTECTED MODE
`
`
`
`182
`
`i
`
`Y
`
`
`EXECUTE GP
`
`FAULT HANDLER
`
`
`
`
`
`
`
`114
`
`
`
`
`
`Y
`
`N
`
`
`
`
`
`
`
`
`GETS RING 0 STACK
`
`
`
`POINTER FROM TSS
`
`
`
`
`
`
`SAVE VTMF ON Top OF
`RING o STACK PoINTED
`
`
`
`TO BY RING o STACK PTR
`
`
`
`
`
`
`
`GP FAULT
`
`
`HANDLER?
`
`
`N
`
`134
`
`
`
`
`
`EXECUTE 'RET
`
`'N3TR”°T‘°N
`
`
`
`
`EXECUTE EHI CODE
`T0 TRAP T0
`
`
`PROTECTED MODE
`
`
`
`
`186
`
`
`
`
`DISCARD VMTF ON RING
`
`
`
`o CAUSED BY TRAP
`
`
`
`
`188
`
`
`
`
`UPDATE RING o
`
`
`
`
`
`STACK PTR IN TSS
`
`190
`
`
`
`
`
`RESTORE SEGMENT
`
`
`REGISTERS
`
`
`
`118
`
`
`
`SPECIAL S/W
`
`
`
`INTERRRUPT?
`
`
`
`
`
`S/W INT
`
`REQUESTING PM
`
`SERVICE?
`
`
`N
`FM» ma:
`
`1 19
`
`
`
`9
`
`
`EXECUTE IRET INSTRUCTION
`
`
`
`TO RETURN TO
`
`
`
`
`
`
`INTERRUPTED PM CODE
`
`
`
`
`
`
`Page 7 of 42
`
`Page 7 of 42
`
`

`
`U.S. Patent
`
`
`
`
`Apr. 12, 1994
`
`
`
`
`
`Sheet 7 of1s
`
`
`' 5,303,378
`
`
`
`ERROR CODE ON
`
`
`RING O STACK?
`
`
`
`
`
`124
`
`
`
`
`PM HANDLER PUSHES A
`
`
`
`POINTER TO VMTF IN VMFS
`
`
`
`
`
`
`
`
`
`
`
`INTERRUPTS ARE ENABLED
`
`
`
`AND THE PROTECTED MODE
`
`
`
`
`SERVICE IS DISPATCHED
`
`
`
`
`
`
`EXECUTE REFLECTION
`
`EXECUTE EXCEPT|ON
`
`
`
`
`
`CODE TO REFLECT
`HANDLER CODE
`
`
`BACK TO V86 MODE
`
`
`
`
`
`
`
`
`
`130
`
`132
`
`
`
`
`
`
`
`PROTECTED MODE
`
`
`SERVICE EXECUTING
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`EXCEPTIONAL
`
`
`CONDITION?
`
`
`
`
`
`Y
`
`
`
`
`
`POP LAST VALUE
`OFF OF VMFS
`
`
`
`
`
`
`
`
`EXECUTE IRET
`
`
`
`INSTRUCTION TO
`
`
`
`RETURN TO V86 CODE
`
`Y
`
`‘
`
`150
`
`
`
`0
`
`Page 8 of 42
`
`PROTECTED
`
`MODE SERVICE
`
`COMPLETE?
`
`
`
`
`E1169 Lu
`
`
`
`G
`
`‘
`
`SAVE PTMF ON THE
`
`
`
`
`RING 0 STACK
`
`133
`
`
`
`
`
`
`
`Page 8 of 42
`
`

`
`U.S. Patent
`
`
`
`Apr. 12, 1994
`
`
`
`
`Sheet 8 of 18
`
`
`
`‘ 5,303,378
`
`
`
`
`140
`
`
`
`
`
`
`
`SAVE SEGMENT
`
`
`
`REGISTERS ON THE
`
`
`RING 0 STACK
`
`
`
`
`
`
`GET POINTER TO LAST
`
`
`
`VTMF ON THE RING 0 STACK
`
`
`
`
`
`
`
`COPY LAST VTMF TO THE
`TOP OF THE RING 0 STACK
`
`
`
`
`TO CREATE NEW VTMF
`
`
`
`
`
`
`
`
`GET SEGMENTIOFFSET OF
`
`
`THE ENTRY POINT OF THE
`
`
`
`
`ISR FROM THE IVT
`
`
`
`
`
`
`MODIFY VMTF TO IRET
`
`
`
`
`
`
`
`TO THIS ENTRY POINT
`
`
`
`
`UPDATE RING o STACK
`
`
`POINTER IN TSS TO POINT
`TO MODIFIED VMTF
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`EXECUTE PAGE
`
`
`FAULT HANDLER
`
`
`
`
`APPEND EHI CODE
`
`
`POINTER TO TOP OF
`
`
`THE Rm 3 STACK
`
`
`
`
`
`
`
`
`
`EXECUTE IRET INSTRUCTION
`
`
`
`TO TRANSFER TO V86 MODE
`TO BEGIN ISR
`
`
`
`
`0
`
`51/619 126
`
`Page 9 of 42
`
`Page 9 of 42
`
`

`
`U.S. Patent
`
`
`
`_ Apr. 12, 1994
`
`
`
`
`
`Sheet 9 of 18
`
`
`5,303,378
`
`
`
`
`
`VMFS
`
`
`POINTER 1
`
`
`
`
`
`
`
`
`FIIGI” 1/
`
`4/
`'
`
`
`
`VMFS
`
`
`
`POINTER 1
`
`
`
`
`
`
`
`
`
`
`F116} M5
`
`
`
`RING O STACK
`
`
`
`VM DATA
`
`
`
`SEGMENTS
`
`VM SS
`
`
`VM ESP
`
`
`
`
`-
`
`
`VM EFLAGS
`
`
`
`CS OF VM TASK
`
`INTERRUPTED
`EIP OF VM TASK
`
`
`INTERRUPTED
`
`
`
`
`RING o STACK
`
`
`
`VM DATA
`
`
`SEGMENTS
`
`
`
`
`VM ESP
`
`
`
`VM EFLAGS
`
`
`
`
`
`INTERRUPTED
`
`
`INTERRUPTED
`
`
`
`
`
`
`
`RING O STACK
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`VMTF‘:
`VMTF‘:
`
`
`
`
`
`VM DATA
`
`
`SEGMENTS
`
`
`
`VM SS
`
`
`
`
`
`
`
`
`
`
`VMTF
`PMTF[
`
`
`
`Page 10 of 42
`
`VMFS
`
`
`POINTER 1
`
`
`
`
`MIG?» 1/5
`
`
`
`VM ESP
`
`
`
`
`VM EFLAGS
`
`
`
`CS OF VM TASK
`
`INTERRUPTED
`
`
`
`EIP OF VM TASK
`
`
`INTERRUPTED
`
`
`
`N VARIABLES
`
`
`
`
`PM EFLAGS
`
`PM CS
`
`
`
`
`
`
`PM DATA
`
`
`SEGMENTS
`
`
`
`
`Page 10 of 42
`
`

`
`U.S. Patent
`
`
`
`
`Apr. 12, 1994
`
`
`
`
`
`Sheet 10 of 18
`
`
`5,303,378
`
`
`
`VMFS
`
`
`
`
`POINTER 1
`
`
`
`
`
`E1167» 1/!
`
`
`
`
`
`
`
`
`
`
`
`
`
`RING O STACK
`
`
`
`
`
`VM DATA
`
`SEGMENTS
`
`
`3
`
`
`
`VM ESP
`
`
`
`VM EFLAGS
`
`
`cs OF VM TASK
`INTERRUPTED
`
`
`ElP OF VM TASK
`
`INTERRUPTED
`
`
`N VAR|ABLES
`
`
`
`
`
`
`
`
`
`
`
`PM EFLAGS
`
`PM cs ’
`
`
`
`
`PM DATA
`
`
`
`SEGMENTS
`
`
`
`VM DATA
`
`SEGMENTS
`
`VM ss
`
`
`
`VM ESP
`
`
`
`
`
`cs OF .\/M TASK
`
`INTERRUPTED
`
`
`EIP OF VM TASK
`INTERRUPTED
`
`
`
`
`
`
`
`
`
`
`
`
`
`VMTF
`
`
`
`COPY
`
`
`
`PMTF
`
`
`
`VMTF
`
`
`
`Page 11 of 42
`
`Page 11 of 42
`
`

`
`US. Patent
`
`
`
`
`Apr. 12, 1994
`
`
`
`
`
`Sheet 11 of 18
`
`
`5,303,378
`
`
`
`
`RING O STACK
`
`
`
` VM DATA
`
`
`
`
`SEGMENTS
`
`VM SS
`
`
`
`VM ESP
`
`VMFS
`
`
`
`
`
`
`
`
`
`
`
`VM EFLAGS
`POINTER 1
`
`
`CS OF VM TASK
`INTERRUPTED
`
`
`
`EIP OF VM TASK
`
`INTERRUPTED
`
`
`N VARIABLES
`
`
`
`
`VMTF #1
`
`PMTF
`
`
`
`Page 12 of 42
`
`
`EM?» JD
`
`
`
`TSS
`
`
`
`
`
`RING 0 STACK PTR
`
`
`
`SP
`
`
`
`
`
`
`
`
`PM EFLAGS
`
`
`
`
`PM CS
`
`
`PM EIP
`
`
`
`PM DATA
`SEGMENTS
`
`
`
`
`
`VM DATA
`
`SEGMENTS
`
`VM SS
`
`
`
`
`
`
`
`VM ESP
`
`MODIFIED
`VMTF
`VM EFLAGS
`-
`
`
`
`
`
`
`TF, IF CLEARED
`CS OF V86 ISR
`
`
`
`
`
`
`EIP OF V86 ISR
`
`Page 12 of 42
`
`

`
`U.S. Patent
`
`
`
`Apr. 12, 1994
`
`
`
`
`
`Sheet 12 of 18
`
`
`5,303,378
`
`
`
`
`
`RING O STACK
`
`A
`
`
`
`VMFS
`
`
`
`
`POINTER 1
`
`
`POINTER 2
`
`
`Ellfie» 1/9)
`
`
`
`TSS
`
`
`
`
`
`VM DATA
`SEGMENTS
`
`VM SS
`
`
`
`
`VM ESP
`
`
`
`
`
`VM EFLAGS
`
`
`CS OF VM TASK
`
`
`
`
`EIP OF VM TASK
`
`
`
`
`
`N VARIABLES
`
`
`
`PM EFLAGS
`
`
`PM CS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PM DATA
`
`
`SEGMENTS
`
`VM DATA
`
`
`SEGMENTS #2
`
`VM SS #2
`
`
`
`VM ESP #2
`
`
`
`VM EFLAGS #2
`
`
`
`
`
`VMTF #1
`
`
`PMTF
`
`
`
`VMTF #2
`
`
`
`
`
`
`
`
`
`
`RING 0 STACK PTR
`
`SP
`
`
`
`
`
`
`CS OF VM TASK #2
`
`
`
`EIP OF VM TASK
`
`#2
`
`
`
`Page 13 of 42
`
`Page 13 of 42
`
`

`
`
`U.S. Patent
`
`
`
`Apr. 12, 1994
`
`
`
`
`
`Sheet 13 of 18
`
`
`~ 5,303,378
`
`
`
`
`RING o STACK
`
`
`
`
`
`VM DATA
`
`SEGMENTS
`
`VM SS
`
`
`
`VM ESP
`
`
`
`VM EFLAGS
`
`
`
`VMTF #1
`
`
`
`
`
`
`
`
`
`
`
`CS OF VM TASK
`
`
`EIP OF VM TASK
`
`
`
`
`N VARIABLES
`
`
`
`
`
`PM EFLAGS
`
`
`PM CS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`VMFS
`
`
`
`
`POINTER 1
`
`
`POINTER 2
`
`
`El/G.) 20
`
`
`
`1.38
`
`
`
`
`
`PM DATA
`SEGMENTS
`
`VM DATA
`
`
`SEGMENTS #2
`
`VM SS #2
`
`
`
`VM ESP #2
`
`
`
`VM EFLAGS #2
`
`
`
`
`
`
`
`
`
`RING 0 STACK PTR
`
`SP
`
`
`
`
`
`CS OF VM TASK #2
`
`
`
`
`EIP OF VM TASK
`
`#2
`
`
`N VARIABLES PM
`
`TASK # 2
`
`
`PMTF
`
`
`VMTF #2
`
`Page 14 of 42
`
`Page 14 of 42
`
`

`
`U.S. Patgnt
`
`
`
`Apr. 12, 1994
`
`
`
`
`Sheet 14 of 18
`
`
`I 5,303,378
`
`
`
`
`VMFS
`
`
`
`
`POINTER 1
`
`
`POINTER 2
`
`
`
`
`
`MIG?» 21
`
`
`
`
`
`
`
`RING 0 STACK PTR
`
`
`SP
`
`
`
`
`
`
`
`
`RING O STACK
`
`
`
`
`VM DATA
`
`
`SEGMENTS
`
`
`VM SS
`
`
`
`
`VM ESP
`
`
`VM EFLAGS
`
`
`
`
`
`CS OF VM TASK
`
`EIP OF VM TASK
`
`
`
`
`N VARIABLES
`
`
`
`
`PM EFLAGS
`
`
`
`PM CS
`
`
`
`
`PM DATA
`
`
`SEGMENTS
`
`
`
`
`VM DATA
`
`SEGMENTS #2
`
`
`
`VM ss #2
`
`
`VM ESP #2
`_
`
`
`
`VM EFLAGS #2
`
`
`
`cs OF VM TASK #2
`
`
`
`EIP OF VM TASK
`
`
`
`N VARIABLES PM
`
`
`TASK # 2
`
`PM EFLAGS #2
`
`
`
`PM CS #2
`
`
`
`
`PM EIP #2
`
`PM DATA
`
`SEGMENTS #2
`
`
`
`VM DATA
`
`SEGMENTS #2
`
`
`
`
`VM SS #2
`
`
`VM ESP #2
`
`
`
`VM EFLAGS #2
`
`
`
`CS OF VM TASK #2
`
`
`
`EIP OF VM TASK
`
`l\)
`
`
`
`
`I I I I I
`
`VMTF#1
`
`
`
`PMTF # 1
`
`
`
`COPY
`
`
`
`
`PMTF#2
`
`
`VMTF#2
`
`Page 15 of 42
`
`Page 15 of 42
`
`

`
`U.S. Patent
`
`
`
`
`_ Apr. 12, 1994
`
`
`
`
`
`
`Sheet 15 of 18
`
`
`5,303,378
`
`
`
`
`
`VMFS
`
`
`
`
`POINTER 1
`
`POINTER 2
`
`
`HIE» 22’
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`RING O STACK
`
`
`
`
`VM DATA
`
`
`SEGMENTS
`
`VM SS
`
`
`VM ESP
`
`
`
`
`
`
`VM EFLAGS
`
`CS OF VM TASK
`
`
`
`
`EIP OF VM TASK
`
`
`
`N VARIABLES
`
`
`
`
`PM EFLAGS
`
`
`
`
`PM CS
`
`
`
`
`PM DATA
`
`
`SEGMENTS
`
`
`
`
`
`VM DATA
`
`SEGMENTS #2
`
`
`
`VM SS #2
`
`
`VM ESP #2
`
`
`
`VM EFLAGS #2
`
`
`
`CS OF VM TASK #2
`
`
`
`
`#2
`
`
`
`
`
`
`
`TASK # 2
`
`
`
`
`
`PM CS #2
`
`
`
`
`PM EIP #2
`
`
`SEGMENTS #2
`
`
`
`
`
`
`
`SEGMENTS #2
`
`
`
`
`
`
`
`
`
`VM EFLAGS #2
`
`
`TF, IF CLEARED
`RING 0 STACK PTR
`
`
`
`
`
`
`CS OF V86 ISR #2
`SP
`
`
`. T35
`
`
`
`
`
`
`
`
`
`
`EIP OF V86 ISR #2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`III IIIIIII
`
`VMTF#1
`
`
`
`PMTF#1
`
`
`VMTF#2
`
`
`PMTF#2
`
`MODIFIED
`
`VMTF#2
`
`
`Page 16 of 42
`
`Page 16 of 42
`
`

`
`U.S. Patent
`
`
`
`Apr. 12, 1994
`
`
`
`
`. Sheet 16 of 18
`
`
`
`5,303,378
`
`
`
`'
`
`
`
`VMFS
`
`
`
`
`POINTER 1
`
`POINTER 2
`
`
`
`51/57:» 193
`
`
`
`
`
`
`
`
`
`RING 0 STACK PTR
`
`
`SP
`
`
`
`
`I RING O STACK
`
`
`
`
`
`VM DATA
`
`
`SEGMENTS
`
`
`VM SS
`
`
`
`
`VM ESP
`
`
`
`VM EFLAGS
`
`CS OF VM TASK
`
`
`
`
`EIP OF VM TASK
`
`
`
`N VARIABLES
`
`
`
`
`PM EFLAGS
`
`
`
`PM cs
`
`
`
`
`PM DATA
`
`
`SEGMENTS
`
`
`VM DATA
`
`SEGMENTS #2
`
`
`
`
`VM SS #2
`
`
`VM ESP #2
`
`
`
`VM EFLAGS #2
`
`
`
`CS OF VM TASK #2
`
`
`
`
`
`EIP OF VM TASK
`
`l\)
`
`N VARIABLES PM
`
`
`TASK # 2
`
`PM EFLAGS #2
`
`
`
`PM CS #2
`
`
`PM EIP #2
`
`PM DATA
`
`SEGMENTS #2
`
`
`
`
`VMTF#1
`
`
`
`
`PMTF # 1
`
`A VMTF#2
`
`
`
`
`PMTF#2
`
`Page 17 of 42
`
`Page 17 of 42
`
`

`
`U.S. Patent
`
`
`
`Apr. 12, 1994
`
`
`
`
`
`Sheet 17 of 18
`
`
`5,303,378
`
`
`
`
`RING O STACK
`
`
`
`
`
`
`
`
`VM DATA
`
`SEGMENTS
`
`VM SS
`
`
`VM ESP
`
`
`
`
`VM EFLAGS
`
`
`
`
`
`CS OF VM TASK
`
`
`
`EIP OF VM TASK
`
`
`N VARIABLES
`
`
`
`
`
`PM EFLAGS
`
`
`PM CS
`
`
`
`
`
`
`
`VMFS
`
`
`
`
`POINTER 1
`
`
`POINTER 2
`
`
`Ellfij-J 2%
`
`
`
`
`
`
`
`
`
`
`
`
`
`PM DATA
`
`
`SEGMENTS
`
`VM DATA
`
`SEGMENTS #2
`
`
`VM SS #2
`
`VM ESP #2
`
`
`
`
`
`
`
`
`
`
`VM EFLAGS #2
`
`
`
`CS OF VM TASK #2
`
`
`
`#2
`
`
`
`
`
`
`
`TASK # 2
`
`
`
`
`
`
`
`
`
`
`
`
`RING 0 STACK PTR
`
`SP
`
`
`
`
`VMTF #1
`
`
`PMTF # 1
`
`VMTF #2
`
`Page 18 of 42
`
`Page 18 of 42
`
`

`
`
`
`U.S. Patent
`
`Apr. 12, 1994
`
`
`
`
`
`Sheet 18 of 18
`
`
`5,303,378
`
`
`
`
`
`RING O STACK
`
`
`
`VM DATA
`SEGMENTS
`VM SS
`
`
`
`
`
`
`
`
`
`
`
`
`VM ESP
`
`VM EFLAGS
`
`
`
`
`
`CS OF VM TASK
`
`
`
`EIP OF VM TASK
`
`
`
`
`_VMFS
`
`
`POINTER 1
`
`
`
`
`F116?» 25
`
`
`
`
`VMTF #1
`
`
`PMTF # 1
`
`
`VMTF #1
`
`TSS
`
`
`
`
`
`
`
`RING 0 STACK PTR
`
`SP
`
`
`
`Mag; 29
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`SEGMENTS
`
`
`
`
`
`RING o STASK
`
`
`
`VM DATA
`
`
`SEGMENTS
`
`
`
`
`
`VM ESP
`
`
`
`VM EFLAGS
`
`
`
`
`
`CS OF VM TASK
`
`
`EIP OF VM TASK
`
`
`
`N VARIABLES
`
`
`
`
`
`
`
`
`
`
`Page 19 of 42
`
`Page 19 of 42
`
`

`
`1
`
`
`
`5,303,378
`
`
`
`REENTRANT PROTECTED MODE KERNEL
`
`
`
`
`USING VIRTUAL 8086 MODE INTERRUPT
`
`
`
`
`
`SERVICE ROUTINES
`
`
`
`l0
`
`15
`
`25
`
`30
`
`35
`
`45
`
`
`
`
`
`2
`
`
`
`
`
`
`
`
`
`80286 and 80386 microprocessors use the value held in
`
`
`
`
`
`
`
`the segment register to look up a base address which is
`stored in a descriptor table in memory. The 80286 uti-
`
`
`
`
`
`
`
`lizes a 24-bit base address, which allows the 80286 to
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`access 16 Megabytes of memory (224)
`instead of l
`
`
`
`
`
`
`
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`Megabyte (220). The 80286 adds a 16-bit offset address
`to this base address to form a 24 bit address. The 80386
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`utilizes a 32-bit base address and a 32-bit offset to form
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`a 32-bit address, which allows the 80386 to access 4
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`gigabytes of memory.
`In order to more fully understand the present inven-
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`tion, there follows a discussion of the way in which the
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`80386 microprocessor addresses memory.
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`The physical address space of most computers is
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`organized as a simple array of bytes. With the develop-
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`ment of memory management units (MMU’s), computer
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`architectures began to distinguish between the physical
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`address space implemented by the memory hardware
`and the logical address space seen by a programmer.
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`The MMU translates the logical addresses presented by
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`programs into the physical addresses that are provided
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`from the microprocessor. The 80386 logical address
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`space consists of a collection of one of the following:
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`Bytes: The logical address space consists of an array
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`of bytes with no other structure (this is sometimes called
`a “flat” or “linear” address space). No MMU translation
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`is required because of a logical address is exactly equiv-
`alent to a physical address.
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`Segments: The logical address space consists of a few
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`or many segments, each of which is composed of a
`variable number of bytes. A logical address is given in
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`two parts, a segment number and an offset into the
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`segment. The MMU translates a logical address into a
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`physical address.
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`Pages: The logical address space consists of many
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`pages, each of which is composed of a fixed number of
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`bytes. A logical address is a page number plus an offset
`within the page. The MMU translates a logical address
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`into a physical address.
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`Paged Segments: The logical address space consists
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`of segments which themselves consist of pages. A logi-
`cal address is a segment number and an offset. The
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`MMU translates the logical address into a linear address
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`which is then translated by the paging mechanism into
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`a physical address.
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`Technically, the 80386 views memory as a collection
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`of segments that are optionally paged. In practice, the
`80386 architecture supports operating systems that use
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`any of the four views of memory described above.
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`There follows a more detailed discussion of the segmen-
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`tation and paging mechanisms in the 80386 micro-
`processor.
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`In protected mode, the segment is the unit the 80386
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`provides for defining a task’s logical address space.
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`Segment registers define the way that memory is orga-
`nized between tasks, that is, a task’s logical address
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`space consists of one or more segments. An instruction
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`refers to a memory operand by a two-part logical ad?
`dress consisting of a segment selector and an offset into
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`the segment. The 80386 uses the selector to look up the
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`segment’s descriptor in a segment descriptor table, and
`the base address in the descriptor is added to the offset
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`to produce the operand’s linear address. In this manner,
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`the segmentation unit in the 80386 translates a logical
`address into a linear address.
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`Each task has its own descriptor table describing the
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`segments for that task, and that (along with 80386 regis-
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`20
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`BACKGROUND OF THE INVENTION -
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`1. Field of the Invention
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`The present invention relates to operating systems in
`computer systems, and more particularly to an inter-
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`ruptible protected mode kernel which can service, in
`virtual 8086 mode, hardware interrupts which occur
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`during execution of ring 0 protected mode code.
`2. Description of the Prior Art
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`Many popular personal computers are based on the
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`Intel Corporation (Intel) 8086 family of microproces-
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`sors. This microprocessor family includes the 8088, the
`8086, the 80186, the 80286, the 80386, and the 80486
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`microprocessors, among others. These microprocessors
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`have been designed for upward compatibility—pro-
`grams written for the 8088 and/or the 8086 can be run
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`on computers having 80286, 80386, or 80486 processors,
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`and programs written for the 80286 processor can be
`run by the 80386 or the 80486. For the purposes of this
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`disclosure, the upwardly compatible series of Intel pro-
`cessors and processors which include the instruction set
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`of these processors is hereinafter referred to as the Intel
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`8086 family of microprocessors. Also, for the purposes
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`of this disclosure, the 8088 and the 8086 may be consid-
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`ered functionally equivalent and will henceforth be
`referred to as “the 8086.” In addition, the 80386 and
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`80486 microprocessors are considered functionally
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`equivalent and will henceforth be referred to as “the
`80386.”
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`The amount of physical memory a microprocessor
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`can access depends on the number of address lines that
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`emanate from the chip. Each additional bit doubles the
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`amount of addressable memory. The 8086 can address
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`one Megabyte of memory, which requires a 20-bit ad-
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`dress. Rather than introduce a 20-bit register into the
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`8086, the 20-bit address is split into two portions—a
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`16-bit segment address and a 16-bit offset address,
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`which are stored in different
`registers. The micro-
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`processor shifts the segment address 4 bits left (thereby
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`effectively multiplying it by 16) and then adds the offset
`address. The result is a 20-bit address that an access 1
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`Megabyte of memory.
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`By convention, a 20-bit address can be shown broken
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`down into its segment and offset parts using the notation
`0000:0000, the segment being to the left of the colon and
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`the offset on the right. For example, a 20-bit address
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`written as FFE6E in hexadecimal notation could be
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`written as FFE4:002E in segmented notation. Each of
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`the four segment registers in the 8086 defines a 64 KB
`block of memory called a “segment.” If all the segment
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`registers are kept constant and equal, then the micro-
`processor can access only 64 kbytes of memory.
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`The 80286 and the 80386 microprocessors all support
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`and go beyond the segmented addressing scheme of the
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`8086. When first powered up, they operate in “real
`mode," which uses segment and offset registers in the
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`same way as the 8086 to access the same one Megabyte
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`of memory. Thus the 80286 and the 80386 microproces-
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`sors are upwardly compatible with the addressing
`scheme of the 8086 chip.
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`In addition to real mode operation, the 80286 and the
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`80386 can operate in “protected mode." The main dif-
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`ference of protected mode is that the segment register is
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`no longer a real (i.e., physical) address. Instead, the
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`5,303,378
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`4
`considers the linear address formed from the segment:-
`offset to be the physical address and provides it on the
`address pins. If paging is enabled, the 80386 translates
`the linear address into a physical address with the aid of
`page tables. The page translation step is optional, and
`paging must be enabled if the operating system is to
`implement multiple virtual 8086 tasks, page-oriented
`protection, or page-oriented virtual memory. FIG. 4
`shows the fundamentals of 80386 logical-to-physical
`address translation.
`'
`In addition to the on-chip memory management fea-
`ture discussed above, the 80386 includes a protection
`scheme in order to support multitasking. The 80386
`protection mechanism consists of two parts: the mem-
`ory management scheme discussed above, which is used
`to protect various tasks from each other, and privilege
`level protection, which is used to selectively protect
`various portions of the operating system and other soft-
`ware from user applications. As explained above, the
`memory management abilities of the 80386 provides for
`the separation of task address spaces by segment de-
`scriptor tables and page tables. This separation can
`effectively prevent application tasks from interfering
`with each other‘s code and data. In addition to isolating
`tasks from each other, the privilege level protection
`mechanism provides facilities for protecting the operat-
`ing system from application code, for protecting one
`part of the operating system from other parts, and for
`protecting a task from some of its own errors.
`Referring now to FIG. 5, the privilege level protec-
`tion facilities of the 80386 are based on the notion of a
`privilege hierarchy. The 80386 microprocessor has four
`levels of protection which can support the needs of a
`multitasking operating system to isolate and protect
`user programs from each other and the operating sys-
`tem. In this description, privilege levels are also gener-
`ally referred to as rings, and they are numbered 0
`through 3. Ring 0 is the most privileged level and ring
`3 is the least privileged level.
`FIG. 5 shows how the 80386 privilege levels can be
`used to establish different protection policies. An un-
`protected system can be implemented by simply placing
`all procedures in a segment (or segments) whose privi-
`lege level is 0. Real mode is an example of an unpro-
`tected system because the operating system (OS) and all
`of the various procedures and applications are operating
`at ring 0 level. In contrast, protected mode utilizes the
`full privilege and protection capabilities of the 80386.
`For example, in protected mode, the most critical and
`least changing operating system procedures (referred to
`as the operating system kernel) are assigned to ring 0.
`Ring 1 is generally used for the services that are less
`critical and more frequently modified or extended, for
`example, device drivers. Ring 2 may be reserved for use
`by original equipment manufacturers (OEM‘s). Such
`OEM’s could then assign their code privilege level 2,
`leaving ring 3 for the end users. In this way, the OEM
`software is protected from the end users; the operating
`system is protected from both the OEM and the end
`users; and,
`the operating system kernel
`is protected
`from all other software, including that part of the oper-
`ating system that is subject to frequent change.
`Therefore, protected mode is so named because seg-
`ments belonging to one task are protected from being
`corrupted by another task. Tasks are organized in privi-
`lege levels, and certain machine-code instructions are
`prohibited to lower privilege levels: In a well-designed
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`ter values) is virtually all that the 803 86 needs to store to
`switch between tasks. Since addresses are stored in the
`descriptor table rather than in the segment registers, the
`operating system can move memory around without
`application programs being affected.
`‘
`Unlike the 8086, 8088, and 80286, the 80386 micro-
`processor incorporates memory paging hardware. This
`allows linear addresses to be mapped to physical mem-
`ory addresses. This facility allows the efficient imple-
`mentation of virtual memory systems. With memory
`paging support, the operating system can easily allocate
`contiguous memory to an application simply by map-
`ping a number of noncontiguous physical memory
`pages into the requested logical program space. This
`mapping of a program’s linear address space into physi-
`cal memory is shown schematically in FIG. 1.
`The mapping of noncontiguous physical memory
`pages into a requested logical program space is per-
`formed by updating the page directory and page tables.
`An 80386 operating system enables paging by setting
`the PG (Paging Enabled) bit
`in Control Register 0
`(CR0) with a privileged instruction. When paging is
`enabled, the processor translates a linear address to a
`physical address with the aid of page tables. Page tables
`are the counterparts of segment descriptor tables; as a
`task’s segment descriptor table defines its logical ad-
`dress space, a task’s page tables define its linear address
`space. An 80386 task’s page tables are arranged in a
`two-level hierarchy as shown in FIG. 2. Each task can
`have its own page table directory. The 80386‘s CR3
`(Page Table Directory Base) system register points to
`the running task’s page table directory. The 80386 up-
`dates CR3 on each task switch, obtaining the new direc-
`tory address from an area of memory associated with
`that task referred to as the task state segment (TSS).
`FIG. 2 shows in functional terms how the 80386 micro-
`processor translate a linear address to a physical address
`when paging is enabled. The processor uses the upper
`10 bits of the linear address as an index into the direc-
`tory. The selected directory entry contains the address
`ofa page table. The processor adds the middle 10 bits of
`the linear address to the page table address to index the
`page table entry that describes the target page. Adding
`the lower 12 bits of the linear address to the page ad-
`dress produces the 32-bit physical address.
`FIG. 3 shows the basic content of a page table entry.
`Directory entries are identical, except
`that the page
`address field is interpreted as the physical address of a
`page table, rather than a page.
`Tasks can share individual pages or entire page tables.
`Entries in different page tables that point to the same
`page are aliases of one another just as descriptors with
`the same base address are aliases of one another. The
`80386‘s two-level page table structure makes it easier to
`share pages between tasks by sharing entire page tables.
`Since the address of a page shared in this way