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`Samsung Exhibit 1005
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`digest of papers
`
`Fcbr:_aa4'y25-23.1936
`
`aB
`
`IFITY-F|F|5T1EEE CC.‘MF‘LJTER
`
`CIETT If-JTEFWATIOPJAL CiCINFEF|E|'~JCE
`
`pl:-n sated by
`3.
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`digest ofpapers
`
`COMPCON ’96
`
`Technologies for the Information Superhighway
`
`Forty—First IEEE Computer Society International Conference
`
`Sponsored by — The IEEE Computer Society
`
`February 25 -28, 1996
`
`Santa Clara, California
`
`IEEE Computer Society Press
`Los Alamitos, California
`-
`
`Tokyo
`. -
`Brussels
`-
`Washington
`
`
`Page 4 of 23
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`Page 4 of 23
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`

`
`
`
`
`
`IEEE Computer Society Press
`10662 Los Vaqueros Circle
`P.O. Box 3014
`Los Alamitos, CA 90720-1264
`
`Copyright © 1996 by The Institute of Electrical and Electronics Engineers, Inc.
`All rights reserved.
`
`Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries may
`photocopy beyond the limits of US copyright law, for private use of patrons, those articles in this volume
`that carry a code at the bottom of the first page, provided that the per-copy fee indicated in the code is paid
`through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923.
`
`IEEE Copyrights Manager, IEEE
`Other copying, reprint, or republication requests should be addressed to:
`Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331.
`
`The papers in this book comprise the proceedings of the meeting mentioned on the cover and title page. They
`reflect the authors’ opinions and, in the interests of timely dissemination, are published as presented and
`without change. Their inclusion in this publication does not necessarily constitute endorsement by the
`editors, the IEEE Computer Society Press, or the Institute ofElectrical and Electronics Engineers, Inc.
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`3.: so 3 fifittaflfi
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`Page 5 of 23
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`Page 5 of 23
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`

`
`Proceedings of COMPCON ’96
`
`Table of Contents
`
`Message from the General Chair ............................................................................................ .. xi
`
`Message from the Program Chair ........................................................................................ .. xiii
`
`Organizing Committees ........................................................................................................... ..xiv
`
`Session 1: Wireless Interconnects
`
`Chair: John Barr ——— Motorola
`
`CDPD and Emerging Digital Cellular Systems ...................................... ..
`
`
`
`W
`
`T. Melanchuk, P. Dupomr, and S. Backer
`
`a
`
`Wireless Network Extension Using Mobile IP ............................ .
`R.L. Geiger, J.D. Solomon, and KJ. Crisler
`
`The Bay Area Research Wireless Access Network (BARWAN) ............................................. .. 15
`R.H. Katz, EA. Brewer, E. Amir, H. Balakrishnan, A. Fox, S. Gribble,
`T. Hades, D. Jiartg, G.T. Nguyen, V. Padmanabhan, and M. Stemm
`
`Session 2: ATM Networks
`
`Chair: Anujan Varrna —- University of California, Santa Cruz
`
`Performance of Explicit Rate Flow Control in ATM Networks ............................................... ..22
`L. G. Roberts
`
`MPEG-2 Over ATM: System Design Issues ........................................................................... . .26
`S. Varma
`
`FAST: A Simuiation Testbed for ATM Networks .................................................................. .. 32
`D. Stiliadis and A. Varma
`
`Session 3: Broadband Interactive Data Services
`
`Chair: Ilja Bedner — HewIett—Packard
`
`I-IP BIDS — Broadband Interactive Data Solution .................................................................. .. 39
`I. Bedner and A. Ranous
`
`Design Considerations for a Hybrid Fiber Coax High-Speed Data Access Network ................. ..45
`D. Picker
`
`Session 4: Agent Languages
`
`Chair: Adam Hertz —~ General Magic
`
`Mobile Telescript Agents and the Web ................................................................................... .
`P. Dome!
`
`. 52
`
`Mobile Agent Security and Telescript ..................................................................................... .58
`J. Tardo and L. Valente
`
`_'_j:‘
`
`‘
`
`Page 6 of 23
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`Page 6 of 23
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`

`
`
`
`Session 5: World Wide Web
`
`Chair: Robert Hagmann ——~ Oracle
`People, Places, and Things: The Next Generation Web .......................................................... ..65
`J. Gwertzman and M. Seltzer
`An Internet Difference Engine and its Applications ................................................................. ..71
`T. Ball and F. Douglis
`Don’t Get Caught in the Web: A Fieldguide to Searching the Net .......................................... _.77
`W.R. Tuthill
`
`Session 6: World Wide Web Sewers
`
`Chair: Winfried Wilcke »— HAL Computer Systems
`A Scalable and Highly Available Web Server .......................................................................... .. 85
`D.M. Dias, W. Kish, R. Makherjee, and R. Tewari
`
`Session 7: Performance Characterization and Analysis
`Co-Chairs: Nasr Ullah and Marianne Hsiung — Motorola
`The Capture, Characterization, and Performance Analysis of Macintosh® Traces .................... ..94
`S. McMahon
`
`A Measurement Study of Memory Transaction Characteristics on a
`PowerPC—Based Macintosh ................................................................................................... .. 100
`T. Adams
`Load Miss Performance Analysis Methodology Using the PowerPC“’‘ 604 Performance
`Monitor for OLTP Workloads ............................................................................................... .. 111
`E.H. Welbon, RS. Moore, F.E. Levine, and C.P. Roth
`Workload Effects on SMP Scaling in AIX Version 4 ............................................................ .. 117
`K. Dixit, J. Van Fleet, and B. Olszewski
`
`Session 8: Panel — Networking Virtual Environments
`Chair: Michael Zyda -—— Naval Postgraduate School
`Panelists: M. Zyda —— “Networking Large—Scale Virtual Environments”
`T. Meyer — “The Future of VRML”
`M. Macedonia —~— “A Taxonomy for Networked Virtual Environments”
`W. Katz — “Defense and Entertainment Industry Efforts in Networking
`Virtual Environments”
`
`Session 9: PowerPC Microprocessors and Systems
`
`Co-Chairs: Nasr Ullah — Motorola
`
`Kaivalya Dixit — IBM
`Design of the PowerPC 604eTM Microprocessor .................................................................... .. 126
`M. Denman, P. Anderson, and M. Snyder
`The Performance and PowerPC Platformm Specification Implementation of the
`MPC106 Chipset .................................................................................................................. .. 132
`C.D. Bryant, MJ. Garcia, B.K. Reynolds, L.A. Weber, and G.E. Wilson
`
`Page 7 of 23
`
`vi
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`Page 7 of 23
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`

`
`PowerPC Platform: A System Architecture .......................................................................... ..140
`S. Bunch, R. Hochspnmg, and T. Moore
`
`Motorola PowerPCTM Migration Tools — Emulation and Translation ................................... .. 145
`T. Afzal, M. Breternirz, M. Kacher, S. Menyhert, M’. Ommermcm, and W. Su
`
`Session 10: PA-RISC Evolution
`
`Chair: Ruby Lee — Stanford University
`
`64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture ...................................... .. 152
`R. Lee and J. Huck
`
`Mid—Range and High—End PA—RISC Computer Systems ................................. ..; ................... ,. 161
`R. Elsbernd
`
`PA730OLC Integrates Cache for Cost/Performance ............................................................... .. 167
`D. Hollenbeck, S.R. Undy, L. Johnson, D. Weiss, P. Tobin, and R. Carlson
`
`Session 1 1 : Having it your Way — High-Code-Density, High-Integration,
`and High-Performance ARMS
`
`Chair: Allen Baum — Apple Computer
`
`Thumb: Reducing the Cost of 32-bit RISC Performance in Portable and
`Consumer Applications ......................................................................................................... .. 176
`L. Goudge and S. Segars
`
`ARM7100 —m— A High—Integration, Low—Power Microcontroller for PDA Applications .......... .. 182
`G. Budd and G. Milne
`—
`'
`-
`
`StrongARM: A High—Performance ARM Processor ............................................................. .. 188
`R. Wirek and J. Montonaro
`
`Session 1 2: MPEG2
`
`Chair: Vivian Shen — HewletI—Packo:rd
`
`A Scalable Chip Set for MPEG2 Real—Time Encoding ...............
`A. Ngai, J. Sutton, C. Boise, and C. Gebler
`
`.j ...................................... .. 193
`'
`
`Performance Comparison of MPEG1 and MPEG2 Video Compression Standards ................. .. 199
`S. Liu
`
`Mediaprocessing in the Compressed Domain ........................................................................ .204
`V. Bhaskaran
`
`Session 1 3:
`
`Interactive Television
`
`Chair: Robert Hagmann ~— Oracle
`
`A Distributed System Client/Server Architecture for Interactive Multimedia Applications ..... ..2l1
`S. Rege
`
`Dynamic Bandwidth Allocation for Interactive Video Applications over Corporate
`' Networks .............................................................................................................................. .219
`CI. Beckmann
`
`-The Tiger Shark File System ................................................................................................. .226
`R.L. Haskin and F.B. Schmuck
`
`- Page 8 of 23
`
`vii
`
`Page 8 of 23
`
`

`
`
`
`Session 1 4: Interactive ‘IV Settop
`
`Chair: Deven Kalra —- Hewlett—Packard
`Interactive Television Se-ttop Terminal Architectures ............................................................ ..233
`A.N. Nair
`Multimedia Transmission Link Protocol — A Proposal for Digital Information
`Transmission in I-IFC Cable Systems .................................................................................... ..
`R~F. Chin and R. Hutchinson
`DAV1D® System Software V2.0 for Interactive Digital Television Networks ........................ ..
`A. Davidson
`
`239
`
`241
`
`Session 1 5: Scalable Clusters
`Chair: Marco Annaratone —— DEC Western Research Laboratory
`Overview of Memory Channel Network for PCI ................................................................... ..244
`R. Gillett, M. Collins, and D. Pimm
`Digital’s Clusters and Scientific Parallel Applications ........................................................... ..
`R. Kaufmann and T. Reddin
`Overview of Digital UNIX Cluster System Architecture ........................... .. .......................... ..
`W.M. Cardoza, F.S. Glover, and W.E. Snaman, Jr.
`
`250
`
`254
`
`Session 1 6: HAL Computer Systems
`Chair: Winfried Wilcke — HAL Computer Systems
`
`A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip ................................................. ..
`A. Mu, J. Larson, R. Sastry, T. Wicki, and WW. Wilcke
`Performance Limiting Factors in Http (Web) Server Operations ............................................ ..
`F. Prefect, L. Doan, S. Gold, T. Wicki, and W. Wilcke
`
`261
`
`267
`
`Session 17: Exploiting New Storage and Network Technologies
`Chair: Norman 1. Pass —— IBM Almaden Research Center
`SSA: A High—Performance Serial Interface for Unparalleled Connectivity ............................ .274
`A. Wilson
`Redundant Arrays of Independent Libraries (RAIL): A Tertiary Storage System .................. ..
`D.A. Ford, R.J.T. Morris, and A.E. Bell
`Randomized Data Allocation for Real-Time Disk I/O ........................................................... ..
`S. Berson, R.R. Muntz, and W.R. Wong
`
`Services and Architectures for Electronic Publishing ............................................................. ..
`D.M. Choy and RJ. T. Morris
`
`Session 1 8: Multimedia Authoring
`Chair: Michael A. Harrison — University of California, Berkeley
`Graphical Object-Oriented Multimedia Application Development: Technology
`and Market Trends ................................................................................................................ ..
`H. Steger
`-
`
`299
`
`' Page 9 of 23
`
`viii
`
`280
`
`286
`
`291
`
`Page 9 of 23
`
`

`
`Graphical Containment in Multimedia Authoring .................................................................. .. 300
`H. Epelman—Wang, S. Markowitz, and B. Roddy
`'
`
`User Interfaces for Authoring Systems with Object Stores ............................................
`B. Roddy, S. Markowitz, and H. Epelrnan-Wang
`
`..... .. 305
`
`Session 1 9: Competing Architectures for Multimedia Processing
`
`Chair: Cary Kornfeld — consultant
`
`The Mpactm Media Processor Redefines the Multimedia PC ....... .; ....................................... .. 311
`P. Foley
`
`An Architectural Overview of the Programmable Multimedia Processor, TM-1 .................... .. 319
`S. Rathnam and G. Slavenbttrg
`
`Improving Performance for Software MPEG Players ............................................................ .. 327
`D.F. Zucker, MJ. Flynn, and RB. Lee
`
`Session 20: The Microllnity Mediaprocessor
`Chair: Steve Manser — Micro Unity Systems
`
`Architecture of a Broadband MediaProcessor ........................................................................ .. 334
`C. Hansen
`
`MicroUnity Software Development Environment .................................................................. ,_ 341
`R. Hayes, G. Loyola, C. Abbott, and H. Mossalin .
`
`Broadband Algorithms with the MicroUnity Mediaprocessor ................................................ .. 349
`C. Abbott, H. Massalin, K. Peterson, T. Karzes, L. Yamano, and G. Kellogg
`
`Session 21: DRAM Technologies
`
`Chair: S. Peter Song —— Samsnng
`
`Burst and Latency Requirements Drive EDO and BEDO DRAM Standards .......................... ..356
`A. Mormann
`'
`
`Synchronous DRAM Evolutionary Changes Bring Cost!Performance Advantages in
`Memory Systems .................................................................................................................. .. 360
`A.B. Cosoroaba
`I
`
`High Bandwidth RDRAM Technology Reduces System Cost
`R. Crisp
`'
`
`.......................................... ..365
`
`Multi-Gigabyte/sec DRAM with the MicroUnity MediaChannelTM Interface ......................... .. 378
`T. Robinson, C. Hansen, B. Herndon, and G. Rosseel
`
`Session 22: Pentium®Pro System Architecture
`Chair: Konrad Lai — Intel
`
`An Overview of the Pentiurn®Pro Processor Bus .................................................................. ..383
`N. Sarangdhor and G. Singh
`
`Pentiurn®Pro Processor Workstation/Server PCI Chipset ...................................................... .. 388
`M. Bell and T. Holman
`'
`
`Multiprocessor Validation of the Pentium®Pro Microprocessor ............................................. .. 395
`D. Morr, S. Thakkar, and R. Zucker
`
`Page 10 of 23
`
`ix -
`
`Page 10 of 23
`
`

`
`
`
`Session 23': Storage Technology
`
`Chair: Harry S. Gill — IBM
`
`Data Storage IC Technolgy ................................................................................................... .
`J. Kovacs and R. Kroesen
`
`. 402
`
`Session 24: UltraSPAfiC and Java
`
`Chair: Robert Garner — Sun Microsysrerns
`
`UltraSPARCTM: Compiling for Maximum Floating-Point Performance ................................ ..408
`P. Tirumalai, D. Greenley, B. Beylin, and K. Subramanian
`
`U1traSPARC—IFM: The Advancement of UltraCOInputing .................................................... ..417
`G. Goldman and P. Tirumaiai
`
`Java“ and Hotlavaz A Comprehensive Overview ............................................................... ..424
`S. Shaio, A. van Hajj”, and H. Jellinek
`
`Session 25: Desktop Color -— From Eye to Paper
`I
`Chair: Allen Baum — Apple Computer
`Digital Cameras and Electronic Color Image Acquisition .....................
`J. Dalton
`
`...........................
`—
`
`. . . 431 '
`
`Electronic Color Printing Technology ................................................................................... ..435
`. G.K. Starkweather
`.
`
`Co1orSyncTM: Synchronizing the Color Behavior of Your Devices ...................................
`W—L. Chu and S. Swen
`
`.
`
`. . 440
`
`Session 26: Architecture of Workflow Management Systems
`
`Chair: Berthold Reinwald — IBM Almaden Research Center
`
`.........
`Object—Oriented Workflow Technology in InConcert ...............
`.
`S.K. Sarin
`_
`Structured Workflow Management with Lotus Notes Release 4 ................................ .
`B. Reinwaid and C. Mohan
`
`...............
`
`............... ..446
`‘
`_ 45 1
`
`.-........
`
`:E
`
`.s
`
`’
`
`An Architecture for Large—Scale Work Management Systems ...................................... ..'........_458
`M. Beizer
`-
`.
`
`Session 27: “Toy Story”
`
`Chair: Darrell Long — University of California, Santa Cruz
`The Making of Toy Story ._...................................................................................... ... ............ ..463
`M. Henne, H. Hickel, E. Johnson, and S. Konishi
`
`Additional Paper: The following paper was presented as the last paper in Session 12
`
`Single Chip MPEG2 Decoder with Integrated Transport deocder for Set—top Box ................. ..-469
`J. Fandrianto
`
`Author Index ..................................................................................................................... .. 473
`
`Page 11 of 23
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`Page 11 of 23
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`

`
`
`
`An Architectural Overview of the Programmable
`Multimedia Processor, TM-1
`
`Selliah Rathnam, «Gert Slavenburg
`
`Philips Semiconductors
`811 E. Arques Avenue, Sunnyvale, CA 94088
`
`
`
`ABSTRACT
`
`sthe irst in afamily ofprogrammable multimedia
`cessor fi':Jm the Trimedia product group of Philips
`:2: onductors. This "C ” programmable processor
`"a high performance VLIW—CPU core with video and
`peripheral units designed to support the popular
`ti edia applications. TM-I is designed to concur-
`géztly process video, audio, graphics, and communica-
`'
`'
`ata. The VLIW—CP U core is capable of executing a
`imam of twenty seven operations per cycle, and the
`d execution rate is about five operations per cy-
`efo " the tuned a plications. The audio unit easily han-
`tfierent au io formats including the 16-bit stereo
`-The video unit is capable 0 processing difierent
`nd RGB pixelformats with orizontal and vertical
`ing-and color space conversion. TM—1 applications
`
`can range from low-cost, stand alone systems such as
`video
`ones to programmable, multipurpose plug-in
`cards jg)!‘ traditional computers.
`
`M INTRODUCTION
`1.0
`h— erformance multi-
`TM-1 is a buildin —block for hi
`media a plications t at -deal with ig -quality video and
`audio.
`-1 easil
`im lements o ular multimedia stan-
`dards such as MP G- and MP
`-2, but its orientation
`around a powerful general-purpose CPU makes it capa-
`ble of implementing a variety of multimedia algorithms,
`whether open or proprietaxy.
`
`More than just an inte rated microprocessor with un— -
`usual peripherals, the T
`1 microprocessor is a fluid
`
`
`
`Synchronous
`.
`Sena.
`
`Image
`coprocessor
`
`ISDN
`v.34
`Frontnlind
`Down at up scaling
`YUV —> RGE
`
`P
`
`PCE Bus
`
`Huflman decoder
`Sliceéat-a-time
`MPEG-1 3. 2
`
`CCIHSO1/656
`YUV 4:222
`
`YUV 4:2:2
`
`I S DC-80 kHz
`Slergo digital audio
`
`I S DC-80 kHz
`Stargo dlital audio
`
`I20 bus to
`camera, em.
`
` C-‘C|Fl6D1l656
`
`I 1. TM-1 block diagram.
`
`399/96 $5.00 © 1996 IEEE
`‘$2 2, 8s'1182
`‘.
`’96
`e'12of23
`
`319
`
`Page 12 of 23
`
`

`
`CCIRBOHBSB
`YUV 4:2:2
`
`Stereo
`Audio In
`
`CC|Fl6D1:'B5B
`YUV 4:2:2
`
`Stereo
`Audio Out
`
`Front End
`
`v.34 Modern
`
`Figure 2. TM-1 system connections. A minimal
`T -1 system requires few supporting compo-
`nents.
`..
`
`computer system controlled by a small real-time OS ker-
`nel t at runs on the VLIW processor core. TM-1 contains
`a CPU, a hi h-bandwidth internal bus, and internal bus-
`mastering D A peripherals.
`
`TM-l is the first member of a famil of chips that will
`carry investments in software forwar
`in time. Compati-
`bility between family members is at the source-code lev-
`el; binary compatibility between family members is not
`guaranteed. Al
`family members, however, will be able
`to
`erform the most important multimedia functions,
`suc
`as running MPEG-2 software.
`
`Defining software com atibility at the source-code
`level
`ives Philips the free om to strike the optimum bal-
`ance etween cost and performance for all the chips in
`the TM—l family. Powerful compilers ensure that pro-
`grammers seldomly need to resort to non— ortable as-
`sembler
`rogramming. Programmers use T —1’s power-
`ful 1ow— evel operations from source code; these DSP—
`like operations are invoked with a familiar function-call
`syntax. Trimedia also
`rovides hand—coded and tuned
`multimedia libraries w ich can be used to increase the
`performance of the multimedia applications.
`
`As the first member of the family, TM—l is tailored for A
`use in PC-based ap lications. Because it is based on a
`generzgpurpose C
`, TM—1l can serve as a(r:nu1ti—fi£i1nc;
`tion P enhancement vehic e. Typically, a P must e
`with multi—standard video and audio streams, and users
`desire both decompression and compression,_if possible.
`While the CPU chips used in _PCs are becoming ca able
`of low-resolution 1'63]-Ul'l‘l_B video decompression,
`igh»
`§i‘i$“’i§"§i?fi Eii‘i°§i‘12”§§i°“1$.'ifi駰dE§$?‘3§r§§i“ {E31
`their systems provide live video andiaudio without sacri-
`ficin the res onsiveness of the s stem.
`3
`P
`Y
`
`TM—l enhances a PC system to rovide real—time mul-
`timedia, and it does so with the a vantages of a special-
`puppose, embedded solution—low cost and chip count—
`an the advantages of a eneral—purpose rocessor—re—
`programmability. For P
`applications, M—l far sur-
`passes the capabilities of
`ixed—function multimedia
`c ips.
`
`Other Trimedia family members will have different
`sets of interfaces a pro riate for their intended use. For
`example, a TM—] chip or a cable—TV decoder box would
`eliminate the video-in interface.
`
`2.0
`
`TM-1 CHIP OVERVIEW
`
`The key features of TM—l are:
`
`eneral— urpose VLIW proces-
`- A very powerful,
`sor core that coor 'nates al on—chip activities. In
`addition to implementin the non—trivial parts of
`multimedia algorithms,
`is
`rocessor runs a small
`real-time operating system at is driven by inter-
`rupts from the other units.
`- DMA—driven. multimedia input/output units that
`operate independently and that properly format
`data to make processing efficient.
`- DMA—driven multimedia coprocessors that operate
`independently and erform_ operations specific to
`important multime ia algorithms.
`s stem that
`- A hi
`h— erformance bus and memo
`3 P
`.
`.
`Ia }’
`provides communication between T -1 s process-
`ing units.
`
`Figure 1 shows a biock diagram of the TM—l chip. The
`bulk of a TM-1 system consists of the TM-1 micro r -
`cessor itself, a block of synchronous DRAM (SDRA]ivl)
`and minimal external circuitry to interface to the incom-
`ing and/or outgoing multimedia data streams. TM-l can
`gluelessly interface to the standard PCI bus for ersonal-
`computer-based a plications; thus, TM—‘l can e placed
`directly on the P mainboard or on a plug—in card.
`
`Figure 2 shows a possible TM—l system application. A
`video-in ut stream, if present, might come directly from
`a CCIR 01-compliant digital video camera chip in YUV
`412:2 format; the interface is glueless in this case. A non—
`standard camera chi
`can be connected via a video de-
`coder chi
`(such as t e Phili
`s SAA71ll). A CCIR 601
`out ut vi eo stream is provi ed directly from the TM»l
`to rive a dedicated video monitor. Stereo audio input
`and output re uire external ADC and DAC support. he
`operation of
`e video and audio interface units is highly
`customizable through programmable parameters.
`
`The glueless PCI interface allows the TM—l to display
`video via a host PC’s video card and to"
`lay audio via a
`host PC’s sound hardware. The Image oprocessor pro-
`vides dis lay support for live video in an arbitrary num-
`ber of ar itraiily overlapped windows.
`
`Finally, the V.34 interface requires only an external
`modem front—end chip and phone line interface to pro-
`vide remote communication support. The modem can be
`used to connect TM—1—based systems for video phone or
`video conferencing applications, or it can be used for
`general-purpose data communication in PC systems.
`
`3.0 BRIEF EXANIPLES OF OPERATION
`
`The ke to understanding TM— 1' operation is observing
`that the PU and peripherals are time—shared and that
`communication between units is through SDRAM mem~
`
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`320
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`Page 13 of 23
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`

`
`Cry, The CPU switches from one task to the next; first it
`decompresses a video frame, then it decompresses a slice
`of the audio stream, then back to video, etc. As neces-
`gar , the CPU issues commands to the peripheral units. to
`are estrate their operation.
`
`the PCI bus for archival on local mass storage, or the host
`can transfer the compressed video over a network, such
`as ISDN. The data can also be sent to a remote system us-
`ing the integrated V.34 interface to create, for example,
`a video phone or video conferencing system.
`
`The TM-1 CPU can enlist the ICP and video-in units
`to help with some of the straightforward, tedious tasks
`associated with video processing. The function of these
`units is programmable. For example, some video streams
`are——or need to be—scaled horizontally, so these units
`can handle the most common cases of horizontal down-
`and up-scaling without
`intervention from the TM—l
`CPU.
`
`3.1 Video Decompression in a PC
`A typical mode of operation for a TM—l s stem is to
`serve -as a video-decom ression engine on a CI card in
`a PC. In this case, the C doesn’t know the TM—l has a
`powerful, general-purpose CPU; rather, the PC just treats
`the hardware on the PCI card as a “black-box” engine.
`
`Video decompression begins when the PC operating
`s stern hands the TM-1 a pointer to compressed video
`ata in the PC’s memory (t e details of the communica-
`tion rotocol are t pica ly handled by a software driver
`insta led in the PC s operating system).
`
`The TM—l CPU fetches data from the compressed vid-
`eo stream via the PCI bus, decompresses frames from the
`video stream, and places them into local SDRAM. De-
`compression ma be aided by the VLD (variable—length
`decoder) unit, w ich implements Huffman decoding and
`is controlled by the TM-l CPU.
`
`When a frame is ready for dis lay, the TM-l CPU
`ives the ICP (image coprocessorfa display command.
`The ICP then autonomously fetches the decom ressed
`frame data from SDRAM and transfers it over
`e PCI
`bus to the frame buffer in the PC’s video dis la card (or
`the frame buffer in PC system memory if t e C uses a
`UMA (Unified Memory Architecture) frame buffer).
`The ICP accommodates arbitrary window size, position,
`and overlaps.
`
`3.2 Video Compression
`
`Another typical application for TM-l is in video com-
`pression. In this case, uncompressed video is usually
`supplied directly to the TM—l system via the video—in
`unit. A camera chip connected directl
`to the video—in
`unit supplies YUV data in eight-bit,
`12:2 format. The
`video—in unit takes care of sampling the data from the
`camera chip and demultiplexing the raw video to
`§/DRAM in three separate areas, one each for Y, U, and
`
`When a complete video frame has been read from the
`camera chip b the video-in unit, it interrupts the TM—l
`CPU. The CPU compresses the video data in software
`(using a set of powerful data—para1]e1 operations) and
`writes
`the compressed data to a separate area of
`SDRAM.
`
`Since the powerful, general—pu ose TM—l CPU is
`available, the com ressed data can e encrypted before
`being transferred or security.
`
`4.0-
`
`CORE AND PERIPHERAL
`
`UNITS
`
`4.1 VLIW Processor Core
`
`The heart of TM—l is its powerful 32-bit CPU core.
`The CPU implements a 32-bit linear address space and
`128, fully general—purpose 32-bit registers. The registers
`are not separated into banks; any operation can use any
`register for any operand.
`
`The core uses a VLIW instzuction—set architecture and
`is fully general-purpose. TM-1 uses a VLIW instruction
`length t at allows up to five simultaneous operations to
`be issued. These operations can target any five of the 27
`functional units in the CPU, including inte er and float-
`ing-point arithmetic units and data~par
`el DSP-like
`units.
`
`Instruction Cache (32Kb}
`
`Instr. Fetch Buffer
`
`Decompression Hardware
`
`Issue Register ( 5 Ops )
`
`Operation Routing Network
`
`Execution Unit ( 27 Functions )
`
`Register Routing and Forwarding Network
`
`Register File ( 128 X 32 )
`
`The compressed video data can now be disposed of in
`any of several ways. It can be sent to a host system over
`
`Figure 3. VLIW Processor Core and Instruction
`Cache.
`
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`
`
`
`
`Although the processor core runs a tiny real—time op-
`erating system to coordinate all activities in the TM—l
`s stern, t e processor core is not intended for true gener-
`a -purpose use as the only CPU in a computer system.
`For example, the processor core does not im lement vir-
`tual memory address translation, an essentia feature in a
`general—purpose computer system.
`
`TM—l uses a VLIW architecture to maximize roces—
`sor throughput at the lowest possible cost. VL
`archi-
`tectures have performance exceeding that of superscalar
`general-purpose CPUs without the extreme complexity
`of a superscalar implementation. The hardware saved by
`eliminating superscalar logic reduces cost and allows the
`integration of multimedia—specific features that enhance
`the power of the processor core.
`
`The TM—l operation set includes all traditional micro-
`processor operations. In addition, multimedia—specific
`operations are included that dramatically accelerate stan-
`dard video compression and decompression algorithms.
`As just one of the five operations issued in a single TM-
`l instruction, a sin Ie special or “custom” operation can
`implement up to
`1 traditional microprocessor o era-
`tions. Multimedia-specific operations combined wit
`the
`VLIW architecture result in tremendous throughput for
`multimedia applications.
`
`Internal “Data Highway” Bus
`4.2
`The internal data bus connects all internal blocks to-
`ether and provides access to internal control registers
`in each on-chi peripheral units), external SDRAM, and
`the external P I bus. The internal bus consists of sepa-
`rate 32-bit data and address buses, and transactions on
`the bus use a block~transfer protocol. Peripherals can be
`masters or slaves on the bus.
`
`Access to the internal bus is controlled by a central ar-
`ibiter, which has a request line from each otential bus
`master. The arbiter is configurable in a num er of differ-
`ent modes so that the arbitration al oiithm can be tai-
`lored for different ap lications. Perip eral units make re-
`quests to the arbiter or bus access, and dependin on the
`arbitration mode, bus bandwidth is allocated to t e units
`in different amounts. Each mode allocates bandwidth
`differently, but each mode guarantees each unit a mini-
`mum bandwidth and maximum service latency. All un-
`used bandwidth is allocated to the TM—l CPU.
`
`The bus allocation mechanism is one of the features of
`TM—l that makes it a true real—time system in stead ofJust
`a highly integrated microprocessor with unusual periph-
`erals.
`
`4.3 Memory and Cache Units
`
`TM—l’s memory hierarchy satisfies the low cost and
`high bandwidth requirement of multimedia markets.
`Since multimedia video streams can require relatively
`large temporary storage, a significant amount of DRAM
`is required.
`
`TM-l has a glueless interface with s nchronous
`DRAM (SDRAM) or
`synchronous grap ics RAM
`
`(SGRAM), which provide higher bandwidth than the
`standard DRAM. As the SDRAM has been supported by
`major DRAM vendors,
`the competition among those
`vendors will kee the SDRAM rice in par with that of
`the standard D M. TM—1‘s RAM memory size can
`range from 2Mbytes to 64 Mbytes.
`
`The TM—l CPU core is supported b separate l6—KB
`data and 32-KB instruction caches.
`he data cache is
`dual—ported in order to allow two simultaneous load!
`store accesses, and both caches are eight-way set-asso-
`ciative with a 64—byte block size.
`
`4.4 Video-In Unit
`
`The video—in unit interfaces directly to any CCIR 601/
`656—coni liant device that outputs eight—bit parallel,
`412:2
`time-multiplexed data. Such devices include
`direct digital camera systems, which can connect glue-
`lessly to TM—l or through the standard CCIR 656 con-
`nector with only the addition of ECL level converters.
`Non-CCIR-compliant devices can use a di
`ital decoder
`chi
`