`Lam
`
`
`[19]
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`
`[11] Patent Number:
`
`
`[45] Date of Patent:
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`5,960,464
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`
`
`Sep. 28, 1999
`
`US005960464A
`
`
`
`[54] MEMORY SHARING ARCHITECTURE FOR
`
`
`
`
`
`A DECODING IN A COMPUTER SYSTEM
`
`
`
`
`
`[75]
`
`
`Inventor: Christopher S. Lam, San Jose, Calif.
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`
`
`[73] Assigriee: STMicr0electronics, Inc., Carrollton,
`
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`
`Tex.
`
`
`
`
`Doquilo, J., “Symmetric Multiprocessing Servers: Scaling
`
`
`
`
`
`the Performance Wall,” Infoworld, Mar. 27, 1995, pp.
`
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`
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`
`
`82-85, 88-92.
`
`
`Video Electronics Standards Association, “VESA Unified
`
`
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`
`
`Memory Architecture Ilardware Specifications Proposal,”
`
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`
`Version: 1.0p, Oct. 31, 1995, 1995, pp. 1-38.
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`[21] Appl. No.: 08/701,890
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`[22]
`Filed:
`Aug. 23, 1996
`
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`G06F 12/10
`[51]
`Int. Cl.“ ..............................
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`...................... .. 711/206
`[52] U.S. Cl.
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`[58] Field of Search ................................... .. 711/202, 203,
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`711/206, 207; 395/846; 710/22
`
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`
`[56]
`
`
`0 673 171 A2
`
`
`
`
`References Cited
`
`
`U.S. PAl'EN'l‘ D()CUMEN'l'S
`
`
`
`11/1993 Watkins et al.
`.................... .. 395/842
`5,263,142
`
`
`
`
`
`4/1994 llerrell et al.
`.. 711/202
`5,301,287
`.
`
`
`
`
`10/1995 Scalise et al.
`5,459,519
`..................... .. 348/431
`
`
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`.
`9/1995 European Pat. Off.
`
`
`
`
`OTHER PUBLICATIONS
`
`
`
`
`
`
`
`
`Bheda, H. and P. Srinivasan, “A High-Performance Cross-
`
`
`
`
`
`Platform MPEG Decoder,” Digital Wcleo Compression on
`
`
`
`
`
`
`Personal Computers: Algorithms and Technologies, Vol.
`
`
`
`
`
`
`2187, Feb. 7-8, 1994, pp. 241,248.
`
`
`
`
`
`
`Bursky, D., “Highly Integrated Controller Eases MPEG-1
`
`
`
`
`
`
`
`Adoption,” Electronic Design, VOl. 43, No. 17, Aug. 21,
`
`
`
`
`
`
`
`
`
`1995, pp. 141-142.
`
`
`
`Galbi, D. et al., “An MPEG-1 Audio/Video Decoder With
`
`
`
`
`
`
`
`
`Run-Length Compressed Antialiased Video Overlays,”
`
`
`
`
`
`1995 IEEE International Solid-State Circuits Conference,
`
`
`
`
`
`
`pp. 286-287, 381.
`
`
`
`Maturi, G., “Single Chip MPEG Audio Decoder,” IEEE
`
`
`
`
`
`
`
`
`Transactions on Consumer Electronics, Vol. 38, No. 3, Aug.
`
`
`
`
`
`
`
`1992, pp. 348-356.
`
`
`
`Butler, B. and T. Mace, “The Great Leap Forward,” PC
`
`
`
`
`
`
`
`
`Magazine, Oct. 11, 1994, pp. 241-244, 246, 248, 250,
`
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`
`
`
`
`
`
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`253-254, 256, 260-261, 264, 266-268, 273-275, 278.
`
`
`
`
`
`
`
`
`(List continued on next page.)
`
`
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`
`
`
`[57]
`
`Primary Examiner—Eddie P. Chan
`
`
`
`Assistant Examiner—Kevin L Ellis
`
`
`
`Attorney, Agent, or Firm—DaVid V. Carlson, Theodore E.
`
`
`
`
`
`
`Galanthay; Lisa K. Jorgenson
`
`
`
`ABSTRACT
`
`
`
`Amethod and apparatus employing a memory management
`
`
`
`
`
`
`
`system that can be used with applications requiring a large
`
`
`
`
`
`
`
`
`contiguous block of memory, such as video decompression
`
`
`
`
`
`
`techniques (e.g., MPEG 2 decoding). The system operates
`
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`
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`
`
`
`with a computer and the computer’s operating system to
`
`
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`
`
`request and employ approximately 500 4-kilobyte pages in
`
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`
`
`two or more noncontiguous blocks of the main memory to
`
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`
`
`
`
`
`construct a contiguous 2-megabyte block of memory. The
`
`
`
`
`
`
`system can employ, on a single chip, a direct memory acoess
`
`
`
`
`
`
`
`
`engine, a microcontroller, a small block of optional memory,
`
`
`
`
`
`
`and a Video decoder circuit. The microcontroller retains the
`
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`
`blocks of multiple pages of the main memory, and the page
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`
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`descriptors of these blocks, so as to lock down these blocks
`
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`
`
`of memory and prohibit
`the operating system or other
`
`
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`
`
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`
`
`
`applications from using them. The microcontroller requests
`
`
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`
`
`the page descriptors for each of the blocks, and programs a
`
`
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`
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`
`
`
`lookup table or memory mapping system in the on-chip
`
`
`
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`
`
`
`
`memory to form a contiguous block of memory. As a result,
`
`
`
`
`
`
`the Video decoder circuit can perform operations on a
`
`
`
`
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`
`2-megabyte contiguous block of memory, where the micro-
`
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`
`controller employs the lookup table to translate each
`
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`
`
`2-megabyte contiguous address requested by the Video
`
`
`
`
`
`
`
`decoder circuit to its appropriate page in the main memory.
`
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`
`
`As soon as the Video decoding operations are complete, the
`
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`
`
`
`microcontroller releases the blocks of multiple pages of
`
`
`
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`
`
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`memory back for use by the computer.
`
`
`
`
`
`
`
`40 Claims, 3 Drawing Sheets
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`WVNDOWS 95
`
`
`
`
`DVD INFORMATION
`FILE MANAGER
`
`
`--1 AJDIO DRIVER
`
`
`
`VVDEO OBJECTS MANAGER \759
`
`
`
`
`
`
`
`
`
`760
`
`VIDEO DRIVER
`
`
`
`
`
`,L
`GISPLAY
`-2.
`
`®@
`
`/56
`
`
`
`DVD DRIVER
`
`
`
`
`115
`
`
`
`I
`DVD
`
`/1
`
`
`
`Samsung Exhibit 1001
`
`Page 1 of 11
`
`
`
`
`
`
`
`
`
`Giorgis, T., “SMP Network Operating Systems,” Computer
`
`
`
`
`
`
`Dealer News, Aug. 8, 1996, pp. 42, 43.
`
`
`
`
`
`
`
`King, A., Inside Windows 95, Microsoft Press, Redmond,
`
`
`
`
`
`
`
`Washington, 1994, pp. 85-90.
`
`
`
`
`“MPEG Video Overview,” SGS-Thomson Microelectronics
`
`
`
`
`Technical Note, Apr. 1992, pp. 1-4.
`
`
`
`
`
`
`
`5,960,464
`Page 2
`
`
`
`
`OTHER PUBLICATIONS
`
`
`
`Video Electronics Standards Association, “VESA Unified
`
`
`
`
`
`
`Memory
`Architecture
`VESA
`BIOS
`Extensions
`
`
`
`
`
`(VUMA—SBE) Proposal,” Version: 1.0p, Nov. 1, 1995, pp.
`
`
`
`
`
`
`
`1-26.
`
`
`Page2of11
`
`Page 2 of 11
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`
`
`U.S. Patent
`
`Sep.28, 1999
`
`Sheet 1 of3
`
`5,960,464
`
`/02
`
`I08
`
`706
`
`
`
`MNN
`MEMORY
`
`
`
`
`
`G2
`
`
`MPEDECODER
`
`\\/O0
`
`‘
`Q30
`
`—:
`
`I I I
`
`I L
`
`\
`
`'
`:
`I
`
`I I I
`
`:
`
`{ I
`
`Fig. 1
`
`/24
`
`/20
`
`
`
`
`MEMORY
`WCR0
`(OPHONAL)
`_C_O_N_T_|ROLLER
`
`
`MMU'
`
`
`
`
`
`vIDEO
`DECOD|NG
`CIRCUIT
`
`
`
`
`DECODING
`CIRCUIT
`
`
`
`/29
`
`I
`
`Page3of11
`
`Page 3 of 11
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`
`U.S. Patent
`
`
`
`Sep.28, 1999
`
`
`
`
`Sheet 2 of3
`
`
`5,960,464
`
`
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`762
`
`
`
`/54
`
`
`
`I52
`
`
`
`755
`
`
`
`
`
`
`USER
`INTERFACE
`
`
`
`
`WINDOWS 95
`
`
`
`
`
`
`
`DVD INFORMATION
`
`
`
`FILE MANAGER
`
`
`
`
`AUDIO DRIVER
`
`
`
`
`
`
`
`
`
`
`
`VIDEO OBJECTS MANAGER
`
`
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`
`
`
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`Page4of11
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`Page 4 of 11
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`U.S. Patent
`
`
`Sep. 28, 1999
`
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`
`Sheet 3 of 3
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`5,960,464
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`202
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`
`204
`
`205
`
`
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`
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`PROGRAM THE
`
`
`
`DESCRIPTORS IN
`
`
`
`THE MPEG CHIP
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`
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`270
`
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`mg. 4
`
`Page5of11
`
`START THE
`
`
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`WINDOWS APPLICATION
`
`
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`
`
`LOCK DOWN
`
`
`
`
`ZMBIT or MEMORY
`
`
`
`Page 5 of 11
`
`
`
`5,960,464
`
`1
`
`MEMORY SHARING ARCHITECTURE FOR
`
`
`
`
`A DECODING IN A COMPUTER SYSTEM
`
`
`
`
`CROSS-REFERENCE TO RELATED
`
`
`APPLICATIONS
`
`
`This application relates to the following U.S. Patent
`
`
`
`
`
`
`
`
`Applications: “VIDEO AND/OR AUDIO DECOMPRES-
`
`
`
`
`
`SION AND/OR COMPRESSION DEVICE THAT
`
`
`
`
`
`10
`SHARESAMEMORY INTERFACE” (U.S. Pat. No. 5,812,
`
`
`
`
`
`
`789 issued on Sep. 22, 1998) and “VIDEO AND/OR
`
`
`
`
`
`
`
`
`
`AUDIO DECOMPRESSION AND/OR COMPRESSION
`
`
`
`
`DEVICE THAT SHARES A MEMORY” (U.S. application
`
`
`
`
`
`
`Ser. No. 08/702,910)[, and “MPEG DECODER TO BE
`
`
`
`
`
`
`USED IN A MICROCOMPUTER” (Attorney’s Docket No.
`
`
`
`
`
`
`
`
`
`
`95-GR2-041), all] filed concurrently herewith.
`TECHNICAL FIELD
`
`
`
`15
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`The present invention relates to the field of electronic
`
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`systems requiring blocks of memory, and is more specifi-
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`cally directed to systems employing decompression devices,
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`
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`such as audio and/or video decompression.
`
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`
`
`BACKGROUND OF THE INVENTION
`
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`
`20
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`2
`
`Current computers, such as personal computers, employ
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`graphics or video accelerator cards that permit the computer
`
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`to rapidly display static images. Personal computers are
`
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`
`
`
`typically unable to decompress and display video images
`
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`
`
`because the decompression or decoding routines typically
`
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`
`
`require substantial processor overhead. For example, the
`
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`
`
`MPEG 2 standard decodes 720 pixels per line and 576 lines
`
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`per frame for a single image, and approximately 30 frames
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`per second. As is known, each frame is divided into a series
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`of 16 pixel by 16 pixel macroblocks, so that for each second,
`
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`the processor must decode 48,600 macroblocks per second.
`
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`Consequently,
`the time interval between decoding each
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`
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`macroblock is approximately 2.0576 microseconds. If a
`
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`
`
`CPU in the PC is running at 100 megahertz, then only 2,057
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`
`
`
`clock cycles are available between decoding of each mac-
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`
`
`roblock. This is an inadequate number of clock cycles to
`
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`decode a given macroblock given the complexity of the
`
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`decoding function under the MPEG 2 standard.
`
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`
`
`As a result, chip sets have been developed that employ a
`
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`
`dedicated microcontroller, a MPEG 2 decompression chip,
`
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`
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`and a large amount (e.g., 2 megabytes) of memory, such as
`
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`
`
`DRAM. Such chip sets can be expensive, particularly since
`
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`
`
`they require 2 megabytes of DRAM. Thus,
`it would be
`
`
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`
`
`desirable to employ the main memory of the computer,
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`
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`
`
`which typically has over 8 megabytes of DRAM.
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`
`Some applications exist that share the main memory. For
`
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`
`
`
`
`
`example,
`the symmetrical multiprocessor environment
`(SMP) by Intel employs two or more identical processors
`
`
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`
`
`
`that each access the same block of main memory. However,
`
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`
`
`each of the microprocessors employs a memory manage-
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`
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`
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`ment unit (MMU) that has an identical memory mapping
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`table. Neither microprocessor can permanently allocate a
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`
`
`portion of the main memory. Instead, as soon as one of the
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`microprocessors no longer employs a portion of the memory,
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`and the address of that memory is removed from its memory
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`map, then the other microprocessor is free to use that portion
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`of memory. Additionally, the SMP environment requires a
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`specific operating system.
`Another known method of sharing main memory is
`
`
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`
`
`employed with graphics accelerators in personal computers.
`
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`
`
`Previously, graphics or video accelerator cards included
`
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`
`
`on-board memory chips. However, under the Video Elec-
`
`
`
`
`
`
`
`
`tronics Standards Association (VESA), a VESA unified
`
`
`
`
`
`
`memory architecture (VUMA) standard has been developed.
`
`
`
`
`
`
`
`Under this standard, video accelerators can share main
`
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`
`
`memory with the computer to thereby eliminate the need for
`
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`
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`
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`on-board memory for the graphics accelerator. During boot-
`
`
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`
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`up of the computer system employing the video accelerator,
`
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`
`
`the video accelerator will cause the basic input/output
`
`
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`
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`
`
`instructions (BIOS) of the computer to reserve a large
`
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`
`
`portion of contiguous memory in the main memory, and
`
`
`
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`
`
`
`prohibit the operating system or other applications from
`
`
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`
`
`accessing or employing that memory.
`
`
`
`
`However,
`typical operating systems such as Windows
`
`
`
`
`
`
`95®, manufactured by Microsoft Corporation, do not permit
`
`
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`
`
`large blocks of memory to be permanently allocated for a
`
`
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`
`
`given application or operation after booting up the computer.
`
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`
`Instead, Windows 95 dynamically allocates memory to an
`
`
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`
`
`
`application based on the need of that application. As soon as
`
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`
`
`the application no longer uses the memory, Windows 95
`
`
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`allocates that memory to another application. Moreover,
`
`
`
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`
`
`MPEG 2 decoding requires 2 megabytes of contiguous
`
`
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`
`
`
`memory. Windows 95 allocates small blocks of memory
`
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`
`
`(typically “pages” of 4 kilobytes each) that are scattered
`
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`
`throughout the main memory.
`
`
`
`
`SUMMARY OF THE INVENTION
`
`
`
`One solution the inventor has developed would be to
`
`
`
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`
`
`
`initialize the computer during the boot-up process to reserve
`
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`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`In the past, moving images were transmitted via analog
`
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`
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`signals, such as television signals. To improve signal to
`
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`noise ratio and improve security, while also potentially
`
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`
`
`providing additional signals over a given channel, moving
`
`
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`
`images are digitized and transferred digitally. The size of a
`
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`
`
`digital representation of moving images (i.e., video) is
`dependent on the resolution of the image. If a display device,
`
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`
`
`
`such as a CRT, has a resolution of 1024x768 picture ele-
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`ments (pels or pixels), where each pixel can have an 8-bit
`
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`color value, one image requires approximately 3A: of a
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`megabyte of memory. At a minimum, 30 images must be
`
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`displayed per second, thereby requiring over 22 megabytes
`
`
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`
`
`of memory per second. A typical 90-minute movie would
`
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`thus require nearly 120 gigabytes of memory.
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`As a result of such need for memory to store a typical
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`movie, digitized video is compressed using various digital
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`compression techniques. One such technique for compress-
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`ing video is the Digicypher II system by General Instru-
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`ments. Such a system allows for compressed video and
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`audio images to be transmitted over high bandwidth chan-
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`nels such as satellite transmission. Other known techniques
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`for encoding/decoding video images include the Motion
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`Picture Expert Group (MPEG) techniques MPEG 1 and
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`MPEG 2. Current encoding/decoding standards for video
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`telephony include the H.261 and H.263 standards.
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`Many of the compression/decompression standards
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`employ the known discrete cosine transfer algorithm (DCT).
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`The MPEG 1, MPEG 2, H.261 and H.263 standards are
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`decompression protocols that describe how an encoded bit
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`stream is to be decoded. As a result,
`the video can be
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`encoded in any manner, as long as the resulting bit stream
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`complies with the particular standard.
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`Once encoded, the images can be decoded and displayed
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`on an electronic system dedicated to displaying video and
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`audio, such as a television or digital video disk (DVD)
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`player, or on electronic systems where displaying images are
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`just one of the features of the system, such as a computer. A
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`given electronic system must include an appropriate decoder
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`to allow it to display digital sequences of images com-
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`pressed under one of the above standards, assuming the
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`original video was compressed using an encoder under that
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`standard.
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`a 2 megabyte portion of contiguous memory, as is performed
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`with video accelerators under the VUMA standard. Such an
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`allocation of memory, however, is awkward, and therefore
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`undesirable by users. Additionally, such a solution would
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`prohibit “on-the-fly” display of video information on the
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`computer. Instead, the computer must be rebooted whenever
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`the computer wishes to use the 2 megabyte portion for other
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`applications.
`The present invention solves problems inherent in the
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`prior art and in the inventor’s above solution, and provides
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`additional advantages, by employing a memory manage-
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`ment system that operates with the computer and its oper-
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`ating system (e.g., Windows 95) to request and employ
`approximately 500 4-kilobyte pages of the main memory,
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`some of which are in noncontiguous blocks of pages,
`to
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`construct a single contiguous 2-megabyte block of memory.
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`The system retains the multiple pages of memory, and their
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`page descriptors, so as to lock down these portions of
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`memory and prohibit the operating system or other appli-
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`cations from using them. The memory management system
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`can be employed on a single chip having a direct memory
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`access (DMA) engine, a microcontroller, a small block of
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`memory (optional), and a video decoder circuit (e.g., an
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`MPEG 2 decoder circuit).
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`The microcontroller, performing a Windows 95 memory
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`allocation application, requests the page descriptors for each
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`block of 4-kilobyte pages. Each of the page descriptors is
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`then stored in the form of a lookup table in the on-chip
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`memory to form a contiguous block of memory. As a result,
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`the video decoder circuit can perform operations on what
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`appears to be a 2-megabyte continuous block of main
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`memory, where the microcontroller employs the lookup
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`table to translate one of the 2-megabyte contiguous
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`addresses to its appropriate page in the main memory. As
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`soon as the video decoding operations are complete,
`the
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`microcontroller releases the multiple pages of memory back
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`to the computer.
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`Broadly stated, the present invention embodies a control
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`circuit for use in a computer system. The computer system
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`is controlled by an operating system and has a main memory.
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`An electronic device is coupled to the processor and the
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`main memory and is configured to request continuous use of
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`several portions of the main memory from the operating
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`system. The memory portions can have noncontiguous
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`addresses. The control circuit is also configured to translate
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`the noncontiguous addresses to contiguous addresses of a
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`block of memory, wherein the control circuit permits access
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`to the portions of the main memory as the block of memory
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`based on the contiguous addresses.
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`Broadly stated,
`the present invention also embodies a
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`memory management method for use with the computer
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`system. The memory management method includes the steps
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`of: (a) requesting continuous use of several portions of the
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`main memory from the operating system, the portions of the
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`main memory having noncontiguous addresses; (b) receiv-
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`ing requests for access to a block of memory, the block of
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`memory having contiguous addresses; and (c) translating the
`contiguous addresses to the noncontiguous addresses.
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`Overall, the present invention is applicable to any appli-
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`cation requiring a large block of contiguous memory, not
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`necessarily video decoding. Other features and associated
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`advantages of the present invention will become apparent
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`from studying the following detailed description, together
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`with the accompanying drawings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a block diagram of a computer system having an
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`MPEG 2 decoder under the present invention.
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`10
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`Page7of11
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`4
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`FIG. 2 is a block diagram of the MPEG 2 decoder of FIG.
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`FIG. 3 is a block diagram of software elements employed
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`by the computer system of FIG. 1.
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`FIG. 4 is a flowchart of a routine performed by the MPEG
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`2 decoder of FIG. 1.
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`DETAILED DESCRIPTION OF THE
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`PRESENTLY PREFERRED EMBODIMENT
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`Referring to FIG. 1, a computer system 100 under the
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`present invention includes a computer 102, such as a con-
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`ventional personal computer (PC). The computer 102
`includes a central processing unit (CPU) 104, which can be
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`an X86 based microprocessor. The CPU 104 communicates
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`with a large block of main memory 106 through a memory
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`controller 108. As will be understood below,
`the main
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`memory 106 should include at least approximately 4 mega-
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`bytes of memory (typically random access memory
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`A visual display device, such as a CRT 110, displays
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`output produced by the computer 102. A digital video disk
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`(DVD) compact disk-read only memory (CD-ROM) player
`112, coupled to the computer 102, plays back video images
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`to the computer from a DVD CD-ROM disk 113, which can
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`be displayed on the CRT 110. The DVD CD-ROM disk 113
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`is a super-density disk that can hold up to 18 gigabytes of
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`audio, video and other types of data (eg., menus in various
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`the
`languages, sub-pictures, graphics, etc.). Specifically,
`DVD CD-ROM player 112 retrieves video images that have
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`been compressed under known video compression tech-
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`niques such as the MPEG 2 technique.
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`An MPEG 2 decoder 114, coupled to the computer 102,
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`decodes the compressed video images from the DVD
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`CD-ROM player 112 to reconstruct the original, uncom-
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`pressed video images so that they can be displayed on the
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`CRT 110. The DVD CD-ROM player 112 can also provide
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`compressed audio sequences which the MPEG 2 decoder
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`114 decodes using known audio decompression techniques
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`(e.g., Dolby AC-3). The computer system 100 of FIG. 1 can
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`also contain other peripherals and elements, not shown, such
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`as a hard disk drive, tape drive, input devices such as a
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`keyboard or mouse, etc.
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`Referring to FIG. 2, the MPEG 2 decoder 114 is shown in
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`greater detail. A microcontroller 120 having a memory
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`management unit 122 (MMU) operates under a routine
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`described below to decode audio and video from the DVD
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`CD-ROM player 112. A direct memory access (DMA)
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`engine 124 coupled between the microcontroller 120 and the
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`computer 102 allows the microcontroller to directly access
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`the main memory 106, without employing the CPU 104. The
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`DMA engine 124 can form part of a video module interface
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`(VMI). The DMA engine 124 and VMIinterfaces are
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`conventional, and are not described in detail herein for
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`purposes of brevity and so as not to obscure the detailed
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`description of the present invention.
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`A video decoding circuit 126, coupled to the microcon-
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`troller 120, decodes or decompresses the video images
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`stored on the DVD CD-ROM disk 113 in the DVD
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`CD-ROM player 112. Preferably, the video decoding circuit
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`126 employs conventional MPEG 2 decoding techniques.
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`Alternatively, or in addition, the video decoding circuit 126
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`can decode video images compressed under the MPEG 1,
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`JPEG, H.261, or other known video compression tech-
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`niques.
`In general,
`the MPEG compression standard is
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`described in SGS-Thomson Microelectronics, Technical
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`Note, MPEG Video Overview, April 1992.
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`An audio decoding circuit 128 similarly decodes audio
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`compressed on the DVD CD-ROM disk 113 in the DVD
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`Page 7 of 11
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`5,960,464
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`6
`The video objects manager 159 is a lower level traffic
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`controller responsible for the parsing of different packets of
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`video, and time synchronization for video and audio “lip
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`synching.” Each video object contains video, audio, sub-
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`picture data, and other data as appropriate. The video and
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`audio packets contain MPEG 2 elementary video stream and
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`system information, i.e., presentation time stamps, scram-
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`bling control, clock data, etc., as is known in the MPEG 2
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`standard. The video objects manager 159 parses the packets
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`and provides appropriate synchronization. The video objects
`manager 159 routes the video packets to a video driver 160,
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`and routes the audio packets to an audio driver 162. In sum,
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`the video objects manager 159 is a system coordinator. As
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`long as the video objects manager 159 obtains data from the
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`DVD driver 156, it routes the data to the appropriate video
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`and audio drivers 160 and 162.
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`The video driver 160 decodes the video under the MPEG
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`2 technique. Likewise the audio driver 162 decodes the
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`audio packets under the Dolby AC-3technique, or other
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`techniques. The video driver 160 and audio driver 162 can
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`be implemented as a combination of both hardware and
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`software elements. The video driver 160 outputs video to the
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`CRT 110, while the audio driver 162 outputs sound to a
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`speaker (not shown).
`In operation,
`the DVD information file manager 158
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`retrieves menu data from the DVD CD-ROM disk 113,
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`through the DVD driver 156, to display a menu through the
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`user interface 154 on the CRT 110. Auser inputs a request,
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`which is received by the DVD information file manager 158
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`that in response thereto, allocates a location and number of
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`sectors on the DVD CD-ROM disk 113 and requests the
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`appropriate information from the DVD driver 156. The
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`DVD driver 156 then reads the appropriate information from
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`the DVD CD-ROM disk 113 and transfers the video objects
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`data, and/or other data, to the DVD information file manager
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`158.
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`The video objects manager 159 parses the video objects
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`into video, audio, sub-picture and other data packets. The
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`video objects manager 159 transfers the video and audio
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`packets to the video and audio drivers 160 and 162,
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`respectively, under synchronism according to time stamps.
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`The video driver 160 then employs known MPEG 2 decod-
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`ing techniques to decode the video and display it on the CRT
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`110. Similarly, the audio driver 162 employs known Dolby
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`AC-3techniques to decode the audio packets and play them
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`back over the speaker. The decoding of audio and video
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`continues until a break occurs, or the user interrupts the
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`process by a user command to the user interface 154.
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`Importantly, the MPEG 2 decoding technique, performed
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`at least in part by the video driver 160, requires 2 megabytes
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`of memory because of temporal compression employed by
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`
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`
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`the technique to compress information and eliminate redun-
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`
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`
`
`dancy therein. The MPEG 2 encoding technique refers to
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`previous and future pictures to encode a current picture. As
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`the MPEG 2 decoding technique must refer to
`a result,
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`previous and future pictures to decode a current picture.
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`Thus, the MPEG 2 technique must store at least two images
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`(past and future) to generate a current image. While prior
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`MPEG 2 decoding circuits employed dedicated memory, the
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`present invention shares the main memory 108 with the
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`computer 102.
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`Referring to FIG. 4, a memory sharing routine 200
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`performed by the microcontroller 120 (FIG. 2) operates with
`the Windows 95 operating system 152 (FIG. 3) to request a
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`2-megabyte portion of the main memory 106. The routine
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`200 can form part of the DVD information file manager 158
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`5
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`CD-ROM player 112. The audio decoding circuit 128 pref-
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`erably employs known audio decoding techniques, such as
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`the Dolby AC-3technique. The video decoding circuit 126
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`and audio decoding circuit 128 are of conventional
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`construction, and are not described in detail herein for
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`purposes of brevity and so as not to obscure the detailed
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`description of the present invention.
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`An optional memory 129, coupled to the microcontroller
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`120, provides storage for a lookup table or memory map, as
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`described below. The microcontroller 120, DMA engine
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`124, video decoding circuit 126, audio decoding circuit 128,
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`and memory 129 can be monolithically integrated as a single
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`chip 130 for use with or in the computer system 100.
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`Referring to FIG. 3, the computer 102 preferably operates
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`under the conventional Windows 95 operating system 152.
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`A user interface 154, forming a high-level part of the
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`Windows 95 operating system 152, provides an interface to
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`a user of the computer system 100. The Windows 95
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`operating system 152 provides services for the user interface
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`154 and “hooks” for all drivers to permit operation there-
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`with. Execution process of drivers and other application
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`programs start from the user interface 154. Upon request by
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`such programs, a first menu appears to the user on the CRT
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`110, allowing the user to select menu items to initiate
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`sequences of events performed by the application, such as
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`initiating viewing of a movie stored on the DVD D-ROM
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`disk 113.
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`A DVD driver 156 employs the hooks of the operating,
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`system 152 and routes data from the DVD CD-ROM disk
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`113 to a DVD information file manager 158 and video
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`objects manager 159. In general, there are two basic levels
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`of data structures on the DVD CD-ROM disk 113, a volume
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`information file which keeps track of the physical locations
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`of lower level data structures, and video objects which
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`contain data packets for all types of data. Physical locations
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`of data on the DVD CD-ROM disk 113 are provided in terms
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`of sectors, each being 2048 bytes long. The DVD driver 156
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`essentially performs the task of reading data from the DVD
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`CD-ROM disk 113. The DVD information file manager 158
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`provides the DVD driver 156 with a physical disk location
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`and a length of data. The DVD driver 156, in turn, transfers
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`the requested data from the DVD CD-ROM disk 113 to a
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`known location in the main memory 106, as described
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`below.
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`The DVD information file manager 158 reads the volume
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`information file from the DVD CD-ROM disk 113 to
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`determine the physical locations of video titles, menu titles
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`for each language, title attributes, etc. that are sto