UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_______________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_______________
`
`
`
`
`
`APPLE INC.
`Petitioner
`
`v.
`
`LONGITUDE FLASH MEMORY SYSTEMS S.A.R.L.
`Patent Owner
`
`_______________
`
`Case IPR2015-01945
`Patent 7,818,490
`
`_______________
`
`
`
`PATENT OWNER LONGITUDE FLASH MEMORY SYSTEMS S.A.R.L.
`AND EXCLUSIVE LICENSEE LONGITUDE LICENSING LTD.’S
`PRELIMINARY RESPONSE
` 
`
` 
`
`

`
`A. 
`
`Table of Contents
`Introduction ....................................................................................................... 1 
`I. 
`II.  Background ....................................................................................................... 2 
`A.  About U.S. Patent No. 7,818,490 (the “‘490 patent”) .................................. 2 
`B. 
`Petitioner’s Grounds of Challenge ................................................................ 8 
`III.  Claim Construction ......................................................................................... 10 
`A. 
`“metablock” ................................................................................................. 11 
`IV.  The Petitioner Does Not Demonstrate That It Is More Likely Than Not to
`Prevail On Any Challenged Claim on the ‘490 Patent ................................... 12 
`Petitioner Fails to Demonstrate That Wells Anticipates Claims 94-97, 102,
`and 104-105 (Ground 1) .............................................................................. 13 
`
`  The Petitioner Fails To Demonstrate That Wells Discloses “a plurality of 1.
`sub-arrays of memory storage elements in which programming operations
`may be performed independently,” As Recited In Independent Claim 94. 13 
`
`  The Petitioner Fails To Demonstrate That Wells Discloses “linking 2.
`together blocks within the plurality of sub-arrays to form a plurality of
`metablocks…” As Recited In Independent Claim 94 ................................. 15 
`
`  The Petitioner Fails To Demonstrate That Wells Discloses “programming 3.
`the one or more pages of updated data of the file into individual ones of the
`erased second plurality of pages in only the second block,” As Recited By
`Claim 96 ...................................................................................................... 16 
`
`  The Petitioner Fails To Demonstrate That Wells Discloses “wherein 4.
`programming the pages of original data includes programming the pages of
`original data of the file in an order of their associated logical addresses,”
`As Recited By Claim 97 .............................................................................. 18 
`
`  The Petitioner Fails To Demonstrate That Wells Discloses “organizing the 5.
`read pages of original data of the file that have not been updated and the
`pages of updated data of the file in an order of their associated logical
`addresses,” As Recited By Claim 104 ........................................................ 19 
`
`ii
` 
`
`

`
`C. 
`
`1. 
`
`2. 
`
`3. 
`
`B. 
`
`
`  The Petitioner Fails To Demonstrate That Wells Discloses “transferring out 6.
`of the memory system the read pages of original data that have not been
`updated and the read pages of updated data,” As Recited By Claim 105 .. 20 
`The Petitioner Fails To Demonstrate That Wells and Niijima Render
`Obvious Claims 98, 100, and 103 (Ground 2) ............................................ 21 
`The Petitioner Fails To Demonstrate That Wells and the Knowledge of
`One of Ordinary Skill in the Art Render Obvious Claims 66, 68, and 70
`(Ground 3) ................................................................................................... 24 
`The Petitioner Fails To Demonstrate That Wells and the Knowledge of
`One of Ordinary Skill in the Art Teach “blocks being organized in at least
`two separate units in which programming may be performed
`independently,” as Recited in Independent Claim 66 ................................. 24 
`The Petitioner Fails To Demonstrate That Wells and the Knowledge of
`One of Ordinary Skill in the Art Teach “linking at least one block from
`individual ones of said at least two units to form a metablock wherein the
`storage elements of its component blocks are erased together,” as Recited
`in Independent Claim 66 ............................................................................. 25 
`The Petitioner Fails To Demonstrate That Wells and the Knowledge of
`One of Ordinary Skill in the Art Teach “programming replacement data
`into another at least one block in only a designated one of the units
`regardless of which unit the data being updated are stored,” as Recited in
`Independent Claim 66 ................................................................................. 25 
`D.  The Petitioner Fails To Demonstrate That Wells, the Knowledge of One of
`Ordinary Skill in the Art, and Niijima Render Obvious Claim 67 (Ground
`4) .................................................................................................................. 28 
`The Petitioner Fails To Demonstrate That Wells, the Knowledge of One of
`Ordinary Skill in the Art, and the Admitted Prior Art or Miyauchi Render
`Obvious Claims 69, 99, and 101 (Ground 5) .............................................. 29 
`The Petitioner Fails To Demonstrate That Wells, the Knowledge of One of
`Ordinary Skill in the Art, and the Admitted Prior Art or Cappelletti
`Renders Obvious Claims 71 and 106 (Ground 6) ....................................... 31 
`G.  Ground 7 ...................................................................................................... 33 
`
`E. 
`
`F. 
`
`iii
` 
`
`

`
`H.  The Petitioner Fails To Demonstrate That Wells, and the Knowledge of
`One of Ordinary Skill in the Art, Hazen, or Dipert, Render Obvious Claims
`66-72 and 94-106 (Ground 8) ..................................................................... 33 
`Reservation of Argument Regarding Other Deficiencies ........................... 34 
`I. 
`V.  Conclusion ...................................................................................................... 35 
`
`
`
`
`
`iv
` 
`
`

`
`Cases 
`
`Table of Authorities
`
`Corning Incorporated v. DSM IP Assets B.V., IPR 2013-00048, paper 94 (PTAB
`5/9/2014) ............................................................................................................... 17
`Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966) ............................. 21
`In re Translogic Tech., Inc., 504 F.3d 1249 (Fed. Cir. 2007) ................................. 11
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007) ................................................ 21
`Liberty Mutual v. Progressive Casualty, CBM2012-00003, paper 8 (PTAB
`10/25/2012) .................................................................................................... 20, 21
`Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359 (Fed. Cir. 2008) ..................... 13
`OSRAM Sylvania, Inc. v. Am. Induction Techs., Inc., 701 F.3d 698 (Fed. Cir. 2012)
` ............................................................................................................................... 22
`SanDisk Corp. v. Kingston Tech. Co., 2011 U.S. Dist. LEXIS 27696 (W.D. Wis.
`Mar. 15, 2011) ................................................................................................ vii, 29
`Verdegaal Bros. v. Union Oil Co. of California, 814 F.2d 628 (Fed. Cir. 1987) .... 13
`Statutes 
`
`35 U.S.C. § 102 ................................................................................................... 9, 13
`35 U.S.C. § 102(b) ..................................................................................................... 9
`35 U.S.C. § 103(a) ..................................................................................................... 9
`35 U.S.C. § 314(a) ........................................................................................ 1, 12, 35
`Other Authorities 
`
`M.P.E.P. § 2131 ....................................................................................................... 13
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48756 (Aug. 14, 2012) ............... 10
`Rules 
`
`37 C.F.R. § 42.22(a)(2) .............................................................................................. 1
`37 C.F.R. § 42.65(a) ............................................................................................ 1, 17
`37 C.F.R. § 42.100(b) .............................................................................................. 11
`37 C.F.R. § 42.104(b)(4) ............................................................................................ 1
`37 C.F.R. § 42.104(b)(5) ............................................................................................ 1
`Fed. R. Evid. 705 ..................................................................................................... 17
`
`
`v
` 
`
`

`
`LIST OF PATENT OWNER’S EXHIBITS
`
`Description
`Claim Construction Opinion and Order, SanDisk Corp. v.
`Kingston Tech. Co., 2011 U.S. Dist. LEXIS 27696 (W.D. Wis.
`Mar. 15, 2011)
`
`
`
`
`
`
`Exhibit
`2001
`
`
`
`vi
` 
`
`

`
`I.
`
`Introduction
`
`The Petition for inter partes review of U.S. Patent No. 7,818,490 (“the ’490
`
`patent”) should be denied and no trial instituted because there is no “reasonable
`
`likelihood that the petitioner would prevail with respect to at least one of the
`
`claims challenged in the petition.” 35 U.S.C. § 314(a).
`
`The Petition presents grounds for challenge against claims 66-72 and 94-106
`
`of the ‘490 patent based on anticipation and/or obviousness. But many of these
`
`grounds improperly rely on the doctrine of inherency without factual support for
`
`Petitioner’s allegations. Additionally, the Petitioner’s obviousness-based
`
`challenges not only fail to reach every feature of the challenged claims, they also
`
`lack sufficient rationale for why a person of ordinary skill in the art would have
`
`modified the prior art to disclose or suggest the challenged claims. And Petitioner’s
`
`expert testimony often fails to “disclose the underlying facts or data” on which it is
`
`based, in violation of 37 C.F.R. § 42.65(a), and instead simply repeats unsupported
`
`attorney argument and conclusions presented by Petitioner. As such, Petitioner
`
`does not meet its burden in establishing a reasonable likelihood of success.
`
`Further, the Petition is in violation of the Board’s governing requirements,
`
`including those set forth in 37 C.F.R. §§ 42.22(a)(2), 42.104(b)(4), and
`
`42.104(b)(5). Under these requirements, the Petition must include a detailed
`
` 
`
`1
`
`

`
`explanation of the significance and relevance of the evidence; and the Petition
`
`must specify where each element of the challenged claims is found in the prior art.
`
`II. Background
`
`A. About U.S. Patent No. 7,818,490 (the “‘490 patent”)
`
`The ‘490 patent is entitled “PARTIAL BLOCK DATA PROGRAMMING
`
`AND READING OPERATIONS IN A NON-VOLATILE MEMORY,” and it
`
`discloses techniques for updating data in less than all of the pages of a non-volatile
`
`memory block by programming new data in unused pages of either the same or
`
`another block. Ex. 1001 at Abstract. The ‘490 patent was filed as U.S. Patent
`
`Application No. 11/250,238 on October 13, 2005 and was issued on October 19,
`
`2010. The ‘490 patent claims priority to and the benefit of U.S. Patent Application
`
`No. 09/766,436, filed on January 19, 2001, now U.S. Patent No. 6,763,424.
`
`Flash memory devices comprise one or more arrays of transistor cells, each
`
`cell capable of non-volatile storage of one or more bits of data so that power is not
`
`required to retain the data programmed therein. Ex. 1001 at 1:29-32. Once a cell is
`
`programmed, it must be erased before it can be reprogrammed with new data. Id. at
`
`1:33-34. Typical flash memory arranges large groups of cells into erasable blocks,
`
`wherein a block contains the smallest number of cells that are erasable at one time.
`
`Id. at 1:36-40. Blocks are often partitioned into individually addressable pages that
`
`are the basic unit for programming user data. Id. at 1:51-55.
`
`2
` 
`
`

`
`Ideally, the data in all of the pages in a block are updated together by
`
`programming the updated data into the pages of an erased block. Ex. 1001 at 2:4-7.
`
`However, it is more typical that data in less than all of the pages in a block are
`
`updated while the data in the remaining pages of that block remain unchanged. Id.
`
`at 2:8-12. This typical update is sometimes referred to as a partial block update. Id.
`
`at 2:14-18.
`
`The ‘490 patent describes two prior art techniques for performing partial
`
`block updates. Ex. 1001 at 2:14-28. In the first prior art technique, data of the
`
`pages to be updated are written into a corresponding number of pages in an unused
`
`erased block. Id. at 2:14-20. The unchanged pages from the original block are then
`
`copied into pages of the new block (e.g., the previously unused erased block). Id.
`
`The original block may then be erased. Id. at 2:18-20. This first prior art technique
`
`has problems. Notably, copying unchanged pages from the original block to the
`
`new block greatly reduces the write performance and usable lifetime of the storage
`
`system. Id. at 5:67-6:5.
`
`In the second prior art technique described by the ‘490 patent, updated pages
`
`are also written to a new block, but the need to copy unchanged pages of the
`
`original block into the new block is eliminated. Ex. 1001 at 2:20-25. This need is
`
`eliminated through the use of flags associated with each page. Id. When updated
`
`data is written to a new block, the flags of pages in the original block which
`
`3
` 
`
`

`
`correspond to the updated data are updated to indicate that they now contain
`
`obsolete (invalid) data. Id. This second prior art technique suffers from limitations
`
`as well. To program obsolete flags in pages where the data has been superceded
`
`requires that a page support multiple programming cycles. Id. at 6:61-63. And in
`
`some cases, memory systems do not permit additional cycles. Id. at 7:4-7.
`
`Moreover, blocks in a system that uses obsolete flags must support the ability to
`
`program a page when other pages in the block with higher offsets or addresses
`
`have already been programmed. Id. at 6:66-7:1. However, a limitation of some
`
`flash memories prevents the usage of obsolete flags by specifying that the pages in
`
`a block can only be programmed in a physically sequential manner. Id. at 7:1-4.
`
`One additional problem with some systems that use obsolete flags is that
`
`allowing those flags to be written in pages whose data is being superceded can
`
`disturb data in other pages of the same block that remain current. Id. at 7:23-26.
`
`NAND type flash memory is particularly susceptible to such disturbs when being
`
`operated in a multi-state mode to store more than one bit of data in each cell. Id. at
`
`7:31-34.
`
`The ‘490 patent presents several solutions to the problems of the prior art. In
`
`these solutions, pages containing updated data are assigned the same logical
`
`address as the pages whose data has been superceded. Ex. 1001 at 7:55-58. Rather
`
`than using obsolete flags to tag the pages whose data has been superceded, the
`
`4
` 
`
`

`
`memory controller distinguishes the pages with updated data from those with
`
`superceded data by keeping track of the order in which the page having the same
`
`logical address were written. Id. at 7:58-67. The controller can do so, for example,
`
`using a counter or time stamp. Id. at 7:58-67, 8:34-55. Alternatively, when pages
`
`are written in order within blocks from the lowest to highest physical page address,
`
`the controller can identify the most recent copy of data by checking the physical
`
`addresses of the pages that contain the updated and superceded data. Id. at 7:58-67.
`
`In this case, the higher physical address contains the most recent copy of the data.
`
`Id.
`
`FIG. 8 of the ‘490 shows an exemplary implementation.
`
`
`
`5
` 
`
`

`
`In this example, new data 37 for each of pages 3-5 of block 35 is written into
`
`three pages (0-2) of a new block 39 that has been previously erased. Ex. 1001 at
`
`8:10-13, FIG. 8. Pages 3-5 from block 35 is thus now superceded by pages 0-2
`
`from new block 39. Pages 3-5 from block 35 also have the same logical address as
`
`pages 0-2 from new block 39. Id. at 8:13-16. In order for the memory controller to
`
`determine whether pages 3-5 from block 35 or pages 0-2 from new block 39
`
`contains the updated data, each page contains an overhead field 43 that provides an
`
`indication of its relative time of programming. Id. at 8:26-33. The memory
`
`controller can thus use the overhead field when called upon to read the data, and
`
`assemble data from the identified new pages in new block 39 along with original
`
`data that has not been updated from block 35. Id. at 8:56-63.
`
`The example of FIG. 8 also shows that the pages with the updated data are
`
`stored in the first three pages (0-2) of new block 39, rather than in the same pages
`
`(3-5) as in block 35. Id. at 8:64-67. In other words, the respective pages have
`
`different offset positions. This is made possible by keeping track of the individual
`
`logical page numbers. Id. at 8:67-9:3. Pages of updated data can also be written to
`
`erased pages of the same block as the page of data being superceded. Id. at 9:4-5.
`
`The ‘490 patent also discloses the use of metablocks to improve
`
`performance by reducing programming time. Ex. 1001 at 11:53-55. One
`
`implementation divides the memory array into largely independent sub-arrays or
`
`6
` 
`
`

`
`units. Id. at 11:55-59. Each unit is divided into a large number of blocks, where
`
`each block is the smallest erasable group of the memory array. Id. at 11:55-59,
`
`12:1-6. Fig. 16 depicts one embodiment of a metablock operation in the ‘490
`
`patent.
`
`
`
`In Fig. 16, blocks 85-88 in a plurality of sub-arrays (units) 80-83 comprise a
`
`metablock. Ex. 1001 at 11:55-59, 11:67-12:1, 12:6-11. A programming operation
`
`of the metablock may include simultaneously programming data into at least one
`
`page of each of the blocks 85-88. Id. at 12:6-11. Partial block updates of a
`
`metablock can be done for individual blocks of a metablock in the same manner
`
`described above with respect to Fig. 8. Id. at 12:13-18.
`
`In the embodiment of Fig. 16, in order to reduce the number of blocks
`
`required for partial block updates, updates to pages of data within this metablock
`
`are made to a single block 90 that is not part of the metablock but within one of the
`
`sub-arrays. Id. at 12:27-32.
`
`7
` 
`
`

`
`Other embodiments disclosed in the specification describe performing
`
`partial block updates by programming updated data to multiple blocks in different
`
`sub-arrays within a metablock. Id. at 3:17-25, 12:13-26. Fig 15 provides an
`
`exemplary depiction of this operation.
`
`
`
`B.
`
`Petitioner’s Grounds of Challenge
`
`The Petitioner challenges the validity of claims 66-72 and 94-106 of the
`
`‘490 patent. Notwithstanding the Petitioner’s insufficient allegations of inherency
`
`and unsupported combinations of references, the cited art fails to disclose many of
`
`the features recited in the claims. The asserted grounds identified in the Petition
`
`rely upon eight prior art references, including so-called Admitted Prior Art
`
`identified in the ‘490 patent. The Petitioner also relies upon the Declaration of Dr.
`
`Vivek Subramanian (“Subramanian Decl.”) (Ex. 1003).
`
`The asserted grounds of rejection are as follows:
`
`8
` 
`
`

`
`Ground Basis
`
`Reference
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`
`
`Anticipation under 35
`U.S.C. § 102(b) of
`Claims 94-97, 102, and
`104-105
`Obviousness under 35
`U.S.C. § 103(a) of
`Claims 98, 100, and 103
`Obviousness under 35
`U.S.C. § 103(a) of
`Claims 66, 68, and 70
`Obviousness under 35
`U.S.C. § 103(a) of Claim
`67
`Obviousness under 35
`U.S.C. § 103(a) of
`Claims 69, 99, and 101
`
`Obviousness under 35
`U.S.C. § 103(a) of
`Claims 71 and 106
`
`Obviousness under 35
`U.S.C. § 103(a) of Claim
`72
`
`Obviousness under 35
`U.S.C. § 103(a) of
`Claims 66-72 and 94-
`106
`
`U.S. Patent No. 5,822,781 to Wells (Ex.
`1005) (“Wells”)
`
`Wells + U.S. Patent No. 5,457,658 to Niijima
`(Ex. 1006) (“Niijima”)
`
`Wells + Knowledge of a Person of Ordinary
`Skill in the Art
`
`Wells + Knowledge of a Person of Ordinary
`Skill in the Art + Niijima
`
`Wells + Knowledge of a Person of Ordinary
`Skill in the Art + Admitted Prior Art + U.S.
`Patent No. 5,627,783 to Miyauchi (Ex. 1007)
`(“Miyauchi”)
`Wells + Knowledge of a Person of Ordinary
`Skill in the Art + Admitted Prior Art +
`“Flash Memories,” edited by Cappelletti et
`al. (Ex. 1008) (“Cappelletti”)
`Wells + Knowledge of a Person of Ordinary
`Skill in the Art + Admitted Prior Art + PC
`Card Standard, Volumes 1 and 3 (Ex. 1009)
`(“PC Card Standard”)
`Wells + Knowledge of a Person of Ordinary
`Skill in the Art + WO 99/35650 (Ex. 1010)
`(“Hazen”) + “Designing with Flash
`Memory,” Dipert et al. (Ex. 1011) (“Dipert”)
`
`9
` 
`
`

`
`Throughout this Preliminary Response, for ease of understanding, the Patent
`
`Owner will refer to these prior art references by the names indicated above.1 These
`
`prior art references are described below at Section IV, in conjunction with the
`
`arguments presented in this Preliminary Response.2
`
`III. Claim Construction
`
`The Petitioner seeks construction of a single term: “metablock.” Petition at
`
`13-16. The standard for construing claim terms in this proceeding is not in dispute.
`
`Since the ‘490 patent is not expired, the Board will interpret claims using the
`
`broadest reasonable interpretation as understood by one of ordinary skill in the art
`
`and consistent with the disclosure (“BRI”). See Office Patent Trial Practice Guide,
`
`77 Fed. Reg. 48756, 48766 (Aug. 14, 2012) (“Office Patent Trial Practice Guide”);
`
`37 C.F.R. § 42.100(b). Under the BRI analysis, claim terms are given their
`                                                            
`1 Patent Owner notes that Wells, Niijima, and Miyauchi were considered by the
`
`U.S. Patent Office (“PTO”) during the prosecution of the ‘490 patent. The PTO
`
`was right to allow the ‘490 patent over these references.
`
`2
`
` Patent Owner reserves its right to present further argument and evidence related
`
`to these prior art references and the content of the Petition and supporting Exhibits
`
`later in this proceeding, consistent with the Board’s Rules and practice. No waiver
`
`is intended by any argument withheld by Patent Owner at this stage of the
`
`proceeding.
`
`10
` 
`
`

`
`ordinary and customary meaning, as would be understood by one of ordinary skill
`
`in the art at the time of the invention. In re Translogic Tech., Inc., 504 F.3d 1249,
`
`1257 (Fed. Cir. 2007). The Petitioner’s proposed constructions are not consistent
`
`with the BRI and therefore should not be adopted.
`
`
`
`A.
`
`“metablock”
`
`Petitioner proposes that this term be construed to mean “set of blocks
`
`associated together such that during operation they are programmed, read, or
`
`erased together as a unit.” Petition at 15-16. But this construction is inconsistent
`
`with the BRI for that term. Instead, Patent Owner believes that this term should be
`
`construed to mean “two or more blocks positioned in separate units of one or more
`
`memory chips for programming and reading together in parallel as part of a single
`
`operation.” Patent Owner’s proposed construction adopts the inventor’s
`
`lexicography for a “metablock” as expressly stated in the Summary of the
`
`Invention:
`
`Another principal aspect of the present invention groups together two
`or more blocks positioned in separate units of the memory array
`(also termed “sub-arrays”) for programming and reading together
`as part of a single operation. Such a multiple block group is
`referenced herein as a “metablock.”
`Ex. 1001 at 3:5-9 (emphasis added). The Petitioner ignores this same
`
`lexicography. As defined by the inventor, a “metablock” is two or more blocks:
`
`11
` 
`
`

`
`(1) positioned in separate units of the memory array; and (2) grouped for
`
`programming and reading together as part of a single operation. Additionally, the
`
`goal of the metablock aspect of the ‘490 patent is described as “to program as
`
`many cells in parallel as can reasonably be done without incurring other
`
`penalties.” Id. at 11:53-55 (emphasis added). The ‘490 patent further explains that
`
`the metablock innovation could be implemented with the metablock units located
`
`on the same memory chip, or where the units forming the metablock are found on
`
`multiple memory chips. Id. at 11:55-64. Accordingly, the BRI for “at least first and
`
`second of the plurality of blocks logically linked together as a metablock” is “two
`
`or more blocks positioned in separate units of one or more memory chips for
`
`programming and reading together in parallel as part of a single operation.” 3
`
`IV. The Petitioner Does Not Demonstrate That It Is More Likely Than Not
`to Prevail On Any Challenged Claim on the ‘490 Patent
`
` 
`
`The institution of an inter partes review requires Petitioner to establish that
`
`there is a “reasonable likelihood that the petitioner would prevail with respect to at
`
`least one of the claims challenged in the petition.” 35 U.S.C. § 314(a). None of
`
`                                                            
`3
` Patent Owner, like Petitioner, notes that the standards of construction applied in
`
`this proceeding are different from the standards applied in the related litigation.
`
`Patent Owner also reserves the right to present evidence to the Board regarding
`
`claim construction in its Response, should one be necessary. 
`
`12
` 
`
`

`
`Petitioner’s challenges meet this threshold, and the Board should deny the Petition
`
`and deny institution of the inter partes review.
`
`A.
`
`Petitioner Fails to Demonstrate That Wells Anticipates Claims 94-
`97, 102, and 104-105 (Ground 1)
`
`A finding of invalidity under 35 U.S.C. § 102 requires a showing that a
`
` 
`
`single reference teaches every limitation of the claim. “A claim is anticipated only
`
`if each and every element as set forth in the claim is found, either expressly or
`
`inherently described, in a single prior art reference.” M.P.E.P. § 2131, quoting
`
`Verdegaal Bros. v. Union Oil Co. of California, 814 F.2d 628, 631 (Fed. Cir.
`
`1987). Furthermore, an anticipatory reference must not only “disclose all elements
`
`of the claim within the four corners of the document,” it must disclose those
`
`elements “arranged as in the claim.” Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d
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`1359, 1369 (Fed. Cir. 2008). The Petitioner in this case fails to establish that any
`
`claim of the ‘490 patent is anticipated by Wells because it fails to show that Wells
`
`discloses all the limitations of any challenged claim.
`
`
`1.
`
`The Petitioner Fails To Demonstrate That Wells Discloses
`“a plurality of sub-arrays of memory storage elements in
`which programming operations may be performed
`independently,” As Recited In Independent Claim 94.
`
`Claim 94 requires a non-volatile semiconductor memory system that has “a
`
`plurality of sub-arrays of memory storage elements in which programming
`
`operations may be performed independently, the sub-arrays individually being
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`divided into a plurality of blocks of memory storage elements that are erasable
`
`together as a unit.” The Petitioner attempts to rely on certain parts of Wells to
`
`teach this feature. Petition at 19. But that attempt fails.
`
`The Petitioner points to chip 68 and chip 70 in Fig. 2 of Wells as
`
`corresponding to the claimed “sub-arrays.” Petition at 18-19. Each chip, according
`
`to the Petitioner, contains 16 blocks. Id. at 18. The Petitioner’s position, however,
`
`is incorrect.
`
`Fig. 2 of Wells depicts two memory chips (68, 70) that act in concert as a
`
`chip pair 66 to permit word-wide operations. Ex. 1005 at 4:41-57. In other words,
`
`programming operations of the two chips are only described as being performed
`
`together, not performed independently, as required by claim 94. Chip 68 stores the
`
`high byte of a word. Id. at 4:51-53. And chip 70 stores the low byte of a word. Id.
`
`Each chip pair is organized as 16 blocks, with each block having 128 Kbytes of
`
`memory. Id. at 4:58-59. Accordingly, the Petitioner is incorrect that each chip has
`
`16 blocks. Rather each chip pair has 16 blocks. If it were true that each chip has 16
`
`blocks, then each chip pair would have been described as having 32 blocks, not 16.
`
`Further proof of this organization is Wells’ separate disclosure that a block has 128
`
`Kbytes, which matches the size of a block that spans a chip pair. Id. at 4:23-25, 58-
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`59. Moreover, Wells discloses that the smallest erasable group of memory storage
`
`elements is the same 128 Kbyte block. Id. at 4:14-17, 23-25.
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`Accordingly, contrary to the Petitioner’s position, a single chip in Fig. 2
`
`cannot be a claimed sub-array, because the programming operations of a chip are
`
`only described as being performed together with another chip, not as being
`
`programmable independently.
`
`For the foregoing reasons, the Petitioner’s challenge of claim 94 should be
`
`denied.
`
`
`2.
`
`The Petitioner Fails To Demonstrate That Wells Discloses
`“linking together blocks within the plurality of sub-arrays
`to form a plurality of metablocks…” As Recited In
`Independent Claim 94
`
`Claim 94 also requires “linking together blocks within the plurality of sub-
`
`arrays to form a plurality of metablocks whose memory storage elements are
`
`erasable together and whose pages of memory storage elements within the linked
`
`blocks are programmable together in parallel.” The Petitioner again turns to Fig. 2,
`
`arguing that “[t]he Block Pair shown in Figure 2, excerpted above, is a logical unit
`
`comprising two blocks from different chips that are logically linked together as a
`
`metablock and are positioned in different sub-arrays. Figure 2 shows two
`
`exemplary sub-arrays (High Chip 68 and Low Chip 70).” Petition at 20. However,
`
`as explained above in Section IV.A.1., the individual chips in Fig. 2 do not
`
`correspond to the claimed sub-arrays. Therefore, linking so-called blocks from
`
`these individual chips does not equate to “linking together blocks within the
`
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`plurality of sub-arrays to form a plurality of metablocks.” If Wells were going to
`
`show this feature, it would need to show a block from the chip pair shown in Fig. 2
`
`being linked to a block from another chip pair. But Fig. 2 only shows one chip pair.
`
`Accordingly, the Petitioner’s challenge to claim 94 must fail.
`
`
`3.
`
`The Petitioner Fails To Demonstrate That Wells Discloses
`“programming the one or more pages of updated data of
`the file into individual ones of the erased second plurality of
`pages in only the second block,” As Recited By Claim 96
`
`Claim 96 recites “programming the one or more pages of updated data of the
`
`file into individual ones of the erased second plurality of pages in only the second
`
`block.” The Petitioner fails to establish that Wells teaches this feature. The entirety
`
`of the Petitioner’s analysis for this claim is two sentences:
`
`This claim is satisfied at least in the situation where a sector of data is
`updated (i.e., one page of updated data). That sector will be written
`into a page in the second block. (Ex. 1003 at ¶¶ 53-54).
`Petition at 28. First, the Petitioner fails to point to anywhere in Wells that purports
`
`to teach the limitations of claim 96. The only “evidence” pointed to by the
`
`Petitioner is paragraphs 53 and 54 of the Subramanian Declaration. Id. But those
`
`paragraphs are a word-for-word copy of the Petitioner’s argument, which in turn is
`
`not supported with evidence by the Petitioner. Ex. 1003 at ¶¶ 53-54. Under the
`
`Board’s rules, a petitioner may present expert testimony in support of its petition,
`
`but that testimony must “disclose the underlying facts or data” on which it is based.
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`37 C.F.R. § 42.65(a). Otherwise, the expert testimony “is entitled to little or no
`
`weight.” Id.; see also Office Patent Trial Practice Guide at 48,763 (“The Board
`
`expects that most petitions . . . will rely upon affidavits of experts,” but
`
`“[a]ffidavits expressing an opinion of an expert must disclose the underlying facts
`
`or data upon which the opinion is based” (citing § 42.65 and Fed. R. Evid. 705).
`
`See also Corning Incorporated v. DSM IP Assets B.V., IPR 2013-00048, paper 94
`
`at 33 (PTAB 5/9/2014) (Final Written Decision by APJ Kamholz, for a panel
`
`consisting of APJs McKelvey, Obermann, Bisk, Kamholz, and Yang) (concluding
`
`that an expert’s verbatim repeating of attorney argument warrants “little weight in
`
`the absence of objective, evidenti