IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re patent of Conley:
`
`Petition for Inter Partes Review
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`U.S. Patent No. 7,818,490
`
`Issued: October 19, 2010
`
`Title: PARTIAL BLOCK DATA
`PROGRAMMING AND
`READING OPERATIONS IN A
`NON-VOLATILE MEMORY
`
`Attorney Docket No.:
`337722-000080.490
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`Customer No.: 26379
`
`Petitioner: Apple Inc.
`
`Real Party in Interest: Apple Inc.
`
`
`
`PETITION FOR INTER PARTES REVIEW OF
`
`U.S. PATENT NO. 7,818,490
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Dear Sir:
`
`Pursuant to the provisions of 35 U.S.C. §§ 311-319, Apple Inc.
`
`(“Petitioner”) hereby petitions the Patent Trial and Appeal Board to institute an
`
`inter partes review of claims 66-72 and 94-106 of United States Patent
`
`No. 7,818,490 (the “’490 patent”) (Exh. 1001).
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`TABLE OF CONTENTS
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`Page
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`I.
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`G.
`
`H.
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`MANDATORY NOTICES ............................................................................ 1
`A.
`Real Party-in-Interest ........................................................................... 1
`B.
`Related Matters ..................................................................................... 1
`C.
`Lead and Back-up Counsel .................................................................. 2
`D.
`Service Information .............................................................................. 3
`GROUNDS FOR STANDING ....................................................................... 3
`II.
`III. RELIEF REQUESTED .................................................................................. 3
`IV. THE REASONS FOR THE REQUESTED RELIEF ..................................... 3
`A.
`Summary of Reasons ............................................................................ 3
`B.
`Relevant Technology Background ....................................................... 5
`C.
`Overview of the ’490 Patent ................................................................. 8
`D.
`Level of Ordinary Skill in the Art ...................................................... 14
`E.
`Claim Construction............................................................................. 14
`F.
`Challenge #1: Claims 94-97, 102, and 104-105 are Anticipated
`by Wells. ............................................................................................. 17
`Challenge #2: Claims 98, 100, and 103 are Rendered Obvious
`by Wells and Niijima. ......................................................................... 33
`Challenge #3: Claims 66, 68, and 70 Are Rendered Obvious by
`Wells and the Knowledge of One of Ordinary Skill in the Art. ........ 34
`Challenge #4 (Relative Order of Programming): Claim 67 Is
`Rendered Obvious by Wells, the Knowledge of One of
`Ordinary Skill in the Art, and Niijima. .............................................. 37
`Challenge #5 (Logical Block Number and Page Offset Claims):
`Claims 69, 99, and 101 are Rendered Obvious by Wells, the
`Knowledge of One of Ordinary Skill in the Art, and the
`Admitted Prior Art or Miyauchi. ........................................................ 39
`Challenge #6 (Multi-Bit Claims): Claims 71 and 106 are
`Rendered Obvious by Wells, the Knowledge of One of
`Ordinary Skill in the Art, and the Admitted Prior Art or
`Cappelletti. ......................................................................................... 42
`
`I.
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`J.
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`K.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`L.
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`Challenge #7 (Enclosure Card): Claim 72 is Rendered Obvious
`by Wells, , the Knowledge of One of Ordinary Skill in the Art,
`and the Admitted Prior Art or the PC Card Standard. ....................... 44
`M. Challenge #8 (Metablock): If the Board Rejects Any of
`Challenges #1-7 Based on the “Metablock” Element, Then
`Such Claims Are Rendered Obvious by Wells and the
`Knowledge of One of Ordinary Skill in the Art, Hazen, or
`Dipert .................................................................................................. 47
`CONCLUSION ............................................................................................. 48
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`
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`V.
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`Exhibit Number Description
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`1001
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`1002
`
`1003
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`1004
`
`1005
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`1006
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`1007
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`1008
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`U.S. Patent 7,818,490
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`File History for U.S. Patent 7,818,490
`
`Declaration of Dr. Vivek Subramanian
`
`(“Subramanian Decl.”)
`
`CV of Dr. Vivek Subramanian
`
`U.S. Patent 5,822,781 (“Wells”)
`
`U.S. Patent No. 5,457,658 (Niijima)
`
`U.S. Patent No. 5,627,783 (“Miyauchi”)
`
`Flash Memories, edited by Cappelletti, et al (1999)
`
`(“Cappelletti”)
`
`1009
`
`PC Card Standard, Volumes 1 and 3 (1999) (“PC
`
`1010
`
`1011
`
`
`
`
`
`
`
`Card Standard”)
`
`PCT WO 99/35650 (“Hazen”)
`
`Designing With Flash Memory, Brian Dipert and
`
`Markus Levy (1994) (“Dipert”)
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`
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`iii
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`U.S. Patent No. 7,818,490
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`I. Mandatory Notices
`
`A. Real Party-in-Interest
`
`Pursuant to 37 C.F.R. § 42.8(b)(1), the real party-in-interest is Apple Inc.
`
`B. Related Matters
`
`Pursuant to 37 C.F.R. § 42.8(b)(2), Petitioner states that Longitude Flash
`
`Memory Systems S.A.R.L. (“Patent Owner”) is asserting U.S. Patent 7,818,490
`
`(the “’490 patent”) against the Real Party-In-Interest in a suit filed September 23,
`
`2014, styled Longitude Licensing Ltd., and Longitude Flash Memory Systems
`
`S.A.R.L. v. Apple Inc., Case No. 3:14-cv-4275, pending in the United States
`
`District Court for the Northern District of California (the “Litigation”). Petitioner
`
`has filed, or soon will file, petitions for inter partes review of U.S. Patent Nos.
`
`6,510,488; 6,763,424 (the “’424 patent”); 6,831,865; 6,968,421; 7,012,835;
`
`7,120,729; 7,224,607; 7,181,611; 7,657,702 (the “’702 patent”); 7,970,987;
`
`8,050,095; and 8,316,177. Petitioner also is concurrently filing two other petitions
`
`for the ’490 patent for claims other than the ones at issue in this petition.
`
`The ’424 patent, which is the grandparent of the ’490 patent, was the subject
`
`of previous litigation and the following opinions in which claim terms found in
`
`both patents were construed: (1) SanDisk Corp. v. Kingston Tech. Co., 695 F.3d
`
`1348 (Fed. Cir. 2012); (2) In the Matter of Certain Flash Memory Controllers,
`
`United States Int’l Commission, Inv. No. 337-TA-619, Order No. 33, July 15, 2008
`1
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`(Bullock, ALJ); and (3) In the Matter of Certain Flash Memory Controllers,
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`United States Int’l Commission, Inv. No. 337-TA-619, Commission Opinion,
`
`November 24, 2009. The ’702 patent, which is related to the ’490 patent, was the
`
`subject of previous litigation and the following opinion in which claim terms were
`
`construed: SanDisk Corp. v. Kingston Tech. Co., Inc., United States District Court
`
`for the Western District of Wisconsin, Case No. 10-cv-243-bbc, March 16, 2011
`
`(Crabb, J.).
`
`As of the filing of this petition, no other judicial or administrative matters
`
`are known to Petitioner that would affect, or be affected by, a decision in an inter
`
`partes review of the ’490 patent.
`
`C. Lead and Back-up Counsel
`
`Lead counsel for this matter is Brent Yamashita (USPTO Reg. No. 53808),
`
`and back-up counsel for this matter is Edward Sikorski (USPTO Reg. No. 39478)
`
`and Kevin Hamilton (USPTO Reg. No. 67,593), all at the e-mail address: Apple-
`
`Longitude-IPR@dlapiper.com. The postal and hand delivery address for all is
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`DLA Piper LLP (US), 2000 University Avenue, East Palo Alto, California, 94303,
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`and the telephone and fax numbers are (650) 833-2348 (for phone) and (650) 687-
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`2
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`1206 (for fax).
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`U.S. Patent No. 7,818,490
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`D.
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`Service Information
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`Pursuant to 37 C.F.R. § 42.8(b)(4), papers concerning this matter should be
`
`served on the following email address: Apple-Longitude-IPR@dlapiper.com.
`
`II. Grounds for Standing
`
`Pursuant to 37 CFR § 42.104(a), Petitioner certifies that the ’490 Patent is
`
`available for inter partes review, and Petitioner is not estopped or barred from
`
`requesting inter partes review challenging the ’490 Patent on the grounds
`
`identified in this petition.
`
`III. Relief Requested
`
`Petitioner asks that the Board review the accompanying prior art and
`
`analysis, institute a trial for inter partes review of claims 66-72 and 94-106 of the
`
`’490 patent, and cancel claims those claims as invalid for the reasons set forth
`
`below.
`
`IV. The Reasons for the Requested Relief
`
`The full statement of the reasons for relief requested is as follows:
`
`A.
`
`Summary of Reasons
`
`Challenge #1: Claims 94-97, 102, and 104-105 are Anticipated
`
`by Wells.
`
`Challenge #2 (Logical Address in Page): Claims 98, 100, and
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`103 are Rendered Obvious by Wells and Niijima.
`3
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`U.S. Patent No. 7,818,490
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`Challenge #3 (Designated Block): Claims 66, 68, and 70 Are
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`Rendered Obvious by Wells and the Knowledge of One of
`
`Ordinary Skill in the Art.
`
`Challenge #4 (Relative Order of Programming): Claim 67 Is
`
`Rendered Obvious by Wells, the Knowledge of One of
`
`Ordinary Skill in the Art, and Niijima.
`
`Challenge #5 (Logical Block Number and Page Offset):
`
`Claims 69, 99, and 101 are Rendered Obvious by Wells, the
`
`Knowledge of One of Ordinary Skill in the Art, and the
`
`Admitted Prior Art or Miyauchi (Ex. 1007).
`
`Challenge #6 (Multi-Bit): Claims 71 and 106 are Rendered
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`Obvious by Wells, the Knowledge of One of Ordinary Skill in
`
`the Art, and the Admitted Prior Art or Cappelletti.
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`Challenge #7 (Enclosure Card): Claim 72 is Rendered
`
`Obvious by Wells, the Knowledge of One of Ordinary Skill in
`
`the Art, and the Admitted Prior Art or the PC Card Standard.
`
`Challenge #8 (Metablock): If the Board Rejects Any of
`
`Challenges #1-7 Based on the “Metablock” Element, Then
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`Such Claims Are Rendered Obvious by Wells and the
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`Knowledge of One of Ordinary Skill in the Art, Hazen, or
`
`Dipert.
`
`B. Relevant Technology Background
`
`1. Overview of Flash Memory
`
`A flash memory device contains one or more arrays of non-volatile memory
`
`cells. (Ex. 1001 at 1:29-40). Non-volatile memory cells retain their data when
`
`power is removed. (Id.) However, unlike most types of non-volatile memory cells
`
`(such as ROM and EPROM cells), flash memory cells are reprogrammable. (Id.).
`
`The typical flash memory architecture used to achieve non-volatility and
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`reprogrammability has several functional limitations. For example, once a flash
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`memory cell is programmed with data, the cell must be erased before that cell can
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`be reprogrammed with new data. (Id.). Further, if it were desired to erase the cells
`
`used in flash memory on a cell-by-cell basis, extensive circuitry would be required
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`to erase such flash memory cells individually. (Ex. 1001 at 1:41-58). Therefore,
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`instead of erasing individual cells, the typical flash memory has large groups of
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`cells arranged into erasable blocks, a block containing the smallest number of cells
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`that can be erased at one time. (Id.). It is desirable to read or write data in units
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`smaller than the size of a block. (Ex. 1001 at 1:51-58). Therefore, blocks are
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`further partitioned into pages, a page containing the smallest number of cells that
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`can be read or written at one time. (Id.). Also, in some flash memories, the pages
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`within each block can only be programmed in a physically sequential manner. (Ex.
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`1001 at 7:1-4; Ex. 1003 at ¶ 13).
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`In addition to user data, each page in a flash memory can contain a set of
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`overhead data fields and flags to store information related to the user data. (Ex.
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`1001 at 1:41-58, 5:53-55). For example, each time user data is written to a page, a
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`logical block number (“LBN”) indicating the data’s logical address can be
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`recorded in a data field within the page. (Ex. 1001 at 5:49-57, 6:6-25, and 6:44-57;
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`Ex. 1003 at ¶ 14).
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`
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`(Ex. 1001 at Figure 6; Ex. 1003 at ¶ 14).
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`The block and page architecture of the typical flash memory presents several
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`challenges when updating user data. In the ideal case, the data in all pages of a
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`block are modified together and written to the pages of an erased block. (Ex. 1001
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`at 2:4-8). However, a partial block update is more common, in which the data in
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`only some pages within a block are updated, while the data in the remaining pages
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`is unchanged. (Ex. 1001 at 2:8-12). At least two techniques to perform a partial
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`block update in a flash memory device were well known when the ’490 patent was
`
`filed and are acknowledged as prior art by the ’490 patent itself. (Ex. 1001 at 2:14-
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`28). The first technique involves writing the updated data into a new, erased block.
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`(Id.) The system then copies the unchanged data from the old block into the new
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`block. (Id.). Finally, the system erases the old block. (Id.). This technique is
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`inefficient because it requires copying unchanged pages of data to a different
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`block. (Id.; Ex. 1003 at ¶ 15).
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`The second known partial block update technique also involves writing the
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`data of the updated pages to a corresponding number of pages in a new block. (Ex.
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`1001 at 2:21-28). However, instead of copying the unchanged pages of data to the
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`new block, the flags of the pages in the original block which are being updated are
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`modified to indicate that those pages contain superseded data. (Id.). When reading
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`the data, the updated data from pages of the new block are combined with the
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`unchanged data from the pages of the original block that are not flagged as
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`superseded. (Id.). While the second technique avoids copying the unchanged data
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`to the new block, it still requires updating a flag in each superceded page. (Id.; Ex.
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`7
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`1003 at ¶ 16).
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`C. Overview of the ’490 Patent
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`The ’490 patent relates to management and organization of a flash memory
`
`system. It recognizes that typical flash systems can write data to individual pages
`
`but can only erase entire blocks and not individual pages. In the Admitted Prior
`
`Art discussed in the ’490 patent, if the host wrote data to Logical Addresses (LA)
`
`1, 2, 3, and 4, the data might be stored in pages as follows:
`
`
`
`(Ex. 1001 at 5:45-48; Ex. 1003 at ¶ 17).
`
`At a later time, if the host wished to update one of the pages, such as LA4,
`
`but not all of the pages, the Admitted Prior Art system discussed in the ’490 would
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`write the updated page in a new block, copy the unchanged data from the old block
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`to the new block, and then erase the old block, as shown below:
`
`
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`(Ex. 1001 at Figure 4; 5:45-67; Ex. 1003 at ¶ 18).
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`This was inefficient and time-consuming. The ’490 patent recognizes the
`
`limitations of the Admitted Prior Art and offers a solution whereby the old block is
`
`maintained and the updated page is written to a new block. This means that the old
`
`page and updated page both will be associated with the same logical address (e.g.,
`
`LA4). The ’490 patent discloses a few different ways to keep track of which page
`
`is the most recent page. For example, the system can include a timestamp with
`
`each page or keep track of the relative order in which each page was written. The
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`’490 patent solution is illustrated below:
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`(Ex. 1001 at Figure 8; 8:64-9:5; Ex. 1003 at ¶ 19).
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`The ’490 patent provides an additional improvement. It creates a
`
`“metablock” by selecting one block from each sub-array and treating them as a
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`unit. For example, the system could perform an erase on the entire metablock at
`
`one time. This is an organizational technique shown below:
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`(Ex. 1001 at Figure 15; 11:53-22:12; Ex. 1003 at ¶ 20).
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`
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`The ’490 patent discloses that when pages are updated within a metablock,
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`the updated pages can be written to a new block in the same sub-array, as shown
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`below:
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`(Ex. 1001 at Figure 15, 12:6-12; Ex. 1003 at ¶ 21).
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`The ’490 patent also discloses an embodiment where updates to any page in
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`the metablock are written to the same update block in one of the sub-arrays, as
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`
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`shown below:
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`(Ex. 1001 at Figure 16, 12:27-47; Ex. 1003 at ¶ 22).
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`As will discussed below, all of these alleged improvements of the ’490
`
`patent are found in the prior art. (Ex. 1003 at ¶ 23).
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`D. Level of Ordinary Skill in the Art
`
`A person of ordinary skill in the relevant art at the time of the ’490 patent
`
`would have had a Master’s Degree or equivalent in electrical engineering or a
`
`related field and two years of experience in memory technology or the equivalent.
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`(Ex. 1003 at ¶ 24).
`
`E. Claim Construction
`
`Pursuant to 37 C.F.R. § 42.100(b) and 42.204(b)(3), the proposed claim
`
`constructions contained below are presented using the broadest reasonable
`
`interpretation standard, which is applied solely for the purposes of inter partes
`
`review.1 In the sections that follow, Petitioner presents its proposed constructions
`
`and also discloses the constructions that Longitude is advocating in the Litigation.
`
`
`1 Because the standards of claim interpretation used by the Courts in patent
`litigation are different from the claim interpretation standards used by the Office in
`inter partes review proceedings, Petitioner reserves the right to advocate a different
`claim interpretation in any other forum in accordance with the claim construction
`standards applied in such forum.
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`1.
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`“metablock”
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`Claim Term
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`Petitioner’s Construction
`
`Patent Owner’s Apparent
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`Construction
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`“metablock”
`
`set of blocks associated
`together such that during
`operation they are
`programmed, read, or erased
`together as a unit
`
`two or more blocks positioned in
`separate units of one or more
`memory chips for programming
`and reading together in parallel as
`part of a single operation
`
`
`Petitioner’s construction is consistent with the claims and specification,
`
`
`
`which refer to the metablock as a set of blocks that are grouped together for an
`
`operation, such as a program, read, or erase operation. It is not necessary that the
`
`blocks of a metablock be programmed together and read together as argued by
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`Patent Owner.2 (Ex. 1003 at ¶¶ 26-27).
`
`For example, the Abstract describes metablocks and does not suggest that
`
`programming and reading must happen to each block concurrently: “This
`
`technique is also applied to metablocks that include one block from each of several
`
`different units of a memory array, by directing all page updates to a single unused
`
`
`2 The parties have not construed the term “metablock” in the Related Litigation,
`but they have construed the larger phrase “at least first and second of the plurality
`of blocks logically linked together as a metablock,” and Petitioner is providing the
`apparent construction that Patent Owner gives to the term “metablock” based on its
`construction of the larger phrase.
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`block in one of the units.” (Ex. 1001 at Abstract). The metablock is simply an
`
`organizational unit. (Ex. 1003 at ¶ 28).
`
`The claims also support Petitioner’s view. For example, claim 66 indicates
`
`that the blocks of the metablock are erased together, but does not indicate that the
`
`blocks of the metablock are read together or programmed together. (Ex. 1001 at
`
`claim 66). Similarly, claim 94 indicates that the blocks of the metablock are
`
`programmed together and erased together (“…memory storage elements are
`
`erasable together and whose pages…are programmable together in parallel…”) but
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`does not indicate that the read operation must occur from both blocks together:
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`“reading data of the file from the first and second plurality of pages.” (Ex. 1001 at
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`claim 94). These claims indicate that a metablock does not need to support parallel
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`erase operations, parallel programming operations, and parallel erase operations.
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`Only one of those is required (Ex. 1003 at ¶ 29).
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`Moreover, Petitioner’s construction is broader than Patent Owner’s
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`construction and is a reasonable construction and therefore is more suitable as the
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`broadest reasonable construction. (Ex. 1003 at ¶ 30).
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`U.S. Patent No. 7,818,490
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`F. Challenge #1: Claims 94-97, 102, and 104-105 are Anticipated by
`Wells.
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`1. Overview of Wells
`
`Wells was filed on October 30, 1992, and issued on October 13, 1998. (Ex.
`
`1005 at cover page). The earliest potential priority date for the ’490 patent is
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`January 19, 2001. (Ex. 1001 at cover page) Wells therefore constitutes prior art
`
`against the ’490 patent under 35 U.S.C. Section 102(a), (b), and (e). Wells is
`
`contained within the file history of the ’490 along with over 110 other prior art
`
`references and hundreds of pages of filings from an ITC proceeding involving a
`
`grandparent of the ’490 patent. (Ex. 1005 at pages 1-2). Wells was not discussed
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`by the Examiner or Applicant during prosecution of the ’490 patent. (Ex. 1002).
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`Wells discloses all of the alleged points of novelty of the ’490 patent. Wells
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`discloses the use of numerous flash memory chips, with each chip divided into
`
`blocks and each block divided into sectors. (Ex. 1005 at Figures 2-3; 4:40-62).
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`Wells organizes the chips into pairs and provides an example involving 30
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`different flash chips divided into pairs, with an exemplary chip pair (item 66)
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`shown in Figure 2:
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`(Ex. 1005 at Figure 2; 4:41-62). Each chip contains 16 blocks, and each block
`
`contains multiple sectors. (Ex. 1005 at Figure 2). Blocks from each chip pair are
`
`grouped together as a unit. For example, in Figure 2, Block 0 from chip 68 and
`
`Block 0 from chip 70 are treated together as block 80. (Ex. 1005 at Figure 2; 4:57-
`
`67). For convenience, this Petition will refer to this logical grouping of blocks
`
`from a chip pair, such as block 80, as a “Block Pair.” The Block Pair is a
`
`metablock under the claims of the ’490 patent. Each Block Pair can be erased as a
`
`unit, and each block in the Block Pair can be programmed concurrently.
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`Moreover, when data in a sector within a block is updated, the updated data is
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`written to a new sector associated with the same logical address as the old sector.
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`(Ex. 1005 at 4:21-53; 14:66-15:13; 32:63-65) (Ex. 1003 at ¶ 31-32).
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`2. Wells anticipates claim 94
`
`a.
`
`Preamble: In a re-programmable non-volatile
`semiconductor memory system having a plurality of
`sub-arrays of memory storage elements in which
`programming operations may be performed
`independently, the sub-arrays individually being
`divided into a plurality of blocks of memory storage
`elements that are erasable together as a unit, the
`plurality of blocks individually being divided into a
`plurality of pages of memory storage elements that
`are programmable together, a method of operating
`the memory system, comprising:
`
`
`
`To the extent this preamble is limiting, Wells discloses the preamble. Wells
`
`discloses a plurality of sub-arrays of memory storage elements in which
`
`programming operations may be performed independently Each memory storage
`
`element is a re-programmable non-volatile semiconductor devices.” (Exhibit 1005
`
`at Abstract, Figures 1-2). For example, Wells provides an example of a system
`
`with 30 flash memory chips, with each chip comprising a sub-array. (Ex. 1005 at
`
`4:40-51). The charge storage elements within individual sub-arrays are
`
`programmable independently in units called “sectors,” where each block comprises
`
`16 sectors. (Figure 2; 4:58-62). The “sector” in Wells is the same as the “page” in
`
`the ’490 patent. Figure 2 also discloses a logical block (such as block 80), which
`
`comprises a block from two sub-arrays. (Figure 2). The logical block is erasable
`
`as a unit. (Ex. 1005 at 32:63-65) (Ex. 1003 at ¶¶ 33-34).
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`b.
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`linking together blocks within the plurality of sub-
`arrays to form a plurality of metablocks whose
`memory storage elements are erasable together and
`whose pages of memory storage elements within the
`linked blocks are programmable together in parallel,
`
`Wells discloses this element. The Block Pair shown in Figure 2, excerpted
`
`above, is a logical unit comprising two blocks from different chips that are
`
`logically linked together as a metablock and are positioned in different sub-arrays.
`
`Figure 2 shows two exemplary sub-arrays (High Chip 68 and Low Chip 70). Each
`
`of the plurality of blocks is divided into a plurality of pages of flash cells—which
`
`Wells calls a “sector”—that are programmable together. (Ex. 1005 at 4:51-53;
`
`32:63-65). For example, Wells states: “Solid state disk controller 64 is thus able
`
`to treat each chip pair as a single 16 bit-wide memory device. Word-wide input
`
`and output gives solid state disk 60 a speed advantage compared to magnetic
`
`drives, which use serial bit stream I/O.” (Ex. 1005 at 4:53-57). This disclosure
`
`indicates to one of ordinary skill in the art that each Block Pair will be
`
`programmed together, read together, and erased together, as if it were a block in a
`
`single device. (Ex. 1003 at ¶¶ 35-36).
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`c.
`
`programming pages of original data of a file into
`individual ones of an erased first plurality of pages in
`a first plurality of blocks forming a first metablock,
`the pages of original data having logical addresses
`associated therewith,
`
`Wells discloses this element. It discloses writing data corresponding to a
`
`sector number (which is a logical address) to a chip pair, block number, and header
`
`pointer to identify the specific sector. (Figures 3-4; 5:1-12). For example, Wells
`
`states:
`
`The data structure of block 80 includes block sector
`
`translation table 84 and data space 86. Block sector
`
`translation table 84 stores headers. A header is a block of
`
`information about one logical sector number and its
`
`associated data. As used herein a logical sector number
`
`(LSN) refers to a sector number stored within a BSTT. A
`
`sector number is a sector identifier received from CPU
`
`52, which the CPU believes corresponds to a fixed
`
`physical location. However, as a result of the write policy
`
`used by solid state disk 60, an LSN does not correspond
`
`to a fixed physical location. Also as a result of the write
`
`policy used, several headers and LSNs may correspond to
`
`a single sector number.
`
`(Ex. 1005 at 5:1-14) (Ex. 1003 at ¶¶ 37-38).
`
`
`
`Wells discloses the use of files comprising pages of data with associate
`
`logical addresses. For example, Wells states: “A typical user file stored on a
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`magnetic disk drive occupies many sectors, randomly located on the surface of the
`
`disk drive. A file allocation table (FAT) allows location of each sector of the file
`
`by storing a chain of pointers for the file. Each pointer points to the next sector of
`
`the file.” (Ex. 1005 at 1:22-26). Wells further states: “The next time the same
`
`process attempts to write a sector, the allocation algorithm first examines the last
`
`block allocated to that process. This helps keep related data "files" in contiguous
`
`memory space and helps reduce the possibility of data fragmentation.” (Ex. 1005 at
`
`17:21-26; Ex. 1003 at ¶ 39).
`
`d.
`
`thereafter programming one or more pages of
`updated data of the file into individual ones of an
`erased second plurality of pages in at least a second
`block, the pages of updated data having logical
`addresses associated therewith, wherein the logical
`addresses associated with the pages of updated data
`programmed into the second plurality of pages are
`common with those associated with the pages of
`original data programmed into the first plurality of
`pages,
`
`Wells discloses this element. When the data in part of a block is updated,
`
`the system writes the updated version of the data into a new location. Wells states:
`
`
`
`In step 246, microprocessor 92 determines
`
`whether a previous header with the same LSN should
`be marked dirty. Microprocessor 92 makes this
`
`determination based upon the information retrieved by
`
`the seek of step 238. If a header was located,
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`microprocessor 92 proceeds to step 247 to mark that
`
`header dirty. Afterward, microprocessor 92 advances to
`
`step 248 to determine whether the previous header was
`
`marked dirty or whether the task was cached. If the task
`
`was not cached, microprocessor 92 advances to 250.
`
`Otherwise, microprocessor 92 branches to step 249.
`
`Because the mark dirty task was cached, there will be
`
`two headers with the same LSN at the end of the current
`
`write. To distinguish the valid data after power-loss, the
`
`revision number for the LSN associated with the most
`
`current version is incremented in step 249.
`
`Microprocessor 92 then proceeds to step 250.
`
`
`
`With step 250, microprocessor 92 begins the
`
`process of writing the new version of the sector data
`
`within FLASH array 62. Microprocessor 92 allocates
`
`sufficient free memory within FLASH array 62 to store
`
`the sector of data and header. This is an involved process
`
`that will be described in detail later. Suffice it to say that
`
`allocation of memory requires locating sufficient
`
`memory within data space 86 of a block and marking that
`
`memory space as reserved. Microprocessor 92 then exits
`
`to step 252.
`
`Microprocessor 92 completes the writing of the
`
`header in steps 252 and 254. First, in step 252, a CRC is
`
`generated for the header, which excludes the dirty bits
`
`and revision numbers because they may be changed in
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`the course of events. Afterward, in step 254, the CRC,
`
`attribute word and LSN are written into BSTT 84. The
`
`LSN is set equal to SNi.
`
`Microprocessor 92 finally writes the sector data
`into data space reserved in step 256. An error correction
`
`code, ECC, is also written with the data.
`
`
`
`The new version of the sector data safely written,
`
`in step 258 microprocessor 92 updates sector header
`
`translation table 94 so that it points to the most recent
`
`version of the sector data associated with the sector
`
`number.
`
`(Ex. 1005 at 14:66-15:36) (emphasis added). As described in the previous section,
`
`Wells discloses the use of files comprising pages of data with associate logical
`
`addresses. (Ex. 1005 at 1:22-26, 17:21-26; Ex. 1003 at ¶¶ 40-41).
`
`At least some of the time, the updated data in Wells will be written into a
`
`block outside of the metablock (the first block and second block). For example, if
`
`the metablock is full, the updated data necessarily will be written to a block other
`
`than the first block and second block. In addition, even if the metablock is not full,
`
`the system follows a dynamic block selection process. Wells discloses at least two