International Bureau
`WORLD INTELLECTUAL PROPERTY ORGANIZATION
`
`INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
`
`(51) In*91‘nati0“a' Patent Classification 6 3
`G11C 16/04
`
`(11) International Publication Number:
`_
`_
`_
`(43) International Publication Date:
`
`WO 99/35650
`
`15 July 1999 ( 15 .07.99)
`
`(21) International Application Number:
`
`PCT/US98/25217
`
`(22) International Filing Date:
`
`24 November 1998 (24.1 1.98)
`
`(30) Priority Data:
`09/002,649
`
`5 January 1998 (05.01.98)
`
`US
`
`(71) Applicant (for all designated States except US): INTEL COR-
`PORATION [US/US]; 2200 Mission College Boulevard,
`Santa Clara, CA 95052 (US).
`
`(81) Designated States: AL, AM, AT, AT (Utility model), AU
`(Petty patent), AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU,
`CZ, CZ (Utility model), DE, DE (Utility model), DK, DK
`(Utility model), EE, EE (Utility model), ES, F1, F1 (Utility
`model), GB, GD, GE, GH, GM, HR, HU, ID, IL, IS, JP,
`KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD,
`MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD,
`SE, SG, SI, SK, SK (Utility model), SL, TJ, TM, TR, TT,
`UA, UG, US, UZ, VN, YU, ZW, ARIPO patent (GH, GM,
`KE, LS, MW, SD, SZ, UG, ZW), Eurasian patent (AM, AZ,
`BY, KG, KZ, MD, RU, TJ, TM), European patent (AT, BE,
`CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC,
`NL, PT, SE), OAPI patent (BF, BJ, CF, CG, CI, CM, GA,
`GN, GW, ML, MR, NE, SN, TD, TG).
`
`(72) Inventors; and
`(75) Inventors/Applicants (for US only): HAZEN, Peter, K.
`[US/US]; 2450 Hidden Oaks Lane, Auburn, CA 95603
`(US). ALEXIS, Ranjeet
`[IN/US];
`101 Alvaston Court, Published
`Folsom, CA 95630 (US). LARSEN, Robert, E. [US/US];
`With international search report.
`5267 Deerwood Drive, Shingle Springs, CA 95682 (US).
`BROWN, Charles, W. [US/US]; 123 Hopper Lane, Folsom,
`CA 95630 (US). TALREJA, Sanjay [IN/US]; 105 Boxcar
`Way, Folsom, CA 95630 (US).
`
`(74) Agents: TAYLOR, Edwin, H. et al.; Blakely, Sokoloff, Taylor
`& Zafman LLP, 7th floor, 12400 Wilshire Boulevard, Los
`Angeles, CA 90025 (US).
`
`(54) Title: FLASH MEMORY PARTITIONING FOR READ—WHILE—WRITE OPERATION
`
`um
`Intorlnco
`
`25.0
`
`rsglstoro
`
`an
`
`(57) Abstract
`
`A method and apparatus for partitioning a flash memory device (20) is provided. The flash memory device includes a plurality of
`partitions, (210, 215, 220, 225, 230), each partition able to be read, written, or erased simultaneously with the other partitions.
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`FOR THE PURPOSES OF INFORMATION ONLY
`
`Codes used to identify States party to the PCT on the front pages of pamphlets publishing international applications under the PCT.
`Slovenia
`SI
`LS
`Lesotho
`ES
`Slovakia
`SK
`LT
`Lithuania
`FI
`SN
`LU
`FR
`Senegal
`Luxembourg
`LV
`Swaziland
`SZ
`Latvia
`GA
`TD
`Monaco
`Chad
`MC
`GB
`TG
`MD
`GE
`Togo
`Republic of Moldova
`MG
`TJ
`GH
`Tajikistan
`Madagascar
`TM
`Turkmenistan
`MK
`GN
`The former Yugoslav
`TR
`GR
`Turkey
`Republic of Macedonia
`TT
`HU
`Mali
`Trinidad and Tobago
`UA
`Ukraine
`IE
`Mongolia
`UG
`Mauritania
`IL
`Uganda
`US
`United Slates of America
`Malawi
`IS
`UZ
`Uzbekistan
`Mexico
`IT
`VN
`Viet Nam
`JP
`Niger
`YU
`KE
`Netherlands
`Yugoslavia
`Zimbabwe
`ZW
`KG
`Norway
`New Zealand
`KP
`Poland
`Portugal
`Romania
`Russian Federation
`Sudan
`Sweden
`Singapore
`
`Albania
`Armenia
`Austria
`Australia
`Azerbaijan
`Bosnia and Herzegovina
`Barbados
`Belgium
`Burkina Faso
`Bulgaria
`Benin
`Brazil
`Belarus
`Canada
`Central African Republic
`Congo
`Switzerland
`Cote d’Ivoire
`Cameroon
`China
`Cuba
`Czech Republic
`Germany
`Denmark
`Estonia
`
`ML
`MN
`MR
`MW
`MX
`NE
`NL
`NO
`NZ
`PL
`PT
`RO
`RU
`SD
`SE
`SG
`
`Spain
`Finland
`France
`Gabon
`United Kingdom
`Georgia
`Ghana
`Guinea
`Greece
`Hungary
`Ireland
`Israel
`Iceland
`Italy
`Japan
`Kenya
`Kyrgyzstan
`Democratic People‘s
`Republic of Korea
`Republic of Korea
`Kazakstan
`Saint Lucia
`Liechtenstein
`Sri Lanka
`Liberia
`
`KR
`KZ
`LC
`LI
`LK
`LR
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`1
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`FLASH MEMORY PARTITIONING FOR READ—WHILE-WRITE
`
`OPERATION
`
`FIELD OF THE INVENTION
`
`The present invention relates to flash memory, and more
`
`specifically, to partitioning of flash memory.
`
`BACKGROUND
`
`Flash memory devices are special type of EEPROM that can be
`
`erased and written to in blocks instead of one byte at a time. Some
`
`applications of the flash memory include embedded control code and
`
`data of a cellular telephone so that it can easily be updated if necessary.
`
`Flash memory may also be used in modems because it enables the
`
`modem manufacturer to support new protocols as they become
`
`standardized. Flash memory may further be used in computers to
`
`provide a basic input / output system (BIOS) that can be upgraded.
`Other uses are known in the art.
`
`Figure 1 illustrates one prior art flash memory device 100. The
`
`memory 110 into which data is written has an X-decoder 160 and a Y-
`decoder 180 associated with it. The X-decoder 160 and Y-decoder 180
`
`permit addressing the rows and columns of memory. A user interface
`
`120 controls the flash memory device 100. The user interface 120
`
`interfaces with a processor that controls access to the memory 110. A
`
`status register 130 stores the current status —— writing, reading, or
`
`erasing -- of the memory 110. The processor knows the status of the
`
`flash memory from the user interface 120.
`
`Sense amplifiers 140 are associated with the memory 110.
`
`In
`
`one prior art implementation, the sense amplifiers are used to amplify
`
`signals for writing to and reading from the memory 110. For a row
`
`divided into sixteen input/ outputs (I/ Os), sixteen sense amplifiers 140
`
`are used for writing and reading, one for each I/ O. A charge pump 150
`
`is further included in the flash memory 100. The charge pump 150 is
`
`used to provide the voltage levels needed for reading from, writing to,
`
`and erasing the memory 110. Generally, prior art flash memory
`
`devices are erased and written to as a block, consisting of a subset of
`
`memory 110. There is one set of circuitry, thus a user can not write to
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`one block of the flash memory while simultaneously erasing or
`
`reading another block of the memory.
`
`Simultaneous operation is desired in some applications that are
`
`constrained by the erase time (typically 250-500 ms) of a flash memory
`
`block. For example, a cellular telephone executes code directly from
`
`the flash memory. It is advantageous to be able to erase a separate
`
`memory block to reclaim space for data storage at the same time.
`
`One prior art solution to this problem is to have multiple flash
`
`memory devices.
`
`In that case, one device may be written to, while the
`
`other device is being erased. This has numerous disadvantages. The
`
`multiple devices take up more real-estate. Because there are multiple
`
`devices hardware is duplicated. Additionally, using multiple flash
`
`memory devices may cost more, increase power use, and decrease
`
`overall system reliability.
`
`SUMMARY OF THE INVENTION
`
`The present invention relates to partitioning of a flash memory
`
`device to permit read-while-write operations. The flash memory
`
`device includes a plurality of partitions, each partition able to be read,
`
`written, or erased simultaneously with the other partitions.
`
`Other features, and advantages of the present invention will be
`
`apparent from the accompanying drawings and from the detailed
`
`description that follows below.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention is illustrated by way of example, and not
`
`by way of limitation, in the figures of the accompanying drawings and
`in which like reference numerals refer to similar elements and in
`
`which:
`
`Figure 1 illustrates a prior art flash memory device.
`
`Figure 2 illustrates one embodiment of a multi-partitioned flash
`
`memory device.
`
`Figure 3 illustrates one embodiment of a three partitioned flash
`
`memory device.
`
`Figure 4 illustrates an example of a cellular telephone using a
`
`flash memory device.
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`DETAILED DESCRIPTION
`
`A method and apparatus for partitioning a flash memory for
`
`read—while—write operation is described.
`
`It is an intended advantage of
`
`the present invention to permit simultaneous reading, and / or writing
`
`and / or erasing operations on a single flash memory device. It is a
`
`further intended advantage of the present invention to permit
`
`updating of code stored on a flash memory device while code is being
`executed.
`
`Figure 2 illustrates a multi-partitioned flash memory device.
`
`Partitions A 210, B 215, C 225, D 220, E 230, .
`
`.
`
`. n-1 235, n 235 are
`
`illustrated. Each partition is implemented as a physically separate
`device on the flash memory device. For one embodiment, each
`
`partition is implemented on a different physical plane. Each of the
`
`partitions 210, 215, 220, 225, 225, 230, 235, and 240 has associated an X
`
`decoder, and a Y selector. Each of the Y selectors are coupled to a Y
`
`decoder 240, that controls the Y selectors. For an alternative
`
`embodiment, multiple Y decoders 240 may be present in the system.
`
`The X decoders and Y selectors enable selection of a specific area within
`
`flash memory 200 for access, including reading, writing, or erasing.
`
`Having multiple X selectors and Y decoders permits simultaneous
`
`access to more than one subsection of the flash memory. For example,
`
`while partition A may be erased, partition B may simultaneously be
`
`read, and partition C written to. Each of the partitions may include
`
`one or more blocks, that may be erased separately. Thus, for example,
`
`a memory in partition A may be written to, while a memory block in
`
`partition B is being erased.
`
`A user interface 250 permits a user to control the access to the
`
`flash memory 200. For one embodiment, the user interface 250 is part
`
`of the flash memory itself. For an alternative embodiment, the user
`
`interface 250 is located on a separate chip. The interface includes a
`
`number of state machines used to control each of the write parallel
`
`operations. Thus, if there can be two parallel write operations (writing
`
`to the data block while updating the code, for example), there are two
`
`state machines.
`
`If there can be three parallel write operations, three
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`state machines are included. These state machines are described in
`
`more detail in the concurrently filed related application entitled
`Serial No.
`
`Status registers are coupled to the user interface 260. The status
`
`registers 260 indicate the status of each partition. There are n
`
`partitions, and for one embodiment there are n status registers 260.
`
`The status of each partition is one of the following:
`
`idle, being read,
`
`being written to, or being erased.
`
`Sense amplifiers 270 are coupled to the user interface 250 as
`
`well. The sense amplifiers are used in the read, write, and erase
`
`operations. For one embodiment, the number of sense amplifiers 270
`
`is determined as follows. For a sixteen bit wide flash memory, sixteen
`
`sense amplifiers 270 are needed for each parallel executable operation.
`
`Thus, for example, if a first partition is read while a second partition is
`
`written to, 32 sense amps 270 are needed. For example, if two
`
`partitions may be read in parallel, 32 sense amps 270 are needed for
`
`reading. The number of sense amplifiers 270 is a factor of the width of
`
`the output row of the flash memory (X) times the number of parallel
`
`executable operations (Y). For one embodiment, for a three partition
`
`flash memory, for example, one partition may be read, another
`
`partition written to, and a third parting erased uses 3X sense amplifiers
`
`270. Sense amplifiers "270 used for erasing use a very low percentage of
`
`the total erase time. Similarly, sense amplifiers 270 used for writing
`
`use a low percentage of the total write time. Therefore, for one
`
`embodiment, a single sense amp 270 is used for each parallel
`
`executable write operation and each parallel executable erase
`
`operation. The sense amp 270 is used for verifying each bit as it is
`written.
`
`Additionally, redundant sense amplifiers 270 may be included
`
`for other operations, such as a redundant column access. For one
`
`embodiment, for each parallel read and / or write, two redundancy
`
`sense amplifiers 270 are included in sense amplifier block 270.
`
`Furthermore, charge pumps 280 are included in the circuit.
`
`Charge pumps 280 are used to set the voltage level for reading, writing,
`
`and erasing. For one embodiment, the Voltage level used for erasing is
`
`approximately -10 volts. For one embodiment, the voltage level used
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`for reading and writing is approximately 7 volts. For one
`
`embodiment, a single charge pump 280 that has multiple leads to
`
`permit parallel access to partitions is used. Alternatively, multiple
`
`separate charge pumps 280 may be used to provide the voltage levels
`needed for accessing the different partitions simultaneously. The
`
`charge pumps 280 are coupled to the Y—selectors of each of the
`
`partitions, to raise the voltage level to the appropriate level to read,
`
`write, or erase.
`
`The multi-partitioned flash memory illustrated in Figure 2 may
`be used for a number of purposes. The number of partitions depends
`
`upon the function of the flash memory. For example, a three
`
`partitioned flash memory device is illustrated in Figure 3.
`
`One example of using a three partitioned flash memory device
`
`is as follows. A first partition may be used to store data. A second
`
`partition may be used to store code, that is executed by an apparatus
`
`that includes the flash memory device. The third partition may be
`
`used to permit updating of the code. Thus, for example, if the code
`
`changes as a result of an update, new code is written to the third
`
`partition while the original code in the second partition is
`
`concurrently executing. When the new code has been written and
`
`verified, the third partition can become the partition used for the code.
`
`Thus, seamless updating of flash memory devices is possible. Another
`
`example of a three partitioned flash memory device is having code
`
`executed from a first partition, while updating data in a second
`
`partition. Thus, for example, if the code execution results in an
`
`updating of data, this can be accomplished seamlessly.
`
`Figure 3 illustrates one embodiment of a three partitioned flash
`
`memory device. Partition A 310, partition B 315, and partition C 320
`
`each have an associated X decoder and Y select, and can be accessed
`
`separately. The layout illustrated in Figure 3 corresponds to one
`
`embodiment of an actual layout of a flash memory device. The X
`decoder 307 and Y select 309 and 312 are associated with Partition A
`
`305, 310. For one embodiment, partition A 310 is split in half by Y
`
`selectors 309, 312. The splitting of partition A 310 is for layout
`
`purposes, such that a first part of partition A 310 is aligned with
`
`partition B, while the other part of partition A 305 is aligned with
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`partition C. For one embodiment, the splitting of partition A 310
`
`optimizes performance for read speed. The Y selectors 309 and 312 are
`
`coupled to Y decoder 325. Additionally, a status register 335 is
`
`associated with partition A. The status register 335 indicates the status
`
`of partition A -- idle, being written to, being read from, or being erased.
`
`Similarly, for partition B, there is an X decoder 317, Y select 319, and a
`
`status register 340. Partition C also includes an X decoder 323, a Y select
`
`322, and a status register 345. For one embodiment, a single user
`
`interface 330 is coupled to the status registers 335, 340, 345 for each of
`
`the partitions.
`
`Sense amplifiers 350 support all of the partitions. For one
`
`embodiment, the number of sense amplifiers is eighteen. Sixteen
`
`sense amplifiers 350,. are used for a read operation to one of the
`
`partitions. One sense amplifier is used for a parallel write operation
`
`from one of the partitions. The interface includes a number of state
`
`machines used to control each of the parallel write operations. Thus,
`
`if there can be two parallel write operations (writing to two partitions
`
`simultaneously), there are two state machines.
`
`The number of charge pumps 360 also parallels the number of
`
`parallel operations. For another embodiment, the number of
`
`connections to a single charge pump 360 equals the number of parallel
`
`operations. Each of these connections may be held at a different
`
`voltage level, permitting multiple operations using different Voltage
`
`levels. For one embodiment, a separate connection is coupled to the
`
`decoders associated with each partition. Thus, a first connection is
`
`coupled to a first partition, a second connection is coupled to a second
`
`partition, and so on. Thus, each connection outputs a variety of
`
`voltage levels, corresponding to each of the operations that may be
`
`executed on the partition. For another embodiment, a first connection
`
`outputs a first voltage level for writing, a second connection outputs a
`
`second voltage level for reading, and a third connection outputs a
`
`third voltage level for erasing.
`
`In this instance, switches couple the
`
`appropriate partition to the appropriate connection for the operation
`
`about to be performed.
`
`Figure 4 illustrates an example of a cellular telephone using a
`
`flash memory device. The cellular telephone 410 includes a flash
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`memory device 430. Although the flash memory device 430 is
`
`illustrated on the cellular phone 410, it is understood that generally
`the flash memory device 430 is received in a receptacle within the body
`of the cellular telephone 410.
`
`The cellular phone 410 illustrated is active. That is, it is
`
`executing code. The partition 460 that includes the currently active
`
`code is being executed. The use of such code is known in the art.
`
`Another partition 450 includes dialing or voice data. For example, the
`
`cell phone 410 may include a dialing director, or similar data in the
`
`data partition 450. A third partition 470 is receiving new code 440 from
`
`outside. For one embodiment, the third partition may be updated
`
`remotely. Thus, while the cellular telephone is active, the code in the
`
`code partition 460 may be executed, while simultaneously new code
`
`440 is written to the new code partition 470, and the data partition 450
`
`is used to recall dialing data. In this way, the cellular telephone
`
`permits seamless updating of its code, and concurrent updating and
`
`use of the cellular telephone. Other applications of such seamless code
`
`updating may be similarly implemented.
`
`In the foregoing specification, the invention has been described
`
`with reference to specific embodiments thereof.
`
`It will, however, be
`
`evident that various modifications and changes may be made thereto
`
`without departing from the broader spirit and scope of the invention.
`
`The specification and drawings are, accordingly, to be regarded in an
`
`illustrative rather than a restrictive sense. The present invention
`
`should not be construed as limited by such embodiments and
`
`examples, but rather construed according to the following claims.
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`CLAIMS
`
`What is claimed is:
`
`1.
`
`A flash memory device comprising:
`
`a plurality of partitions of the flash memory device, each
`
`partition able to be written, read, or erased simultaneously with the
`other partitions.
`
`The flash memory device of claim 1, further comprising:
`2.
`an plurality of x decoders, each x decoder associated with a
`
`partition; and
`
`a plurality of y decoders, each y decoder associated with a
`
`partition.
`
`3.
`
`The flash memory device of claim 1, further comprising a
`
`plurality of sense amplifiers.
`
`4.
`
`The flash memory device of claim 3, wherein the
`
`plurality of sense amplifiers comprising:
`
`a first plurality of sense amplifiers for each simultaneously
`
`executable read operation; and
`
`at least one sense amplifier for each simultaneously executable
`
`erase and write operation.
`
`5.
`
`The flash memory device of claim 4, wherein the first
`
`plurality of sense amplifier comprises a plurality of sense amplifiers
`
`for each parallel read operation.
`
`6.
`
`The flash memory device of claim 1, further comprising a
`
`charge pump for providing a voltage output.
`
`7.
`
`The flash memory device of claim 6, wherein the charge
`
`pump provides a plurality of voltage outputs.
`
`8.
`
`The flash memory device of claim 7, wherein the
`
`plurality of voltage outputs corresponds in number to the plurality of
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`partitions of the flash memory device, thereby providing a voltage
`output for each partition.
`
`9
`
`9.
`
`The flash memory device of claim 1, further comprising a
`
`plurality of status registers.
`
`10.
`
`The flash memory device of claim 9, wherein the
`
`plurality of status registers corresponds to the plurality of partitions of
`
`the flash memory device.
`
`11.
`
`A system comprising:
`
`a bus;
`
`a processor coupled to the bus; and
`
`a memory coupled to the bus and accessible by the processor, the
`
`memory including a flash memory, the flash memory comprising a
`
`plurality of partitions, each of the partitions separately readable,
`
`writable, and erasable.
`
`12.
`
`The flash memory device of claim 11, further comprising:
`
`an plurality of x decoders, each of the x decoders associated with
`
`a partition;
`
`a plurality of y decoders, each of the y decoders associated with a
`
`partition.
`
`13.
`
`The flash memory device of claim 11, further comprising
`
`a plurality of sense amplifiers.
`
`14.
`
`The flash memory device of claim 13, wherein the
`
`plurality of sense amplifiers comprising:
`
`a first plurality of sense amplifiers for each simultaneously
`
`executable read operation; and
`
`at least one sense amplifier for each simultaneously executable
`
`erase and write operation.
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`15.
`
`The flash memory device of claim 14, wherein the first
`
`plurality of sense amplifier comprises sixteen sense amplifiers for each
`
`parallel read operation.
`
`16.
`
`The flash memory device of claim 11, further comprising
`
`a charge pump for providing a Voltage output.
`
`17.
`
`The flash memory device of claim 16, wherein the charge
`
`pump provides a plurality of voltage outputs.
`
`18.
`
`The flash memory device of claim 17, wherein the
`
`plurality of voltage outputs corresponds in number to the plurality of
`
`partitions of the flash memory device, thereby providing a voltage
`
`output for each partition.
`
`19.
`
`The flash memory device of claim 11, further comprising
`
`a plurality of status registers.
`
`20.
`
`The flash memory device of claim 19, wherein the
`
`plurality of status registers corresponds to the plurality of partitions of
`
`the flash memory device.
`
`21.
`
`A method of simultaneously accessing and erasing a flash
`
`memory, the flash memory including a first partition, a second
`
`partition, and a third partition, the method comprising:
`
`accessing the first partition or the second partition; and
`
`simultaneously erasing the third partition.
`
`22.
`
`The method of claim 21, wherein said step of accessing
`
`comprises reading from or writing to the first partition or the second
`
`partition.
`
`23.
`
`The method of claim 21, wherein said step of erasing
`
`comprises the step of:
`
`applying a first voltage level to the third partition.
`
`SUBSTITUTE SHEET (RULE 26)
`
`APPLE INC.
`EXHIBIT 1010 - PAGE 0012
`
`

`
`WO 99/35650
`
`PCT/U598/25217
`
`ll
`
`24.
`
`The method of claim 23, wherein said step of accessing
`
`comprises the step of:
`
`applying a second voltage level to the first or the second
`
`partition.
`
`25.
`
`The method of claim 24, wherein said second voltage
`
`level is lower than said first voltage level.
`
`SUBSTITUTE SHEET (RULE 26)
`
`APPLE INC.
`EXHIBIT 1010 - PAGE 0013
`
`

`
`WO 99/35650
`
`PCT/US98/25217
`
`User
`
`Interface
`J_2_Q
`
`Y decoder
`.‘L8_Q
`
`Fig.1 (Prior Art)
`
`APPLE INC.
`EXHIBIT 1010 - PAGE 0014
`
`

`
`WO 99/35650
`
`71nH89mTCP
`
`
`
`maE:m%§_omaE<omcmm82...
`
`
`3.5crx.oo£..2:_
`
`
`OIWM
`
`APPLE INC.
`EXHIBIT 1010 - PAGE 0015
`
`

`
`WO 99/35650
`
`PCT/US98/25217
`
`interface
`3_3_Q
`
`Status Reg.
`for A
`
`Status Reg.
`for B
`
`Status Reg.
`for C
`
`309
`
`II Partition A 307
`
`AA
`1-P
`
`Y
`decoder
`
`Sense Amps
`3.5.0
`
`Charge Pump
`
`1
`3.6.5
`
`Charge Pump
`2
`3.6.Q
`
`Charge Pump
`3
`,
`3.82 L
`
`325
`
`X decoder Part. B 317 H X decoder Part. C 323
`
`Partition B
`3.1.5
`
`Partition C
`3.29
`
`(
`
`B)
`
`(C)
`
`Fig.
`
`3
`
`319
`
`22
`
`3
`
`APPLE INC.
`EXHIBIT 1010 - PAGE 0016
`
`

`
`WO 99/35650
`
`PCT/US98/25217
`
`Flash Memory 430
`
`Dialing/Voice
`Data
`450
`
`APPLE INC.
`EXHIBIT 1010 - PAGE 0017
`
`

`
`INTERNATIONAL SEARCH REPORT
`
`[ntcmational application No.
`PCT/US98/25217
`
`A.
`
`CLASSIFICATION OF SUBJECT MATTER
`
`:G1lC 16/O4
`IPC(6)
`US CL :365/185.11,185.33,18S.29,189.04
`According to International Patent Classification (IPC) or to both national classification and IPC
`B.
`FIELDS SEARCHED
`
`Minimum documentation searched (classification system followed by classification symbols)
`
`U.S.
`
`:
`
`365/185.11,l85.33,185.29,189.04
`
`Documentation searched other than minimum documentation to the extent that such documents are included in the fields seurclied
`NONE
`
`Electronic data base consulted during the international search (name of data base and, where practicable, search terms used)
`U.S. PTO APS
`
`C.
`
`DOCUMENTS CONSIDERED TO BE RELEVANT
`
`Category*
`
`Citation of document, with indication, where appropriate, of the relevant passages
`
`Relevant to claim No.
`
`X,P
`
`US 5,748,528 A (CAMPARDO et al.) 05 May 1998 (05/05/98) see
`entire document.
`
`1-25
`
`I: Further documents are listed in the continuation of Box C. C]
`Special categories of cited documents:
`
`document defining the general state of the art which is not considered
`to be of particular relevance
`earlier document published on or after the intsmationul filing date
`document which may throw doubts on priority claim(s) or which is
`cited to establish the publication date of another citation or other
`special reason (as specified)
`document referring to Ill onl disclosure, use, exhibition or other
`moons
`
`document published prior to the international filing date but later than
`the priority date claimed
`Date of the actual completion of the international search
`
`05 MARCH 1999
`
`Name and mailin address of the ISA/US
`Commissioner of stents and Trademarks
`Box PCT
`Washington. D.C. 20231
`Facsimile No.
`(703) 305-3230
`
`Form PCT/ISA/210 (second sheet)(July 1992):
`
`see patent family annex.
`later document published after the international filing date or priority
`date and not in conflict with the application but cited to understand
`an Principle 0, meow underlying an invention
`document of particular relevance; the claimed invention cannot be
`considered novel or cannot be considered to involve an inventive step
`when the document is taken alone
`
`the claimed invention cannot be
`document of particular relevance;
`considered to involve an inventive stop when the document
`is
`combined with one or more other such documents, such combination
`being obvious to a person skilled in the art
`document member of the same patent family
`
`Date of mailing of the international search report
`
`15 APR i999
`
`(703) 308-0089
`
`APPLE INC.
`EXHIBIT 1010 - PAGE 0018