UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`Samsung Electronics, Co., Ltd., and
`Samsung Electronics America, Inc.
`PETITIONERS
`
`V.
`
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`Case IPR No: 2015-01944
`Patent No. 5,812,789
`Title: VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION
`DEVICE THAT SHARES A MEMORY INTERFACE
`____________
`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. 37 C.F.R. §42.107
`
`
`
`
`

`
`I.
`II.
`III.
`IV.
`
`
`
`TABLE OF CONTENTS
`
`INTRODUCTION .......................................................................................... 1
`THE `789 PATENT ...................................................................................... 2
`THE PROPOSED GROUNDS ARE REDUNDANT ............................................ 3
`PETITIONER DOES NOT ESTABLISH A REASONABLE LIKELIHOOD THAT
`ANY CHALLENGED CLAIM IS INVALID ...................................................... 7
`A. Lambrecht (claims 1, 3, 5, 11, and 13) .................................................... 7
`1. Lambrecht does not disclose a shared bus that enables “the decoder to
`access the memory” and operate in real time ........................................... 8
`2. Lambrecht does not disclose a shared bus that has “a sufficient
`bandwidth” to enable the decoder to access the memory and operate in
`real time .................................................................................................. 12
`B. Lambrecht in view of Artieri (claim 4) .................................................. 15
`C. Lambrecht in view of Moore (claim 6) .................................................. 15
`D. Rathnam in view of Lambrecht (claims 1, 3, 4, 5, and 11) ................... 16
`1. Rathnam does not disclose an arbiter for selectively providing access for
`the first device and the decoder to the memory (“arbiter limitation”) ... 19
`2. Rathnam does not disclose the bus having a sufficient bandwidth
`to enable the decoder to access the memory and operate in real time
`when the first device simultaneously accesses the bus
`(“real time limitation”) ........................................................................... 21
`3. Combination of Rathnam with Lambrecht does not disclose the real time
`limitation ................................................................................................ 22
`4. No motivation to combine Rathnam and Lambrecht ............................. 23
`E. Rathnam in view of Lambrecht and Moore (claim 6) ........................... 30
`F. Rathnam in view of Lambrecht and Slavenburg (claim 13) .................. 30
`CONCLUSION ........................................................................................... 31
`V.
`
`
`
`
`ii
`
`

`
`TABLE OF AUTHORITIES
`
`Cases
`
`Amkor Tech., Inc. v. Tessera, Inc., 2013 WL 5653117,
` IPR2013-00242 (Patent Tr. & App. Bd. Oct. 11, 2013) ................................ 10
`
`
`Berk-Tek LLC v. Belden Tech. Inc., IPR2013-00057,
`2013 WL 5947699 (Patent Tr. & App. Bd. May 14, 2013) ............................ 10
`
`
`C.R Bard, Inc. v. M3 Sys., Inc.,
`157 F.3d 1350 (Fed. Cir. 1998) ....................................................................... 27
`
`
`CONOPCP, Inc. v. The Procter & Gamble Co., IPR2013-00505,
`2014 WL 1253037 (Patent Tr. & App. Bd. Feb. 12, 2014) ............................ 10
`
`
`Epistar, et al. v. Trustees Of Boston University, No. IPR2013-00298,
`Decision Not To Institute, Paper No. 18 (P.T.A.B. November 15, 2103) 32, 33
`
`
`Illumina, Inc. v. Trustees of Columbia Univ., No. IPR2012-00006,
`Paper 43 (P.T.A.B. May 10, 2013) ................................................................ 8, 9
`
`
`In re Fine,
`837 F.2d 1071 (Fed. Cir. 1988) ........................................................... 33, 34, 35
`
`
`In re Wilson,
`424 F.2d 1382 (CCPA 1970) ..................................................................... 26, 27
`
`
`Kinetic Tech., Inc. v. Skyworks Solutions, Inc., IPR2014-00530,
`2014 WL 4925282 (Patent Tr. & App. Bd. Sep. 29, 2014) ............................ 28
`
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ........................................................................................ 27
`
`
`Liberty Mutual Ins. Co. v. Progressive Casualty Ins. Co.,
`No. CBM-2012-00003, Paper No. 8 (P.T.A.B. Oct. 25, 2012) ......................... 7
`
`
`
`
`
`iii
`
`

`
`Oracle Corp. v. Clouding IP, LLC, IPR2013-00088,
`2013 WL 5970180 (Patent Tr. & App. Bd. Jun. 13, 2013) ............................. 10
`
`
`OSRAM Sylvania, Inc. v. Am Induction Techs., Inc.,
`701 F.3d 698 (Fed. Cir. 2012) ......................................................................... 33
`
`
`Richardson v. Suzuki Motor Co.,
`868 F.2d 1226 (Fed. Cir. 1989) ....................................................................... 18
`
`
`Teleflex, Inc. v. Ficos N. America Corp.,
`299 F.3d 1313 (Fed. Cir. 2002) ....................................................................... 28
`
`
`United States v. Adams,
`383 U.S. 39 (1966) .......................................................................................... 32
`
`
`Verdegaal Bros. v. Union Oil Co. of California,
`814 F.2d 628 (Fed. Cir. 1987) ......................................................................... 18
`
`
`Rules
`
`35 U.S.C. § 314(a) ................................................................................................ 5
`
`37 C.F.R § 42.1(b) ................................................................................................ 8
`
`
`
`
`iv
`
`

`
`I.
`
`INTRODUCTION
`
`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
`
`Owner”) respectfully requests that the Board deny the Petition for Inter Partes
`
`review (“Petition”) filed by Samsung Electronics Co., Ltd., and Samsung
`
`Electronics America, Inc. (collectively, “Petitioner”) regarding certain claims of
`
`U.S. Patent No. 5,812,789 (“`789 Patent”) because the Petition fails to
`
`demonstrate a reasonable likelihood that the Petitioner would prevail as to at least
`
`one of the challenged claims, as required under 35 U.S.C. § 314(a).
`
`The Petition proposes six grounds challenging claims 1, 3-6, 11 and 13
`
`(“challenged claims”). Specifically, the Petitioner contends that certain
`
`challenged claims are invalid as anticipated by Lambrecht (Ground A). The
`
`Petitioner also contends that certain dependent challenged claims are obvious in
`
`view of Lambrecht and Artieri (Ground B) or Moore (Ground C). Additionally,
`
`the Petitioner contends that certain challenged claims are obvious in view of
`
`Rathnam and Lambrecht (Ground D). Finally, the Petitioner contends that certain
`
`dependent challenged claims are obvious in view of Rathnam and Lambrecht
`
`further in view of Moore (Ground E) or Slavenburg (Ground F).
`
`Ground A fails at least because Lambrecht does not disclose all limitations
`
`of independent claim 1 and, therefore, does not anticipate that claim. By
`
`
`
`1
`
`

`
`extension, the challenged dependent claims are also not anticipated by Lambrecht
`
`or rendered obvious as the Petitioner contends for at least the same reasons.
`
`Therefore, there is no reasonable likelihood that the Petitioner would prevail with
`
`respect to any of the claims challenged in Grounds A-C.
`
`Similarly, Grounds D-F fail at least because Rathnam and Lambrecht, alone
`
`or in combination, do not disclose all limitations of independent claim 1.
`
`Moreover, one of ordinary skill in the art would not have been motivated to
`
`combine Rathnam with Lambrecht as the Petitioner proposes. At least for these
`
`reasons, Rathnam and Lambrecht, alone or in combination, fail to disclose all
`
`limitations of independent claim 1 and do not render that claim obvious. By
`
`extension, the challenged dependent claims are also not obvious in view of
`
`Rathnam and Lambrecht for at least the same reasons. Therefore, there is no
`
`reasonable likelihood that the Petitioner would prevail with respect to any of the
`
`claims challenged in Grounds D-F.
`
`The Petition should be denied because there is no reasonable likelihood that
`
`the Petitioner would prevail as to any of the challenged claims.
`
`II. THE `789 PATENT
`
`The `789 Patent is generally directed to sharing a memory interface and
`
`memory between a video and/or audio decoder and another device contained in
`
`
`
`2
`
`

`
`an electronic system. `789 Pat. [Ex. 1001], Abstract; independent claim 1.
`
`Accordingly, the electronic system includes a first device that requires access to
`
`the memory and a decoder that requires access to the memory sufficient to
`
`maintain real time operation. Id. at claim 1. A memory interface is coupled to the
`
`memory, the first device and the decoder. Id. The memory interface includes an
`
`arbiter for selectively providing access for the first device and the decoder to the
`
`memory. Id. A shared bus is coupled to the memory, the first device and the
`
`decoder. Id. The shared bus has sufficient bandwidth to enable the decoder to
`
`access the memory and operate in real time when the first device simultaneously
`
`accesses the shared bus. Id.
`
`III. THE PROPOSED GROUNDS ARE REDUNDANT
`
`The Petitioner proposes two sets of grounds of rejection: Grounds A-C
`
`using Lambrecht for both anticipation and as the primary reference for
`
`obviousness; and Grounds D-F using Rathnam as the primary reference for
`
`obviousness. Pet. at 10-47. The Petitioner’s proposed grounds have horizontal
`
`redundancy which has been prohibited by the Board. Liberty Mutual Ins. Co. v.
`
`Progressive Casualty Ins. Co., No. CBM-2012-00003, Paper No. 8 (P.T.A.B.
`
`Oct. 25, 2012). Horizontal redundancy “involves a plurality of prior art references
`
`applied not in combination to complement each other but as distinct and separate
`
`
`
`3
`
`

`
`alternatives.” Id. at 3. The Petition has horizontal redundancy because it includes
`
`grounds proposing the rejection of claims 1, 3-6, 11 and 13 as i) anticipated by
`
`Lambrecht or rendered obvious using Lambrecht as the primary reference; and ii)
`
`rendered obvious using Rathnam as the primary reference. Pet. at 10-47.
`
`The Board has made clear that in order to ensure “the just, speedy, and
`
`inexpensive resolution of every proceeding,” it will not institute inter partes
`
`review proceedings on cumulative grounds. Illumina, Inc. v. Trustees of
`
`Columbia Univ., No. IPR2012-00006, Paper 43 (P.T.A.B. May 10, 2013) (citing
`
`37 C.F.R § 42.1(b)). Indeed, the Board has instructed parties that it will not
`
`“authorize inter partes review on certain unpatentability challenges . . . [where]
`
`the challenges appear to rely on the same prior art facts as other challenges for
`
`which inter partes review had been authorized.” Id. “In other words, considering
`
`multiple rejections for the same unpatentability issue would unnecessarily
`
`consume the time and resources of all parties involved.” Id.
`
`To avoid dismissal of a proposed ground of unpatentability, a petitioner
`
`must “provide a meaningful distinction between the different, redundant
`
`rejections.” Id. Where multiple references have been cited for the same facts, it is
`
`not enough for a petitioner to argue that the cited references are not identical, or
`
`to “speculate[] that in certain publications an element may be more clearly set
`
`
`
`4
`
`

`
`forth in one publication rather than another.” Id. Rather, a petitioner must provide
`
`an adequate explanation as to the differences between the references and “how
`
`this difference would impact the unpatentability challenge.” Id.
`
`Petitioner acknowledges that Grounds A-C and Grounds D-F both
`
`challenge the same claims. Pet. at 5. However, the petitioner contends that the
`
`proposed grounds are not redundant because: (1) Lambrecht, the primary
`
`reference in Grounds A-C, addresses the claimed “real time” operation, “memory
`
`interface,” and “decoder” in a different way than Rathnam, the primary reference
`
`in Grounds D-F; and (2) Lambrecht has a chipset that Rathnam does not have.
`
`Pet. at 5.
`
`That Lambrecht and Rathnam address the claimed “real time” operation,
`
`“memory interface” and “decoder” in different ways or that Lambrecht includes
`
`a chipset that Rathnam does not have is not sufficient to establish lack of
`
`redundancy. The Board has recognized that “absent some explanation as to why
`
`differences between a set of prior art references are relevant (e.g., why reference
`
`A is a stronger reference with respect to claim element X than reference B), the
`
`fact that references disclosed slightly different things does not demonstrate that
`
`asserted grounds are not cumulative to each other.” Amkor Tech., Inc. v. Tessera,
`
`Inc., No. IPR2013-00242, 2013 WL 5653117, *17 (P.T.A.B. Oct. 11, 2013)
`
`
`
`5
`
`

`
`(emphasis added). Because the Petition makes “no meaningful distinction”
`
`between Grounds A-C and Grounds D-F, the Patent Owner respectfully submits
`
`that the proposed grounds are cumulative and redundant. See Berk-Tek LLC v.
`
`Belden Tech. Inc., No. IPR2013-00057, 2013 WL 5947699, *3 (P.T.A.B. May
`
`14, 2013) (“If petitioner makes no meaningful distinction between certain
`
`grounds, the Board may exercise discretion by acting on one or more grounds and
`
`regard the others as redundant”); Oracle Corp. v. Clouding IP, LLC, No.
`
`IPR2013-00088, 2013 WL 5970180, *3 (P.T.A.B. Jun. 13, 2013) (“[I]n the
`
`absence of the Petitioner identifying meaningful distinctions in terms of relative
`
`strengths and weaknesses of the different prior art references, it is within the
`
`discretion of the Board to conclude that even with different facts in
`
`different grounds, multiple grounds may nevertheless be redundant”) (emphasis
`
`added); CONOPCP, Inc. v. The Procter & Gamble Co., No. IPR2013-00505,
`
`2014 WL 1253037, *10 (P.T.A.B. Feb. 12, 2014) (finding the grounds redundant
`
`where petitioner did not identify “strengths or weaknesses in the prior art
`
`disclosures as they relate to the limitations of those claims”) (emphasis added).
`
`The Petitioner failed to explain how Lambrecht differs from Rathnam or
`
`how any consideration of the grounds that use Lambrecht as the primary reference
`
`for claims 1, 3-6, 11 and 13 would impact these proceedings differently than a
`
`
`
`6
`
`

`
`consideration of the grounds that use Rathnam as the primary reference. See, e.g.,
`
`id. The Petitioner also failed to explain why the reliance on Lambrecht for these
`
`claims may be the stronger assertion as applied in certain instances and why the
`
`reliance on Rathnam may be the stronger assertion in other instances. See Pet. at
`
`10-47.
`
`Accordingly, nothing in the Petitioner’s analysis of the claims suggests that
`
`the grounds using Lambrecht would (or even could) be more determinative of an
`
`outcome of these proceedings than the grounds using Rathnam. Id. Instead, all
`
`the Petitioner has done is to propose redundant grounds of rejection, and request
`
`institution of a patent trial on all proposed rejections. Id. As indicated above, the
`
`Board has consistently held that such a request will not suffice to preclude
`
`dismissal of proposed challenges on grounds of redundancy.
`
`Accordingly, the Petitioner’s proposed grounds of unpatentability using
`
`Lambrecht (i.e., Grounds A-C) are redundant over the proposed ground of
`
`unpatentability using Rathnam (i.e., Grounds D-F). For this reason alone, the
`
`Board should deny Grounds D-F as redundant.
`
`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE LIKELIHOOD THAT
`ANY CHALLENGED CLAIM IS INVALID
`
`
`A. Lambrecht (claims 1, 3, 5, 11, and 13)
`
`
`
`7
`
`

`
`Lambrecht does not anticipate independent claim 1 because at least two
`
`limitations of independent claim 1 are not disclosed by Lambrecht.
`
`1. Lambrecht does not disclose a shared bus that enables “the
`decoder to access the memory” and operate in real time
`
`Independent claim 1 recites a shared bus coupled to the memory, the first
`
`device and the decoder which enables “the decoder to access the memory and
`
`operate in real time.” Ex. 1001, claim 1. The Petition identifies multimedia device
`
`(142D) as the first device; the main memory (110) as the memory; the multimedia
`
`device (144D) as the decoder; and the PCI expansion bus (120) as the shared bus.
`
`Pet. at 16. The Petitioner then contends that the PCI expansion bus (120) provides
`
`real time access by the multimedia device (144D) (alleged decoder) to the main
`
`memory (110) (alleged memory) when operating in the multimedia mode which
`
`is a special mode optimized for real-time data transfers. Pet. at 17-19. The Patent
`
`Owner respectfully disagrees because when operating in the multimedia mode,
`
`the PCI expansion bus (120) (alleged shared bus) does not transfer data between
`
`the multimedia device (144D) (alleged decoder) and the main memory (110)
`
`(alleged memory). Instead, when operating in the multimedia mode, data is
`
`transferred through the PCI expansion bus (120) (alleged shared bus) from one
`
`multimedia device to another.
`
`
`
`8
`
`

`
`In describing the embodiment of Figure 21 which is relied upon by the
`
`Petitioner, Lambrecht states:
`
`Thus, the multimedia devices 142D-146D communicate with each
`other and with the CPU 102 and main memory 110 via the PCI bus
`120, as is well known in the art. The multimedia devices 142D-146D
`also communicate data between using the PCI bus signal lines 120
`when the PCI bus 120 is in the multimedia mode.
`Lambrecht at 27:57-62. It is unclear from this portion of Lambrecht whether the
`
`PCI bus (120) operating in the multimedia mode transfers data from the
`
`multimedia device (144D) (alleged decoder) to the main memory (110) (alleged
`
`memory) or from one multimedia device 142D-146D to another. However, a
`
`closer scrutiny of Lambrecht makes it evident that the operation of the PCI bus
`
`(120) in the multimedia mode is directed to transferring data from one multimedia
`
`device to another.
`
`In describing the embodiment of Figure 21, Lambrecht notes that “[t]he
`
`computer system of FIG. 21 is similar to the computer system of FIG. 1” except
`
`that “the mode logic in the computer system of FIG. 21 is operable to place the
`
`PCI bus 120 in either a normal PCI mode or in a real-time/multimedia mode
`
`optimized for multimedia transfers of periodic data.” Lambrecht at 26:48-56.
`
`Accordingly, the embodiment of Figure 21 replaces the PCI expansion bus (120)
`
`and the real time bus (130) of Figure 1 with a single PCI expansion bus (120)
`
`which has two different modes of operation. However, the operation of the PCI
`9
`
`
`
`

`
`bus (120) of the embodiment of Figure 21 in the multimedia mode is analogous
`
`to the operation of the real-time bus (multimedia bus) (130) of Figure 1. See
`
`Lambrecht at 26:48-56.
`
`With respect to the operation of the multimedia bus (130) of Figure 1,
`
`Lambrecht provides:
`
`The multimedia devices 142-146 use the multimedia bus 130 to
`communicate data, preferably only periodic data, between the
`respective devices. … Thus, the multimedia devices 142-146
`communicate with each other via the PCI bus 120 and also
`communicate with the CPU and main memory 110 via the PCI bus
`120, as is well known in the art. The multimedia devices 142-146
`also communicate data between each other using the real-time bus
`or multimedia bus 130. When the multimedia devices 142-146
`communicate using the real-time bus 130, the devices are not
`required to obtain PCI bus mastership and they consume little or no
`PCI bus cycles.”
`
`
`Lambrecht, 8:8-28.
`
`In fact, as shown in Figure 1 (reproduced below), real-time bus (130)
`
`only facilitates data transfer between the multimedia devices (142, 144,
`
`146). The real-time bus (130) is not connected to the PCI Bridge Chipset
`
`(106) and the main memory (110) and cannot transfer data from the
`
`multimedia device (144) (alleged decoder) to the main memory (110)
`
`(alleged memory).
`
`
`
`10
`
`

`
`
`
`Accordingly, assuming that the Petitioner has correctly identified the
`
`main memory (110), the PCI expansion bus (120) operating in multimedia
`
`mode, and the multimedia device (144D) as being analogous to the recited
`
`memory, shared bus and decoder (which Patent Owner does not concede),
`
`Lambrecht nevertheless fails to anticipate independent claim 1 because
`
`when the PCI expansion bus (120) operates in the multimedia mode it
`
`transfers data between the multimedia devices (142D, 144D, 146D). Data
`
`is not transferred from the multimedia device (144D) (alleged decoder) to
`
`the main memory (110) (alleged memory) using the PCI expansion bus
`
`
`
`11
`
`

`
`(120) (alleged shared bus) when the PCI expansion bus (120) operates in
`
`the multimedia mode.
`
`2. Lambrecht does not disclose a shared bus that has “a sufficient
`bandwidth” to enable the decoder to access the memory and
`operate in real time
`
`Independent claim 1 recites a shared bus having “a sufficient bandwidth to
`
`enable the decoder to access the memory and operate in real time.” The Petition
`
`identifies the main memory (110) as the recited memory; the PCI expansion bus
`
`(120) operating in the multimedia mode as the recited “shared bus” and the
`
`multimedia device (144D) as the recited decoder. First, as discussed in Section
`
`IV.A.1, supra, the PCI expansion bus (120) operating in the multimedia mode
`
`does not enable the multimedia device (144D) (alleged decoder) to access the
`
`main memory (110) (alleged memory) in real time. Moreover, even if the PCI
`
`expansion bus (120) operating in multimedia mode did facilitate data transfer
`
`from the multimedia device (144D) (alleged decoder) to the main memory (110)
`
`(alleged memory) (which it does not), the multimedia device (144D) would
`
`nevertheless not be able to access the main memory (110) and operate in real
`
`time.
`
`Specifically, as shown in Figure 21 (reproduced below), any data
`
`transferred from the multimedia device (144D) to the main memory (110) of
`
`
`
`12
`
`

`
`Lambrecht would have to pass through at least three different components: (1)
`
`the PCI expansion bus (120); (2) the PCI Bridge Chipset (106); and (3) the
`
`memory bus (108). Accordingly, all three of these components must facilitate real
`
`time data transfer in order to allow real time access by the multimedia device
`
`(144D) (alleged decoder) to the main memory (110) (alleged memory). The
`
`Petitioner has not identified any portion of Lambrecht which discloses the PCI
`
`Bridge chipset (106) or the memory bus (108) operating in real time. Because the
`
`PCI Bridge chipset (106) and the memory bus (108) do not operate in real time,
`
`the multimedia device (144D) (alleged decoder) cannot access the main memory
`
`(110) (alleged memory) and operate in real time as recited in independent claim
`
`1.
`
`
`
`13
`
`

`
`
`
` A claim is anticipated only if each and every element as set forth in the
`
`claim is found, either expressly or inherently described, in a single prior art
`
`reference. Verdegaal Bros. v. Union Oil Co. of California, 814 F.2d 628, 631
`
`(Fed. Cir. 1987). Accordingly, “[t]he identical invention must be shown in as
`
`complete detail as is contained in the … claim.” Richardson v. Suzuki Motor Co.,
`
`868 F.2d 1226, 1236 (Fed. Cir. 1989). Because Lambrecht does not disclose every
`
`limitation of independent claim 1 (as discussed above), it does not anticipate that
`
`claim. Claims 3, 5, 11 and 13 depend on independent claim 1 and are therefore
`
`not anticipated by Lambrecht for at least the same reasons.
`
`
`
`
`
`
`
`14
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`

`
`B. Lambrecht in view of Artieri (claim 4)
`
`The Petition alleges that claim 4 is obvious in view of Lambrecht and
`
`Artieri. Claim 4 depends on independent claim 1. As discussed in Section IV.A.,
`
`supra, Lambrecht fails to disclose all limitations of independent claim 1. The
`
`Petition only relies on Artieri for its alleged disclosure of “the decoder [being]
`
`capable of decoding a bitstream formatted to comply with the MPEG-2 standard.”
`
`Pet. at 24-25. Therefore, Artieri does not disclose that which Lambrecht lacks and
`
`independent claim 1 is also not obvious in view of the proposed combination of
`
`Lambrecht and Artieri. Dependent claim 4 is allowable at least for the same
`
`reasons and the Petition fails to establish a reasonable likelihood of establishing
`
`invalidity with respect to this claim. In re Fine, 837 F.2d at 1076 (“Dependent
`
`claims are nonobvious under § 103 if the independent claims from which they
`
`depend are nonobvious”).
`
`C. Lambrecht in view of Moore (claim 6)
`
`The Petition alleges that claim 6 is obvious in view of Lambrecht and
`
`Moore. Claim 6 depends on independent claim 1. As discussed in Section IV.A.,
`
`supra, Lambrecht fails to disclose all limitations of independent claim 1. The
`
`Petition only relies on Moore for its alleged disclosure of “the decoder, the
`
`encoder and the memory interface [being] monolithically integrated into the first
`
`
`
`15
`
`

`
`device.” Pet. at 26-27. Therefore, Moore does not disclose that which Lambrecht
`
`lacks and independent claim 1 is also not obvious in view of the proposed
`
`combination of Lambrecht and Moore. Dependent claim 6 is allowable at least
`
`for the same reasons and the Petition fails to establish a reasonable likelihood of
`
`establishing invalidity with respect to this claim. In re Fine, 837 F.2d at 1076
`
`(“Dependent claims are nonobvious under § 103 if the independent claims from
`
`which they depend are nonobvious”).
`
`D. Rathnam in view of Lambrecht (claims 1, 3, 4, 5, and 11)
`
`Fundamentally, Rathnam discloses nothing more than the very same
`
`system identified in the `789 Patent as prior art. In describing the background of
`
`the invention, the `789 Patent notes that a typical decoder such as an MPEG
`
`decoder (10) contained a video/audio decoding circuit (12/14), a microcontroller
`
`(16), and a memory interface (18) coupled to a dedicated memory (22). `789 Pat.
`
`[Ex. 1001], 2:4-26. The `789 Patent then highlights the disadvantages of this prior
`
`art system:
`
`A typical MPEG decoder 10 requires 16 Mbits of memory to operate
`in the Main Profile at Main Level mode (MP at ML). This typically
`means that the decoder requires a 2 Mbyte memory. Memory 22 is
`dedicated to the MPEG decoder 10 and increases the price of adding
`a decoder 10 to the electronic system. In current technology, the cost
`of this additional dedicated memory 22 can be a significant
`percentage of the cost of the decoder.
`
`
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`16
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`

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`Id. at 2:26-34. Figure 1a of the `789 Patent depicts this prior art configuration and
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`is reproduced below side by side with Figure 1 of Rathnam.
`
`
`Like the prior art system discussed in the `789 Patent, Figure 1 of Rathnam
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`depicts a block diagram of the TM-1 multimedia processor which “consists of the
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`TM-1 microprocessor itself, a block of synchronous DRAM (SDRAM), and
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`minimal external circuitry to interface to the incoming and/or outgoing
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`multimedia data streams.” Rathnam [Ex. 1005], at 13. In a “typical mode of
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`operation,” the TM-1 described in Rathnam “serve[s] as a video-decompression
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`engine on a PCI card in a PC.” Id. at 14 (emphasis added). In fact, the memory
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`size of TM-1’s SDRAM is the same as the memory size of the dedicated memory
`
`of prior art decoders disclosed in the `789 Patent. Compare Rathnam [Ex. 1005]
`
`at 15 (“TM-1’s DRAM memory size can range from 2Mbytes to 64 Mbytes”);
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`17
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`

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``789 Pat. [Ex. 1001], 2:29-32 (“This typically means that the decoder requires a
`
`2 Mbyte memory. Memory 22 is dedicated to the MPEG decoder …”).
`
`Accordingly, Rathnam discloses the very same configuration identified in
`
`the `789 Patent as prior art and suffers from the same drawbacks. In fact, the `789
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`Patent is directed to eliminating the SDRAM of Rathnam – i.e., the decoder’s
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`dedicated memory. See `789 Pat., 4:30-34 (“An advantage of the present
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`invention is the significant cost reduction due to the fact that the video and/or
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`audio decompression and/or compression device does not need its own dedicated
`
`memory but can share a memory with another device and still operate in real
`
`time”).
`
`A comparison of the limitations of the challenged claims with the
`
`disclosure of Rathnam as discussed below underscores the fact that Rathnam does
`
`not disclose the improved configuration of the `789 Patent and is instead, directed
`
`to what the `789 Patent identifies as the prior art.
`
`The Petition does not establish a reasonable likelihood that any challenged
`
`claim is invalid as obvious in view of Rathnam and Lambrecht because: (1)
`
`Rathnam and Lambrecht, alone or in combination, fail to disclose all limitations
`
`of the challenged claims; and (2) one of ordinary skill would not have been
`
`motivated to combine Rathnam and Lambrecht as suggested by the Petitioner.
`
`
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`18
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`

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`Accordingly, the proposed combination of Rathnam with Lambrecht does not
`
`render independent claim 1 obvious. By extension, dependent claims 3-5 and 11
`
`are also not rendered obvious by the proposed combination.
`
`1. Rathnam does not disclose an arbiter for selectively providing
`access for the first device and the decoder to the memory
`(“arbiter limitation”)
`
`Independent claim 1 recites an arbiter that selectively provides access by
`
`the first device and the decoder to the memory. The Petition identifies the central
`
`arbiter of Rathnam as corresponding to this limitation. Pet. at 35. However, at
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`best, the central arbiter of Rathnam controls access to the internal bus, not access
`
`to the SDRAM (i.e., the alleged memory).
`
`Rathnam discloses an “internal data bus” that connects “all internal blocks
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`together and provides access to internal control registers (in each on-chip
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`peripheral unit), external SDRAM, and external PCI bus.” Rathnam [Ex. 1005]
`
`at 15. Each of the peripherals can be a master or a slave on the internal bus. Id.
`
`Rathnam’s central arbiter has a request line from each potential bus master and
`
`controls “access to the internal bus.” Id. Peripheral units make requests to the
`
`arbiter “for bus access” and depending on the arbitration mode, “bus bandwidth
`
`is allocated” to the units in different amounts. Id. Accordingly, each mode of the
`
`central arbiter “allocates bandwidth” on the internal bus differently while
`
`
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`19
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`

`
`guaranteeing “a minimum bandwidth and maximum service latency.” Id.
`
`Therefore, Rathnam does not disclose an arbiter that controls access to the
`
`SDRAM (i.e., the alleged memory). Instead, the central arbiter of Rathnam
`
`controls access to the internal bus that connects many different components,
`
`including peripherals and the PCI bus together.
`
`Controlling access to a bus that connects multiple system components is
`
`not the same as controlling access to the SDRAM (i.e., the alleged memory). The
`
`distinction between accessing the bus and accessing the memory is evident from
`
`the disclosure of the `789 Patent which allows, for example, the video decoder to
`
`use part of the available bandwidth of the bus to access the shared memory while
`
`the remaining bus bandwidth remains available to other components. The `789
`
`Patent specification recognizes the benefit of controlling access to the memory as
`
`opposed to the memory bus. See, e.g., `789 Pat. [Ex. 1001], 7:10-22 (“In the
`
`preferred embodiment, even during decoding and encoding, the decoder/encoder
`
`80 does not always use the entire required bandwidth. Since the fast bus 70 has a
`
`bandwidth a little less than twice the size of the required bandwidth, the
`
`decoder/encoder 80 uses at most 60% of the bandwidth of the fast bus 70. … In
`
`the preferred embodiment the decoder/encoder typically will be using less than
`
`40% of the bandwidth of the fast bus 70. This frees up the remaining bandwidth
`
`
`
`20
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`

`
`to be used by the other devices with which the decoder/encoder 80 is sharing the
`
`memory 50”). By controlling access to the main memory, rather than the memory
`
`bus, embodiments of the `789 Patent allow multiple devices to use the bus even
`
`while only one device, e.g. the decoder, has access to the memory.
`
`Therefore, Rathnam’s alleged disclosure of a central arbiter that controls
`
`access to an internal bus does not satisfy the limitation of independent claim 1
`
`which recites an arbiter that controls access to the main/system memory.
`
`2. Rathnam does not disclose the bus having a sufficient bandwidth
`to enable the decoder to access the memory and operate in real
`time when the first device simultaneously accesses the bus (“real
`time limitation”)
`Independent claim 1 required that the shared bus have a sufficient
`
`bandwidth to enable the decoder to access the memory and operate in real time
`
`when the first device simultaneousl