Paper No. __
`Filed: September 22, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Samsung Electronics Co., Ltd., and
`Samsung Electronics America, Inc.
`Petitioners
`
`v.
`
`
`
`Parthenon Unified Memory Architecture LLC
`Patent Owner
`
`INTER PARTES REVIEW OF U.S. PATENT NO. 5,812,789
`Case IPR No.: To Be Assigned
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 5,812,789
`UNDER 35 U.S.C. §§ 311-19 AND 37 C.F.R. § 42.100 et seq.
`
`
`
`
`
`
`
`
`
`
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`
`TABLE OF CONTENTS
`
`
`
`IDENTIFICATION OF CHALLENGES UNDER 37 C.F.R.
`
`INTRODUCTION ........................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(b) .............................. 1
`III.
`PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a) .................................... 3
`IV. GROUNDS FOR STANDING ........................................................................ 3
`V.
`§§ 42.22 AND 42.104(b) ................................................................................. 3
`A.
`Statutory Grounds of Challenge ............................................................ 3
`B.
`The Proposed Grounds are Not Redundant ........................................... 5
`VI. THE ’789 PATENT ......................................................................................... 5
`VII. CLAIM CONSTRUCTION ............................................................................ 6
`A.
`Claim Terms To Be Construed .............................................................. 7
`1.
`“video decoder” ........................................................................... 7
`2.
`“real time” ................................................................................... 8
`B.
`Expiration of the ’789 Patent ................................................................ 9
`VIII. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 10
`IX. SPECIFIC GROUNDS OF CHALLENGE ................................................... 10
`A. Ground A: Lambrecht anticipates claims 1, 3, 5, 11, and
`13. ........................................................................................................ 10
`1.
`Claim 1 ...................................................................................... 10
`2.
`Claim 3 ...................................................................................... 19
`3.
`Claim 5 ...................................................................................... 20
`4.
`Claim 11 .................................................................................... 21
`5.
`Claim 13 .................................................................................... 22
`claim 4 ................................................................................................. 24
`1.
`Claim 4 ...................................................................................... 24
`claim 6 ................................................................................................. 26
`
`B.
`C.
`
`Ground B: Lambrecht in view of Artieri renders obvious
`
`Ground C: Lambrecht in view of Moore renders obvious
`
`i
`
`

`
`X.
`
`
`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`
`Ground E: Rathnam in view of Lambrecht and Moore
`
`Claim 6 ...................................................................................... 26
`1.
`D. Ground D: Rathnam in view of Lambrecht renders
`obvious claims 1, 3, 4, 5, and 11 ......................................................... 27
`1.
`Claim 1 ...................................................................................... 27
`2.
`Claim 3 ...................................................................................... 38
`3.
`Claim 4 ...................................................................................... 39
`4.
`Claim 5 ...................................................................................... 40
`5.
`Claim 11 .................................................................................... 41
`E.
`renders obvious claim 6 ....................................................................... 42
`1.
`Claim 6 ...................................................................................... 42
`F.
`Slavenburg renders obvious claim 13. ................................................ 44
`1.
`Claim 13 .................................................................................... 44
`CONCLUSION .............................................................................................. 48
`
`Ground F: Rathnam
`
`in view of Lambrecht and
`
`
`
`ii
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`
`TABLE OF AUTHORITIES
`
`
`
`Page(s)
`
`Federal Cases
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) .....................................................................................passim
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 10
`
`Parthenon Unified Memory Architecture LLC v. Apple, Inc.,
`No. 2:15-cv-00621-JRG-RSP (E.D. Tex) ............................................................. 2
`
`Parthenon Unified Memory Architecture LLC v. HTC Corp. et al.,
`No. 2:14-cv-00690-RSP (E.D. Tex.) .................................................................... 2
`
`Parthenon Unified Memory Architecture LLC v. Huawei Techs. Co.,
`Ltd. et al.,
`No. 2:14-cv-00687-JRG-RSP (E.D. Tex.) ............................................................ 1
`
`Parthenon Unified Memory Architecture LLC v. LG Elecs., Inc. et al.,
`No. 2:14-cv-00691-JRG-RSP (E.D. Tex.) ............................................................ 2
`
`Parthenon Unified Memory Architecture LLC v. Motorola Mobility,
`Inc.,
`No. 2:14-cv-00689-JRG-RSP (E.D. Tex.) ............................................................ 1
`
`Parthenon Unified Memory Architecture LLC v. Qualcomm Inc. et al.,
`No. 2:14-cv-00930-JRG-RSP (E.D. Tex.) ............................................................ 2
`
`Parthenon Unified Memory Architecture LLC v. Samsung Elecs. Co.,
`Ltd. et al.,
`No. 2:14-cv-00902-JRG-RSP (E.D. Tex.) ............................................................ 2
`
`Parthenon Unified Memory Architecture LLC v. ZTE Corp. et al.,
`No. 2:15-cv-00225-JRG-RSP (E.D. Tex.) ............................................................ 2
`
`In re Rambus, Inc.,
`694 F.3d 42 (Fed. Cir. 2012) ................................................................................ 9
`
`iii
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`
`STMicroelectronics, Inc. v. Motorola Inc. et al.,
`No. 4:03-cv-00276-LED (E.D. Tex.) .................................................................... 2
`
`Toyota Motor Corp. v. Hagenbuch,
`IPR2013-00483, Paper No. 37 (Dec. 5, 2014) .................................................... 10
`
`In re Translogic Tech., Inc.,
`504 F.3d 1249 (Fed. Cir. 2007) ............................................................................ 7
`
`In re Yamamoto,
`740 F.2d 1569 (Fed. Cir. 1984) ............................................................................ 7
`
`In re Zletz,
`13 USPQ2d 1320 (Fed. Cir. 1989) ....................................................................... 6
`
`Federal Statutes
`
`35 U.S.C. 102(a) ........................................................................................................ 4
`
`35 U.S.C. 102(b) ........................................................................................................ 5
`
`35 U.S.C. 102(e) ................................................................................................ 3, 4, 5
`
`35 U.S.C. § 103 .................................................................................................passim
`
`35 U.S.C. § 112 .......................................................................................................... 6
`
`35 U.S.C. § 311 ........................................................................................................ 48
`
`Regulations
`
`37 C.F.R. § 42.8(b) .................................................................................................... 1
`
`37 C.F.R. § 42.15(a) ................................................................................................... 3
`
`37 C.F.R. § 42.22 ....................................................................................................... 3
`
`37 C.F.R. § 42.101 ................................................................................................... 48
`
`37 C.F.R. § 42.104(a) ................................................................................................. 3
`
`37 C.F.R. § 42.104(b) ................................................................................................ 3
`
`77 Fed. Reg. 48,756 (Aug. 14, 2012) ........................................................................ 7
`
`iv
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`LIST OF EXHIBITS
`
`Ex. 1004
`
`ISO/IEC 11172-2: 1993: Information technology—Coding of moving
`pictures and associated audio for digital storage media at up to about
`1,5 Mbit/s Part 2: Video,” (1“ ed. August 1, 1993) (“MPEG
`Standarcf’)
`
`S. Rathnam et al., “An Architectural Overview of the Programmable
`Multimedia Processor, TM-1,” IEEE Proceedings of COMPCON ’96,
`pp. 319-326 (1996) (“Rathnam”)
`
`R.J. Gove, “The MVP: A Highly-Integrated Video Compression
`Chip,” Proceedings of the IEEE Data Compression Conference (DCC
`‘94), pp. 215-224 (March 29-31, 1994).
`
`Ex. 1007 U.S. Patent No. 5,774,676 (“Stearns”)
`Ex 1008
`Ex- 1009
`Ex. 1010 WorldCat Entry for Rathnam
`
`Ex. 1011
`
`Patent Owner Claim Construction Brief in Case No. 2: 14-cv-690,
`April 7, 2015
`
`Ex. 1012
`
`Patent Owner Claim Construction Brief in Case No. 2: 14-cv-902, June
`
`Ex. 1019
`
`Shanley, et al., “PCI System Architecture,” Addison-Wesley
`Publishing Company, 1995 (3rd ed.) (“Shanley”)
`
`Ex. 1020
`
`Stone, H., “Microcomputer Interfacing,” Addison-Wesley Publishing
`Company, 1982
`
`

`
`Petition for Inter Partes Review of U_S_ Pat. No. 5,812,789
`
`Ex. 1024
`
`“Accelerated Graphics Port Interface Specification,” Intel
`Corporation, July 31, 1996 (Revision 1.0) (“AG ”)
`
`Ex. 1025 VESA Unified Memory Architecture Hardware Specifications
`Proposal,” Version 1_0p (“VUJMA”)
`
`Ex. 1032 U_S. Patent No. 5,682,484 (“Lambrecht”)
`
`Ex. 1033 Reserved
`
`Ex_ 1034
`
`Slavenburg, G., “The TriMedia VLIW—Based PCI Multimedia
`Processor,” Microprocessor Forum 1995, Oct. 10-11, 1995
`5,
`I
`
`Ex_ 1035 G. Moore, “ramming more components onto integrated circuits,”
`Electronics, Vol. 38, No. 8, Ar. 19, 1965
`
`vi
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`
`I.
`
`INTRODUCTION
`Petitioners1 respectfully request inter partes review of claims 1, 3-6, 11 and
`
`13 (the “Challenged Claims”) of U.S. Patent No. 5,812,789 (“the ’789 patent”)
`
`(Ex. 1001). This Petition shows that there is a reasonable likelihood that Petitioner
`
`will prevail on the Challenged Claims of the ’789 patent based on prior art that was
`
`not considered during prosecution. This Petition also shows by a preponderance of
`
`the evidence that the prior art anticipates or renders obvious the Challenged Claims
`
`of the ’789 patent. The Challenged Claims of the ’789 patent should be found
`
`unpatentable and cancelled.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(b)
`Real Party-in-Interest: The real parties-in-interest are Samsung Electronics
`
`Co., Ltd. and Samsung Electronics America, Inc.
`
`Related Matters: The following would affect, or be affected by, a decision in
`
`this proceeding:
`
`1.
`
`U.S. district court actions in which Patent Owner asserted the ’789
`
`patent: Parthenon Unified Memory Architecture LLC v. Huawei Techs. Co., Ltd. et
`
`al., No. 2:14-cv-00687-JRG-RSP (E.D. Tex.); Parthenon Unified Memory
`
`Architecture LLC v. Motorola Mobility, Inc., No. 2:14-cv-00689-JRG-RSP (E.D.
`
`1 “Petitioners” refers collectively to Samsung Electronics Co., Ltd. and Samsung
`
`Electronics America, Inc.
`
`-1-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`
`Tex.); Parthenon Unified Memory Architecture LLC v. HTC Corp. et al., No. 2:14-
`
`cv-00690-RSP (E.D. Tex.); Parthenon Unified Memory Architecture LLC v. LG
`
`Elecs., Inc. et al., No. 2:14-cv-00691-JRG-RSP (E.D. Tex.); Parthenon Unified
`
`Memory Architecture LLC v. Samsung Elecs. Co., Ltd. et al., No. 2:14-cv-00902-
`
`JRG-RSP (E.D. Tex.); Parthenon Unified Memory Architecture LLC v. Qualcomm
`
`Inc. et al., No. 2:14-cv-00930-JRG-RSP (E.D. Tex.); Parthenon Unified Memory
`
`Architecture LLC v. ZTE Corp. et al., No. 2:15-cv-00225-JRG-RSP (E.D. Tex.);
`
`and Parthenon Unified Memory Architecture LLC v. Apple, Inc., No. 2:15-cv-
`
`00621-JRG-RSP (E.D. Tex).
`
`2.
`
`STMicroelectronics, Inc. v. Motorola Inc. et al., No. 4:03-cv-00276-
`
`LED (E.D. Tex.), in which Patent Owner’s predecessor-in-interest asserted U.S.
`
`Patent No. 5,812,789.
`
`Petitioners have been involved in the filing of inter partes review petitions
`
`against five related patents: U.S. Patent Nos. 7,321,368 (IPR2015-01500);
`
`7,777,753 (IPR2015-01501); 7,542,045 (IPR2015-01502); 8,054,315 (IPR2015-
`
`01494); and 8,681,164 (IPR2015-01503). In addition, concurrent with the filing of
`
`this Petition, Petitioners are filing an inter partes review petition against another
`
`related patent: U.S. Patent No. 5,960,464.
`
`Lead and Back-Up Counsel and Service Information: Lead counsel is Allan
`
`M. Soobert (Reg. No. 36,284), and back-up counsel is Naveen Modi (Reg. No.
`
`-2-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`46,224). Service information is Paul Hastings LLP, 875 15th Street NW,
`
`Washington, DC 20005, Telephone: 202-551-1700, Fax: 202-551-1705, E-mail:
`
`Samsung-PUMA-IPR@paulhastings.com. Petitioners consent to electronic service.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`The required fees are submitted herewith. The PTO is authorized to charge
`
`any additional fees due at any time during this proceeding to Deposit Account No.
`
`50-2613.
`
`IV. GROUNDS FOR STANDING
`Petitioners certify that, under 37 C.F.R. § 42.104(a), the ’789 patent is
`
`available for inter partes review, and that Petitioners are not barred or estopped
`
`from requesting inter partes review of the ’789 patent on the grounds identified.
`
`V.
`
`IDENTIFICATION OF CHALLENGES UNDER 37 C.F.R. §§ 42.22
`AND 42.104(b)
`A.
`The Challenged Claims are unpatentable on the following grounds:
`
`Statutory Grounds of Challenge
`
`Ground A. Under pre-AIA 35 U.S.C. § 102(e), Lambrecht (Ex. 1032) anticipates
`
`claims 1, 3, 5, 11 and 13 (see Section IX.A).
`
`Ground B. Under pre-AIA 35 U.S.C. § 103, Lambrecht (Ex. 1032) in view of
`
`Artieri (Ex. 1036) renders obvious claim 4 (see Section IX.B).
`
`-3-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`Ground C. Under pre-AIA 35 U.S.C. § 103, Lambrecht (Ex. 1032) in view of
`
`Moore (Ex. 1035) renders obvious claim 6 (see Section IX.C).
`
`Ground D. Under pre-AIA 35 U.S.C. § 103, Rathnam (Ex. 1005) in view of
`
`Lambrecht (Ex. 1032) renders obvious claims 1, 3-5, 11 (see Section
`
`IX.D).
`
`Ground E. Under pre-AIA 35 U.S.C. § 103, Rathnam (Ex. 1005), in view of
`
`Lambrecht (Ex. 1032) and Moore (Ex. 1035), renders obvious claim 6
`
`(see Section IX.E).
`
`Ground F. Under pre-AIA 35 U.S.C. § 103, Rathnam (Ex. 1005), in view of
`
`Lambrecht (Ex. 1032) and Slavenburg (Ex. 1034), renders obvious
`
`claim 13 (see Section IX.F).
`
`Lambrecht was filed on November 20, 1995, and thus qualifies as prior art at
`
`least under pre-AIA 35 U.S.C. 102(e). Rathnam was published during the IEEE
`
`COMPCON ’96 Conference in February 1996 (see Ex. 1005 at 3), was available at
`
`the Library of Congress at least as of April 4, 1996 (see id. at 6), and was indexed
`
`in the WorldCat library database on April 23, 1996 (Ex. 1010). Therefore,
`
`Rathnam qualifies as prior art at least under pre-AIA 35 U.S.C. 102(a). Slavenburg
`
`was published in October 1995, during the 8th Annual Microprocessor Forum
`
`Conference (see Ex. 1034 at 1-2), and thus qualifies as prior art at least under pre-
`
`AIA 35 U.S.C 102(a). Artieri was filed on May 24, 1994, and thus qualifies as
`
`-4-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`prior art at least under pre-AIA 35 U.S.C. 102(e). Moore was published in
`
`Electronics, Vol. 38, No. 8, on April 19, 1965, and thus qualifies as prior art at
`
`least under pre-AIA 35 U.S.C. 102(b).
`
`The Proposed Grounds are Not Redundant
`
`B.
`Grounds A-C and Grounds D-F both challenge claims 1, 3-6, 11 and 13 of
`
`the ’789 patent. However, the grounds are not redundant because of several
`
`significant differences. For example, the primary references applied, Lambrecht
`
`(Ex. 1032) for Grounds A-C and Rathnam (Ex. 1005) for Grounds D-F, address the
`
`claimed “real time” operation, “memory interface,” and “decoder” in different
`
`ways. Also Lambrecht has a chipset that Rathnam does not have, which affects the
`
`mapping to the claimed elements. Therefore, for at least these reasons, Petitioners
`
`respectfully request the Board adopt all proposed Grounds in this Petition,
`
`particularly because not adopting one of the grounds may affect how Petitioners
`
`later challenge the validity of the ’789 patent.
`
`VI. THE ’789 PATENT
`The ’789 patent, entitled “Video and/or Audio Decompression and/or
`
`Compression Device that Shares a Memory Interface,” was filed August 26, 1996
`
`and issued September 22, 1998. The ’789 patent concerns arbitrating access to a
`
`memory shared between a decoder and another device. See Ex. 1001, Abstract.
`
`Conventionally, the ’789 patent alleges, a video decoder would have its own
`
`-5-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`dedicated memory to allow it to operate in real time, which would remain unused
`
`most of the time and significantly increase costs. See id., 2:29-35, 3:50-59. The
`
`’789 patent proposes having a video decoder share memory with other devices. See
`
`id., 5:15-37. The ’789 patent accomplishes this using an arbiter, which arbitrates
`
`between the video decoder and another device when one of them requests access to
`
`the shared memory. See id., 6:15-23.
`
`But by the ’789 patent’s priority date, others had solved the same problem of
`
`a dedicated memory using the same arbitration scheme. See Ex. 1030, Stone Decl.
`
`at ¶¶ 36-66 (discussing Exs. 1004, 1007, 1019, 1020, 1023, 1024, 1025). None of
`
`the references applied below was considered during prosecution of the ’789 patent.
`
`(See, e.g., Ex. 1001, 1 (References Cited); see generally Ex. 1002.)
`
`VII. CLAIM CONSTRUCTION
`inter partes review,
`In
`the Board applies the broadest reasonable
`
`interpretation (“BRI”) standard to construe claim terms of an unexpired patent.2
`
`
`2 Because the standards applied in litigation differ from PTO proceedings, any
`
`interpretation of claim terms herein is not binding upon Petitioners in any related
`
`litigation. See In re Zletz, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989). Petitioners
`
`reserve their rights to make all arguments in the district court with respect to claim
`
`construction and on other grounds (e.g., 35 U.S.C. § 112).
`
`-6-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`Under the BRI standard, terms are given their “broadest reasonable interpretation,
`
`consistent with the specification.” In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir.
`
`1984); Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,764 (Aug. 14,
`
`2012). Claim terms are “generally given their ordinary and customary meaning,”
`
`which is the meaning that the term would have to a person of ordinary skill in the
`
`art. See In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007) (quoting
`
`Phillips v. AWH Corp., 415 F.3d 1303, 1312, 1313 (Fed. Cir. 2005) (en banc)).
`
`A. Claim Terms To Be Construed
`For purposes of this proceeding only, Petitioners propose BRI constructions
`
`for the following terms. All remaining terms should be given their plain meaning.
`
`“video decoder”
`
`1.
`Proposed BRI Construction: “hardware and/or software that translates data
`
`streams into video information”
`
`The term “video decoder” appears in claim 3. The ’789 patent generally
`
`refers to a decoder as a “video and/or audio decompression device.” Ex. 1001,
`
`1:46-51. According to the specification, “[a]ny conventional decoder including a
`
`decoder complying to the MPEG-1, MPEG-2, H.261, or H.261 standards, or any
`
`combination of them, or any other conventional standard can be used as the
`
`decoder/encoder.” Id., 12:23-27 (emphasis added). A conventional decoder around
`
`the time of the alleged invention of the ’789 patent was understood to include “any
`
`-7-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`hardware or software system that translates data streams into video or audio
`
`information.” Ex. 1014, 3.
`
`Consistent with
`
`this understanding of a decoder,
`
`the ’789 patent
`
`acknowledges that a decoder can be implemented as hardware or software. See,
`
`e.g., Ex. 1001, 5:43-45. In one example, the specification explains that video
`
`decoding can be performed by hardware and audio decoding can be performed by
`
`software. Id., 5:50-56.
`
`Therefore,
`
`consistent with
`
`the
`
`’789
`
`patent
`
`specification
`
`and
`
`contemporaneous dictionary definitions, the BRI of the term “video decoder” is
`
`“hardware and/or software that translates data streams into video information.”
`
`“real time”
`
`2.
`The term “real time” appears in independent claim 1. The ’789 patent and its
`
`related patents disclose that both bandwidth and latency are factors to consider as
`
`to whether a bus may operate in “real time” (see Ex. 1001, 3:13-21; Ex. 1015,
`
`7:59-8:2). Moreover, patents related to the ’789 patent describe that a PCI bus is an
`
`example of a real time bus (see Ex. 1015, 5:36-43, 8:13-21). In contrast, during
`
`prosecution of U.S. Patent No. 8,681,164 (“the ’164 patent”), which is related to
`
`the ’789 patent (see Ex. 1015 at 1:28-37), Applicants argued (1) a bus’s latency,
`
`irrespective of bandwidth, determines whether a bus satisfies a “real time”
`
`requirement, and, as a result, (2) a PCI bus does not satisfy a “real time”
`
`-8-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`requirement. Ex. 1016 at 8; see also Microsoft Corp. v. Multi-Tech Sys., Inc., 357
`
`F.3d 1340, 1350 (Fed. Cir. 2004) (finding an applicant’s statement to the USPTO
`
`in a later application is relevant to the scope of the claimed invention in an earlier
`
`issued patent); In re Katz Interactive Call Processing Patent Litig., 639 F.3d 1303,
`
`1325 (Fed. Cir. 2011).
`
`The discrepancy between the description of “real time” in the ’789 patent
`
`and the prosecution history of the ’164 patent would have caused one of ordinary
`
`skill in the art not to be informed, with reasonable certainty, about the scope of a
`
`bus that satisfies the “real time” requirement. Nautilus, Inc. v. Biosig Instruments,
`
`Inc., 134 S. Ct. 2120, 2123 (2014).
`
`In related litigation, Patent Owner has argued that the term “real time”
`
`means “fast enough to keep up with an input data stream.” (Ex. 1011 at 18; Ex.
`
`1012 at 16.) Therefore, while Petitioners submit that claim 1’s recitation of “real
`
`time” is indefinite, Petitioners have applied Patent Owner’s interpretation of “real
`
`time” when applying the prior art to claim 1.
`
`Expiration of the ’789 Patent
`
`B.
`In addition to the BRI analysis above, Petitioners recognize that the ’789
`
`patent appears set to expire in August 2016, which will be subsequent to the
`
`requested institution of trial in this proceeding, but may precede a final decision. In
`
`such cases, the Board has held (citing In re Rambus, Inc., 694 F.3d 42, 46 (Fed.
`
`-9-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`Cir. 2012)), that it will construe patent claims, once expired, according to the
`
`standard applied by the district courts by applying the principles set forth in
`
`Phillips, 415 F.3d at 1312. See, e.g., Toyota Motor Corp. v. Hagenbuch, IPR2013-
`
`00483, Paper No. 37 at 5 (Dec. 5, 2014). Petitioners respectfully submit that this
`
`change in standards would not affect any of the proposed grounds in this Petition,
`
`especially in view of Patent Owner’s interpretations of the claims under the
`
`Phillips standard.
`
`VIII. LEVEL OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art at the time of the alleged invention of
`
`the ’789 patent would have had an accredited Bachelor’s degree in Electrical
`
`Engineering and/or Computer Science and/or Computer Engineering and had three
`
`years’ experience in the fields of data compression and overall computer system
`
`architecture. This person would have been capable of understanding and applying
`
`the prior art references described herein. Ex. 1030, ¶¶ 74-77.
`
`IX. SPECIFIC GROUNDS OF CHALLENGE
`A. Ground A: Lambrecht anticipates claims 1, 3, 5, 11, and 13.
`Claim 1
`
`1[pre]: “An electronic system coupled to a memory, comprising:”
`
`Lambrecht discloses an electronic system coupled to a memory. See, e.g.,
`
`1.
`a.
`
`Ex. 1032, Lambrecht at Fig. 21 (annotated below); see also id. at 27:4-9, 26:51-56
`
`-10-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`(“The computer system of FIG. 21 is similar to the computer system of FIG. 1.
`
`However, the mode logic in the computer system of FIG. 21 is operable to place
`
`the PCI bus 120 in either a normal PCI mode or in a real-time/multimedia mode
`
`optimized for multimedia transfers of periodic data.”); see also Ex. 1030, Stone
`
`Decl. ¶ 78.
`
`
`
`In particular, Lambrecht teaches an electronic system that includes a CPU,
`
`chipset, and various multimedia devices. See id. A dynamic random access
`
`memory (DRAM) acts as main memory and is coupled to the electronic system.
`
`See, e.g., id. at 27:4-9 (“The bridge or chipset 106 couples through a memory bus
`
`108 to main memory 110. The main memory 110 is preferably DRAM (dynamic
`
`random access memory) or EDO (extended data out) memory, or other types of
`
`memory, as desired. The chipset logic 106 preferably includes a memory controller
`
`-11-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`for interfacing to the main memory 110.”), Fig. 21; see also Ex. 1030, Stone Decl.
`
`¶ 78; analysis and citations below for other claim elements.
`
`b.
`
`1[a]: “a first device that requires access to the memory;”
`
`Lambrecht discloses this limitation. See, e.g., Ex. 1032 at Fig. 21; 27:4-9;
`
`see also Ex. 1030, Stone Decl. ¶ 78. In particular, Lambrecht discloses a first
`
`device that requires access to the memory. See, e.g., Ex. 1032, Fig. 21 (annotated
`
`below), 27:32-34 (“One or more multimedia devices or multimedia devices 142D,
`
`144D, and 146D are coupled to each of the PCI bus 120 and the multimedia bus
`
`130.”) (emphasis added).
`
`Lambrecht adds:
`
`
`
`“The multimedia devices 142D-146D may be any of
`various
`types of
`input/output devices,
`including
`multimedia devices and communication devices, as
`described above. The multimedia devices 142D-146D are
`preferably similar to the multimedia devices 142-146
`
`-12-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`
`described above, except that the interface logic 962 in the
`multimedia devices 142D-146D each
`include
`the
`interface logic for interfacing to the PCI bus 120 in
`multiple modes. As described above, the multimedia
`devices 142D-146D may comprise video accelerator or
`graphics accelerator cards, video playback cards, MPEG
`decoder cards, sound cards, network interface cards,
`SCSI adapters for interfacing to various input/output
`devices, such as CD-ROMS and tape drives, or other
`devices as desired.”
`
`See id. at 27:43-56 (emphasis added). The first device disclosed in Lambrecht
`
`requires access to memory. See id. at 27:57-59 (“Thus, the multimedia devices
`
`142D-146D communicate with each other and with the CPU 102 and main
`
`memory 110 via the PCI bus 120, as is well known in the art.”).
`
`c.
`
`1[b]: “a decoder that requires access to the memory sufficient to
`maintain real time operation; and”
`
`Lambrecht discloses this limitation. See, e.g., Ex. 1032 at Fig. 21 (annotated
`
`below), 27:32-34 (“One or more multimedia devices or multimedia devices 142D,
`
`144D, and 146D are coupled to each of the PCI bus 120 and the multimedia bus
`
`130.”) (emphasis added); see also Ex. 1030, Stone Decl. ¶ 78.
`
`-13-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`
`Lambrecht describes that one of the several multimedia devices is a decoder:
`
`
`
`“The multimedia devices 142D-146D may be any of
`various
`types of
`input/output devices,
`including
`multimedia devices and communication devices, as
`described above. The multimedia devices 142D-146D are
`preferably similar to the multimedia devices 142-146
`described above, except that the interface logic 962 in the
`multimedia devices 142D-146D each
`include
`the
`interface logic for interfacing to the PCI bus 120 in
`multiple modes. As described above, the multimedia
`devices 142D-146D may comprise video accelerator or
`graphics accelerator cards, video playback cards, MPEG
`decoder cards, sound cards, network interface cards,
`SCSI adapters for interfacing to various input/output
`devices, such as CD-ROMS and tape drives, or other
`devices as desired.”
`
`-14-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`See id. at 27:43-56 (emphasis added). In other words, Lambrecht discloses an
`
`arrangement in which multimedia device 144D is a decoder (i.e., an MPEG
`
`decoder card). See id.
`
`The decoder disclosed in Lambrecht requires access to memory. See id. at
`
`27:57-59 (“Thus, the multimedia devices 142D-146D communicate with each
`
`other and with CPU 102 and main memory 110 via the PCI bus 120, as is well
`
`known in the art.”). The memory access is sufficient to operate in real time. See id.
`
`at 27:66-28:2 (“In the preferred embodiment of the invention of FIG. 21, the
`
`multimedia mode comprises placing the system bus or PCI bus 120 in a special
`
`mode optimized for real-time data transfers.”); see also id. at 5:33-48, 26:48-63;
`
`Ex. 1030, Stone Decl. ¶ 78.
`
`d.
`
`1[c]: “a memory interface for coupling to the memory, and coupled to
`the first device and to the decoder, the memory interface having an
`arbiter for selectively providing access for the first device and the
`decoder to the memory and a shared bus coupled to the memory the
`first device, and the decoder, the bus having a sufficient bandwidth to
`enable the decoder to access the memory and operate in real time when
`the first device simultaneously accesses the bus.”
`Lambrecht discloses this limitation. See, e.g., Ex. 1032 at Fig. 21 (annotated
`
`below); see also Ex. 1030, Stone Decl. ¶ 78.
`
`-15-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`
`
`
`Lambrecht’s chipset is a memory interface that has an arbiter. See, e.g., Ex.
`
`1032 at 7:45-47 (“The chipset logic 106 preferably includes a memory controller
`
`for interfacing to the main memory 110 and also includes the arbitration logic
`
`107.”); see also id., 26:66-27:2. Lambrecht discloses the memory interface is
`
`coupled to memory, the first device, and the decoder:
`
`As shown, the computer system includes a central
`processing unit (CPU) 102 which is coupled through a
`CPU local bus 104 to a host/PCI/cache bridge or chipset
`106. The chipset 106 includes various bridge logic and
`includes arbitration logic 107. The chipset 106 is
`preferably similar to the Triton chipset available from
`Intel Corporation, including certain arbiter modifications
`to accommodate
`the real-time bus of
`the present
`invention. A second level or L2 cache memory (not
`shown) may be coupled to a cache controller in the
`chipset 106, as desired. The bridge or chipset 106 couples
`
`-16-
`
`

`
`Petition for Inter Partes Review of U.S. Pat. No. 5,812,789
`
`
`through a memory bus 108 to main memory 110. The
`main memory 110 is preferably DRAM (dynamic random
`access memory) or EDO (extended data out) memory, or
`other types of memory, as desired. The chipset logic 106
`preferably includes a memory controller for interfacing
`to the main memory 110 and also includes the arbitration
`logic 107.
`
`See id. at 7:30-47 (emphasis added); see also id. at 26:66-27:9, Fig. 21
`
`(annotated above); Ex. 1030, Stone Decl. ¶ 78.
`
`The memory interface (i.e. the chipset) includes an arbiter that “selectively
`