Samsung Exhibit 1032
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`Page 6 of 42
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`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 6 of 25
`
`5,682,484
`
`Oo 0
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`Page 7 of 42
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`Page 8 of 42
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`

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`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 8 of 25
`
`5,682,484
`
`©.O_u._
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`Page 9 of 42
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`Page 9 of 42
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`Page 18 of 42
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`5,682,484
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`Page 19 of 42
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`Page 20 of 42
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`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 20 of 25
`
`5,682,484
`
`MULTIMEDIA MEMORY
`ADDRESS SPACE
`
`GENERAL
`
`ADDRESS
`SPACE
`
`GENERAL
`ADDRESS
`SPACE
`
`FIG. 17
`
`Page 21 of 42
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`Page 21 of 42
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`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 21 of 25
`
`5,682,484
`
`502
`
`504
`
`505
`
`508
`
`510
`
`512
`
`514-
`
`516
`
`CPU TRANSFERS
`MULTIMEDIA DATA
`TO_MA|N MEMORY
`
`CPU TRANSFERS
`DATA STRUCTURE TO
`DMA ENGINE
`
`DMA ENGINE PR|0R|'I1ZES
`DATA STRUCTURE
`IN COMMAND QUEUE
`
`DMA ENGINE
`ARBITRATES FOR
`MAIN MEMORY
`
`DMA ENGINE
`TRANSFERS MULTIMEDIA
`DATA FROM MAIN MEMORY
`T0 MULTIMEDIA MEMORY
`
`MULTIMEDIA DEVICE
`ACCESSES MUL'I1MEDIA
`DATA FROM
`
`MULTIMEDIA MEMORY
`
`MULTIMEDIA ENGINE
`PERFORMS OPERATIONS
`USING MULTIMEDIA DATA
`
`MULTIMEDIA ENGINE
`GENERATES MULTIMEDIA
`°”"°”Ts
`
`FIG. 18
`
`Page 22 of 42
`
`Page 22 of 42
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`

`
`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 22 of 25
`
`5,682,484
`
`3
`
`SH
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`22:
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`Page 23 of 42
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`Page 23 of 42
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`

`
`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 23 of 25
`
`5,682,484
`
`902
`
`/
`
`PCI EXPANSION
`BUS INTERFACE
`
`MEMORY
`DATA
`CHANNEL
`INTERFACE
`
`FIG. 20
`
`Page 24 of 42
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`Page 24 of 42
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`

`
`U.S. Patent
`
`2
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`7
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`Page 25 of 42
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`Page 25 of 42
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`

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`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 25 of 25
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`5,682,484
`
`1 42D
`
`5
`
`PCI EXPANSION
`PC] ExpAN3|0N BUS MULTIMEDIA
`Bug NTERFA
`MODE INTERFACE
`CE
`LOGIC
`
`FIG. 22
`
`Page 26 of 42
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`Page 26 of 42
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`

`
`1
`SYSTEM AND METHOD FOR
`TRANSFERRING DATA STREAMS
`SIMULTANEOUSLY ON MULTIPLE BUSES
`IN A COMPUTER SYSTEM
`
`5,682,484
`
`2
`
`hardware devices are generally required to share bus usage
`with non-real time devices.
`
`Also, multimedia hardware devices generally do not make
`eflicient usage of system resources. As an example, multi-
`media hardware cards typically include their own memory in
`addition to system memory. For example, video accelerator
`cards are typically configured with one to four Megabytes of
`video RAM. Audio cards, video capture cards, and other
`multimedia cards are also generally configured with dedi-
`cated on-board memory. This requirement of additional
`memory adds undesirable cost to the system.
`As multimedia applications become more prevalent, mul-
`timedia hardware will correspondingly become essential
`components in personal computer systems. Therefore, an
`improved computer system architecture is desired which is
`optimized for real-time multimedia and communications
`applications as well as for non-realtime applications. In
`addition,
`improved methods are desired for transferring
`real-time data between multimedia devices.
`
`Applicant is aware of two new graphics standards from
`the Video Electronics Standards Association (VESA) which
`are designed to improve digital video transfers in computer
`systems. These two standards are referred to as the VESA
`advanced feature connector (VAFC) and the VESA media
`channel (VMC). Athird standard has been proposed by Intel
`and ATI referred to as the shared frame buffer interconnect
`(SFBI).
`The VAFC standard is a 32 bit replacement for prior 8 bit
`VGA connectors which supports video at much higher
`resolutions and in better color. The VMC standard also oifers
`a 32 data path and supports up to 15 video streams simul-
`taneously. The VMC standard comprises a dedicated chan-
`nel for real-time video, and peripherals can communicate
`independently Without slowing the system CPU. The VMC
`standard also decouples the memory subsystem from the
`video transfer specification, allowing graphics board manu-
`facturers to offer a variety of boards with differing types of
`graphics memory.
`The SFBI standard combines frame buffers and memory
`use by each multimedia system into a single shared memory
`pool. The SFBI standard also includes a protocol for arbi-
`trating among devices attempting to access the memory.
`However, one drawback to this standard is that the standard
`is designed to maintain all of the components on a single
`board. The SFBI standard does not provide an external
`feature connector unless SFBI cards are connected to
`another device over the host bus. In addition, SFBI cards can
`include a VMC or VAFC connector for connecting to a VMC
`or VAFC card.
`
`SUMMARY OF THE INVENTION
`
`The present invention comprises a computer system and
`method optimized for real-time applications which provides
`increased performance over current computer architectures.
`The system preferably includes a standard local expansion
`bus or system bus, such as the PCI bus, and also includes a
`dedicated real-time bus or multimedia bus. Thus multimedia
`devices, such as video devices, audio devices, etc., as well
`as communications devices, transfer real-time data through
`a separate bus without requiring arbitration for or usage of
`the PCI bus. The computer system of the present invention
`thus provides much greater performance for real-time appli-
`cations than prior systems. In an alternate embodiment, the
`computer system only includes one or more dedicated
`real-time buses which replace the PCI bus.
`In the preferred embodiment. the computer system com-
`prises a CPU coupled through chip set or bridge logic to
`
`FIELD OF THE INVENTION
`
`The present invention relates to a computer system which
`includes a system expansion bus such as the Peripheral
`Component Interconnect (PCI) bus and also includes a
`separate real-time or multimedia bus which transfers peri-
`odic and/or multimedia stream data for increased system
`performance for multimedia and real-time applications.
`
`DESCRIPTION OF THE RELATED ARI‘
`
`Computer architectures generally include a plurality of
`devices interconnected by one or more various buses. For
`example, modern computer systems typically include a CPU
`coupled through bridge logic to main memory. The bridge
`logic also typically couples to a high bandwidth local
`expansion bus or system expansion bus, such as the periph-
`eral component interconnect (PCI) bus or the VESA (Video
`Electronics Standards Association) VL bus. Examples of
`devices which can be coupled to local expansion buses
`include video accelerator cards, audio cards,
`telephony
`cards, SCSI adapters, network interface cards, etc. An older
`type expansion bus is generally coupled to the local expan-
`sion bus for compatibility. Examples of such expansion
`buses included the industry standard architecture (ISA) bus,
`also referred to as the AT bus, the extended industry standard
`architecture (EZISA) bus, or the microchannel architecture
`(MCA) bus. Various devices may be coupled to this second
`expansion bus, including a fax/modern, sound card, etc.
`Personal computer systems were originally developed for
`business applications such as word processing and
`spreadsheets. among others. However, computer systems are
`currently being used to handle a number of real time
`applications,
`including multimedia applications having
`video and audio components, video capture and playback.
`telephony applications, and speech recognition and
`synthesis, among others. These real time applications typi-
`cally require a large amount of system resources and band-
`width.
`
`One problem that has arisen is that computer systems
`originally designed for business applications are not well
`suited for the real-time requirements of modem multimedia
`applications. For example, modem personal computer sys-
`tem architectures still presume that the majority of applica-
`tions executing on the computer system are non real-time
`business applications such as word processing and/or
`spreadsheet applications, which execute primarily on the
`main CPU. In general, computer systems have not tradition-
`ally been designed with multimedia hardware as part of the
`system, and thus the system is not optimized for multimedia
`applications. Rather, multimedia hardware is typically
`designed as an add-in card for optional insertion in an
`expansion bus of the computer system, wherein the expan-
`sion bus is designed for non-realtime applications.
`In many cases, multimedia hardware cards situated on an
`expansion bus do not have the required system bus band-
`width or throughput for multimedia data transfers. For
`example, a multimedia hardware card situated on the PCI
`expansion bus must first arbitrate for control of the PCI bus
`before the device can begin a data transfer or access the
`system memory. In addition, since the computer system
`architecture is not optimized for multimedia, multimedia
`
`10
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`

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`5,682,484
`
`3
`main memory. The bridge logic couples to a local bus such
`as the PCI bus. The computer system also includes a
`real-tirne expansion bus or multimedia bus for transferring
`real-time or multimedia data. A plurality of multimedia
`devices. such video devices, audio devices, MPEG encoders
`and/or decoders, and/or communications devices, are
`coupled to each of the PCI bus and the multimedia bus. In
`one embodiment, the multimedia bus transfers only periodic
`stream data, such as audio data at 44,100 samples per
`second, video data at 30 frames per second, or real-time
`communication streams at rates dependent on the transport
`media.
`
`The computer system preferably includes a plurality of
`PCI expansion bus connector slots connected to the PCI bus
`for receiving add-in devices, and also preferably comprises
`one or more multimedia bus connector slots corresponding
`to respective ones of the PCI expansion bus connector slots.
`Thus, in one embodiment, the PCI bus and the multimedia
`bus are comprised on the motherboard and include respec-
`tive connector slots for receiving add-in cards. Multimedia
`device expansion cards each include two connectors which
`correspond to the PCI bus and the multimedia bus.
`Alternatively, the multimedia devices are comprised directly
`on the motherboard and connect directly to the PCI bus and
`the multimedia bus, and connector slots are not used.
`In one embodiment, the multimedia bus comprises pri-
`marily or only data lines.
`In this embodiment, control
`information for the periodic stream transfers is transferred
`on the PCI bus by a sourcing device, or is transferred by the
`CPU to the bridge logic. Thus multimedia data transfers
`initially involve the transfer of control or setup information
`on the PCI bus, or transfer of control or setup information by
`the CPU, to set up the transfer. This transfer of control
`information is followed by the transfer of the periodic data
`streams on the multimedia bus. Alternatively, once control!
`setup information has been used to set up the transfer, the
`periodic data stream may occupy both the PCI data lines and
`the multimedia bus for increased data throughput. In this
`embodiment, the transferring or source device transfers a
`multiple bus transfer request which requests simultaneous
`transfers on both the PCI bus and the multimedia bus. If the
`
`multiple bus transfer request is accepted, then the source
`device transfers data on both the PCI bus and the multimedia
`bus.
`
`invention further includes an improved
`The present
`method for transferring periodic data streams on a bus in the
`computer system, such as periodic video streams or periodic
`audio streams. According to this method, the transferring
`device first transmits addressing and control information to
`set up the transfer. The transferring device then transmits a
`periodic transfer data request to the receiving device. The
`periodic transfer data request includes information regarding
`the frequency and amount of the periodic transfers. The
`receiving device detennines if it can guarantee availability at
`the periodic time frequencies requested by the transferring
`device. If the receiving device indicates availability for the
`periodic transfers. the transferring device sets a periodic
`transfer flag. The transferring device then perfonns the
`periodic transfers to the receiving device at the specified
`time frequency. If the receiving device does not indicate
`availability for the periodic transfers. the transferring device
`performs only a single transfer and is required to transfer
`control information at the beginning of each subsequent
`periodic transfer.
`In a second embodiment. the computer system includes a
`dedicated control channel separate from the PCI bus and the
`multimedia bus for transferring control
`information for
`
`4
`multimedia bus data transfers. The control channel is pref-
`erably a serial bus. Alternatively, the control channel is a
`4-bit, 8-bit or 16-bit bus. Thus a multimedia data transfer
`initially involves the transfer of control infonnation on the
`dedicated control channel followed by the transfer of the
`periodic data streams on the multimedia bus.
`In a third embodiment, the multimedia bus comprises
`separate channels for ditferent data types. In the preferred
`embodiment, the computer system includes a first video data
`channel for. transferring video and/or graphics information,
`a second audio channel for transfening audio information,
`and optionally a third channel for transferring communica-
`tions information. The video channel is preferably 32 bits,
`24 bits, or 16 bits. Alternatively, the video channel is an 8-bit
`bus or a very high speed serial bus. The audio channel is
`preferably 16 bits or 8 bits. Alternatively, the audio channel
`is also a 32-bit bus or a very high speed serial bus. The
`communications channel is also preferably either 16 or 8
`bits. This third embodiment may use the PCI bus for control
`information transfers, or may use a separate control channel
`separate from the PCI bus and the multimedia bus for
`transferring control
`information for the periodic stream
`transfers.
`
`In a fourth embodiment, each multimedia device has a
`high speed link directly to system memory, which is pref-
`erably single or multiple ported memory. These individual
`links are preferably high speed serial interconnects but,
`alternatively, may be 4-bit, 8-bit, 16-bit, 24-bit, 32-bit,
`64-bit or any combination thereof. In this embodiment,
`intelligent bulfering is preferably implemented within the
`core logic, and arbitration for access to main memory is
`preferably implemented within the core logic. Each of the
`multimedia devices uses its dedicated memory data channel
`to perform data accesses and transfers directly to the main
`memory, bypassing PCI bus arbitration and PCI bus cycles.
`Alternatively, each of the multimedia devices includes a
`high speed memory channel directly to the memory con-
`troller in the core logic for accessing system memory.
`In a fifth embodiment, the multimedia bus is time sliced
`wherein time slices or time slots are allocated in proportion
`to the required bandwidth. In one embodiment, the time
`slices are each a constant size and a number of the equal
`sized time slots are allocated to respective data streams in
`proportion to the required bandwidth. In this embodiment,
`for example, video data streams may be allocated more time
`slots than audio data streams because of the increased data
`transfer band width requirements of video streams.
`Alternatively, the time slots are not equally sized, but rather
`are dynamically sized or allocated to data streams in pro-
`portion to the required bandwidth.
`In a sixth embodiment, multimedia devices that connect
`to the multimedia bus include intelligent controller circuitry
`which includes knowledge of the respective time slice
`allocated to the multimedia device. In this embodiment,
`arbitration for the multimedia bus is not required. Rather, a
`multimedia device which is a transmitter of video data
`monitors the bus and includes controller circuitry which
`begins transmitting the video data when the device’s respec-
`tive time slot occurs. A corresponding receiver device also
`knows that the current time slot is a video time slot and
`monitors the bus to receive the data.
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`In this embodiment, the interface circuitry of each of the
`multimedia devices are programmed at boot time for a static
`allocation of time slots. Alternatively, the interface circuitry
`in the multimedia devices is dynamically programmed by a
`central controller dependent upon the mix of real-time
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`processes and applications and the corresponding data trans-
`fer bandwidth requirements. For example, the CPU may
`program each of the multimedia devices with a respective
`time slot at power-on. Alternatively, the CPU dynamically or
`heuristically allocates time slot based on bandwidth require-
`ments.
`
`In one embodiment of the invention, the computer system
`includes a centralized multimedia I/O processor which oper-
`ates to direct or “pull” data stream information through the
`system. The multimedia I/O processor is programmed with
`lmowledge of the various data rates, data periodicity, data
`sources and destinations, and coordinates all transfers within
`the system. Thus,
`the multimedia I/O processor creates
`connections between two or more devices and sets up
`transfers between devices. The centralized multimedia I/O
`
`processor of the present invention may be used exclusively
`in the multimedia bus or may be used on a standard PCI bus.
`In one embodiment, the centralized multimedia I/O pro-
`cessor byte slices the multimedia bus to allow different data
`streams to use different byte channels simultaneously. Thus
`the byte sliced multimedia bus allows different peripherals
`to share the bus simultaneously. The centralized multimedia
`I/O processor thus may assign one data stream to a subset of
`the total byte lanes on the multimedia bus. and fill the unused
`byte lanes with another data stream. For example, with a
`32-bit multimedia bus, if an audio data stream is only 16 bits
`wide and thus only uses half of the multimedia data bus, the
`multimedia bus intelligently allows data stream transfers on
`the unused bits of the bus. In this embodiment, the central-
`ized multimedia I/O processor includes knowledge of the
`destinations and allows transfers to occur without addressing
`information.
`
`In one embodiment of the invention, the computer system
`includes a multimedia memory coupled to each of the PCI
`local expansion bus and the real-time bus. One or more
`multimedia devices may be coupled to the PCI local expan-
`sion bus and the real-time bus. Each of these devices
`accesses the multimedia memory to retrieve necessary code
`and data to perform respective operations. The multimedia
`devices preferably include an arbitration protocol for access-
`ing the multimedia memory using the real-time bus.
`In one embodiment,
`the system bus (preferably PCI)
`implements a new mode of operation specifically for real-
`t:ime transfers. A signal (or signals) is used to indicate that
`the system bus should be placed in a special real time mode.
`When not in special real time mode, the system bus operates
`as usual. The real time mode is optimized for the transfer of
`high bandwidth real-time information.
`Therefore. the present invention comprises a novel com-
`puter system architecture and method which provides one or
`more real-time or multimedia buses, optionally with a local
`expansion bus, to increase the performance of real-time
`peripherals and applications. The multimedia bus of the
`present invention provides improved data transfers perfor-
`mance and throughput for real-time devices. The various
`embodiments discussed above may be combined in various
`ways for optimum real-time and/or multimedia perfor-
`mance.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A better understanding of the present invention can be
`obtained when the following detailed description of the
`preferred embodiment is considered in conjunction with the
`following drawings, in which:
`FIG. 1 is a block diagram of a computer system including
`a local expansion bus and a real-time bus or multimedia bus
`according to the present invention;
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`FIG. 2 is a block diagram of a multimedia device in the
`computer system of FIG. 1;
`FIG. 3A is a flowchart diagram illustrating a multimedia
`bus transfer which uses the PCI bus for control and address-
`ing information;
`FIG. 3B is a flowchart diagram illustrating a multimedia
`bus transfer which uses both the PCI bus data lines and the
`multimedia bus data lines for improved bandwidth;
`FIG. 3C is a flowchart diagram illustrating a multimedia
`bus transfer optimized for periodic data transfers;
`FIG. 4 is a block diagram of the motherboard of the
`computer system of FIG. 1;
`FIG. 5 illustrates a modular add-in card including a local
`expansion bus connector and a multimedia bus connector
`according to the present invention;
`FIG. 6 is a block diagram of an alternate embodiment of
`the computer system of FIG. 1;
`FIG. 7 is a block diagram of a computer system including
`a local expansion bus and a real-time bus or multimedia bus
`and also including a dedicated control channel according to
`an alternate embodiment of the present invention;
`FIG. 8 is a block diagram of a multimedia device in the
`computer system of FIG. 7;
`FIGS. 9A and 9B are flowchart diagrams illustrating
`multimedia bus transfers in the computer system of FIG. 7;
`FIG. 10 is a block diagram of a computer system includ-
`ing a local expansion bus and separate multimedia channels
`for video, audio, and communications;
`FIG. 11 is a block diagram of an embodiment of the
`multimedia bus interface in the multimedia device of FIGS.
`
`2 or 8 which includes time slot logic according to the present
`invention;
`FIG. 12 illustrates various time slotting techniques;
`FIG. 13 is a block diagram of a computer system includ-
`ing a local expansion bus and a real-time bus or multimedia
`bus and also including a centralized multimedia I/O proces-
`sor;
`
`FIG. 14 is a block diagram of the centralized multimedia
`I/O processor of FIG. 13;
`FIG. 15 is a block diagram of a computer system includ-
`ing a local expansion bus and a real-time bus and including
`a multimedia memory according to an alternate embodiment
`of the present invention;
`FIG. 16 is a block diagram of the motherboard of the
`computer system of FIG. 5;
`FIG. 17 illustrates the address space of the main memory
`and the multimedia memory;
`FIG. 18 is a flowchart diagram illustrating operation of
`data transfers from the main memory to the multimedia
`memory;
`
`FIG. 19 is a block diagram of a computer system includ-
`ing a plurality of high speed memory channels for each
`peripheral device;
`FIG. 20 is a block diagram of a multimedia device or
`multimedia device in the computer system of FIG. 19;
`FIG. 21 is a block diagram of a computer system having
`an expansion bus which includes a multimedia mode for
`high speed multimedia transfers; and
`FIG. 22 is a block diagram of a multimedia device or
`multimedia device in the computer system of FIG. 21.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`Incorporation by Reference
`
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`7
`PCI System Architecture by Tom Shanley and Don Ander-
`son and available from Mindshare Press, 2202 Buttercup
`Dr., Richardson, Tex. 75082 (214) 231-2216,
`is hereby
`incorporated by reference in its entirety.
`The Intel Peripherals Handbook, 1994 and 1995 editions,
`available from Intel Corporation, are hereby incorporated by
`reference in their entirety. Also, data sheets on the Intel
`82430FX PCIset chipset, also referred to as the Triton
`chipset, are hereby incorporated by reference in their
`entirety. including the 82430 Cache Memory Subsystem
`data sheet (Order No. 290482-004), the 82420/82430 PCIset
`ISA and EISA bridge data sheet (Order No. 290483-004),
`and the Intel 82430FX PCIset Product Brief (Order No.
`297559-001). all of which are available from Intel
`Corporation, Literature Sales, P.O. Box 7641. Mt. Prospect,
`I11. 60056-7641 (l—800—879—4683), and all of which are
`hereby incorporated by reference in their entirety.
`The Video Electronics Standards Association (VESA)
`VESA advanced feature connector (VAFC) specification and
`the VESA media channel (VMC) specification are hereby
`incorporated by reference in their entirety.
`The Intel-AII shared frame buffer interconnect (SFBI)
`specification is also hereby incorporated by reference in its
`entirety.
`The PCI Multimedia Design Guide Revision 1.0, dated
`Mar. 29, 1994, as well as later revisions. are hereby incor-
`porated by reference in their entirety.
`'
`Computer System Block Diagram
`Referring now to FIG. 1, a block diagram of a computer
`system according to the present invention is shown. As
`shown. the computer system includes a central processing
`unit (CPU) 102 which is coupled through a CPU local bus
`104 to a host/PCI/cache bridge or chipset 106. The chipset
`106 includes various bridge logic and includes arbitration
`logic 107. The chipset 106 is preferably similar to the Triton
`chipset available from Intel Corporation, including certain
`arbiter modifications to accommodate the real-time bus of
`the present invention. A second level or L2 cache memory
`(not shown) may be coupled to a cache controller in the
`chipset 106. as desired. The bridge or chipset 106 couples
`through a memory bus 108 to main memory 110. The main
`memory 110 is preferably DRAM (dynamic random access
`memory) or EDO (extended data out) memory, or other
`types of memory, as desired.
`The chipset logic 106 preferably includes a memory
`controller for interfacing to the main memory 110 and also
`includes the arbitration logic 107. The chipset logic 106
`preferably includes various peripherals, including an inter-
`rupt system. a real time clock (RFC) and timers, a direct
`memory access (DMA) system. and ROM/Flash memory
`(all not shown). Other peripherals (not shown) are preferably
`comprised in the chipset 106. including communications
`ports. diagnostics ports, command/status registers, and non-
`volatile static random access memory (NVSRAM).
`The host/PCI/cache bridge or chipset 106 also interfaces
`to a local expansion bus or system bus 120. In the preferred
`embodiment, the local expansion bus 120 is the peripheral
`component interconnect (PCI) bus 120. However, it is noted
`that other local buses may be used, such as the VESA (Video
`Electronics Standards Association) VL bus. Various types of
`devices may be connected to the PCI bus 120.
`The computer system shown in FIG. 1 also includes a
`real-time bus. also referred to as a multimedia bus 130. The
`multimedia bus 130 preferably includes a 32 or 64 bit data
`path and may also include address and control portions.
`One or more multimedia devices or multimedia devices
`142. 144. and 146 are coupled to each of the PCI bus 120 and
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`the multimedia bus 130. One or more multimedia devices
`may connect to the PCI bus 120 only. The multimedia
`devices 142-146 include interface circuitry 170 which
`includes standard PCI interface circuitry for communicating
`on the PCI bus 120. For devices which also connect to the
`multimedia bus, the interface circuitry 170 in the multimedia
`devices 142-146 also includes interface logic for interfacing
`to the multimedia bus 130. The multimedia devices 142-146
`use the multimedia bus 130 to communicate data, preferably
`only periodic data, between the respective devices.
`The multimedia devices 142-146 may be any of various
`types of inputloutput devices, including multimedia devices
`and communication devices. For example, the multimedia
`devices 142-146 may comprise video accelerator or graph-
`ics accelerator devices, video playback devices, MPEG
`encoder or decoder devices, sound devices, network inter-
`face devices, SCSI adapters for interfacing to various input/
`output devices, such as CD-KOMS and tape drives, or other
`devices as desired.
`Thus, the multimedia devices 142-146 communicate with
`each other via the PCI bus 120 and also communicate with
`the CPU and main memory 110 via the PCI bus 120, as is
`well known in the art. The multimedia devices 142-146 also
`communicate data between each other using the real—time
`bus or multimedia bus 130. When the multimedia devices
`142-146 communicate using the real-tirne bus 130.
`the
`devices are not required to obtain PCI bus mastership and
`they consume little or no PCI bus cycles.
`Expansion bus bridge logic 150 may also be coupled to
`the PCI bus 120. The expansion bus bridge logic 150
`interfaces to an expansion bus 152. The expansion bus 152
`may be any of varying types, including the industry standard
`architecture (ISA) bus, also referred to as the AT bus, the
`extended industry standard architecture (EISA) bus, or the
`rnicrochannel architecture (MCA) bus. Various devices may
`be coupled to the expansion bus 152, such as expansion bus
`memory or a modern (both not shown).
`Multimedia Devices
`
`Referring now to FIG. 2, a block diagram is shown
`illustrating one of the multimedia devices 142-146, such as
`multimedia device 142. As shown, the multimedia device
`142 includes interface logic 170 comprising PCI interface
`circuitry 172 for communicating on the PCI bus 120 and also
`including multimedia bus interface logic 174 for interfacing
`to the multimedia bus 130. The multimedia device 142 also
`may include a digital signal processor (DSP) 210 or other
`hardware circuitry for implementing a multimedia or com-
`munications function. Each of the multimedia devices
`142-146 preferably includes the interface logic 170, as
`shown in FIG. 2.
`
`The multimedia devices 142-146 preferably use the mul-
`timedia or real-time bus 130 only for high speed data
`transfers of real-time stream data information. In one
`embodiment the multimedia bus 130 transfers only periodic
`stream data, i.e., data streams which require periodic trans-
`fers for multimedia or communication purposes. Examples
`of periodic data include audio data. which is typically
`transmitted at 44,100 samples per second, Video data, which
`is typically transmitted at 30 frames per second, or real-time
`communication streams at rates dependent on the transport
`media. In an alternate embodiment, the multimedia bus 130
`is used for any of various types of multimedia or commu-
`nications data transfers, including both periodic and a peri-
`odic data.
`In the embodiment shown in FIG. 1, the multimedia bus
`130 includes primarily or only data lines, such as a 32 bit or
`64 bit data path, and does not include address or arbitration
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`portions. As discussed above with reference to FIG. 2, the
`multimedia devices 142-146 each include inte